[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-iop32x / iq31244.c

/*
 * arch/arm/mach-iop32x/iq31244.c
 *
 * Board support code for the Intel EP80219 and IQ31244 platforms.
 *
 * Author: Rory Bolt <rorybolt@pacbell.net>
 * Copyright (C) 2002 Rory Bolt
 * Copyright 2003 (c) MontaVista, Software, Inc.
 * Copyright (C) 2004 Intel Corp.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/mm.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/pm.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/arch/time.h>

/*
 * Until March of 2007 iq31244 platforms and ep80219 platforms shared the
 * same machine id, and the processor type was used to select board type.
 * However this assumption breaks for an iq80219 board which is an iop219
 * processor on an iq31244 board.  The force_ep80219 flag has been added
 * for old boot loaders using the iq31244 machine id for an ep80219 platform.
 */
static int force_ep80219;

static int is_80219(void)
{
	extern int processor_id;
	return !!((processor_id & 0xffffffe0) == 0x69052e20);
}

static int is_ep80219(void)
{
	if (machine_is_ep80219() || force_ep80219)
		return 1;
	else
		return 0;
}


/*
 * EP80219/IQ31244 timer tick configuration.
 */
static void __init iq31244_timer_init(void)
{
	if (is_ep80219()) {
		/* 33.333 MHz crystal.  */
		iop_init_time(200000000);
	} else {
		/* 33.000 MHz crystal.  */
		iop_init_time(198000000);
	}
}

static struct sys_timer iq31244_timer = {
	.init		= iq31244_timer_init,
	.offset		= iop_gettimeoffset,
};


/*
 * IQ31244 I/O.
 */
static struct map_desc iq31244_io_desc[] __initdata = {
	{	/* on-board devices */
		.virtual	= IQ31244_UART,
		.pfn		= __phys_to_pfn(IQ31244_UART),
		.length		= 0x00100000,
		.type		= MT_DEVICE,
	},
};

void __init iq31244_map_io(void)
{
	iop3xx_map_io();
	iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
}


/*
 * EP80219/IQ31244 PCI.
 */
static inline int __init
ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq;

	if (slot == 0) {
		/* CFlash */
		irq = IRQ_IOP32X_XINT1;
	} else if (slot == 1) {
		/* 82551 Pro 100 */
		irq = IRQ_IOP32X_XINT0;
	} else if (slot == 2) {
		/* PCI-X Slot */
		irq = IRQ_IOP32X_XINT3;
	} else if (slot == 3) {
		/* SATA */
		irq = IRQ_IOP32X_XINT2;
	} else {
		printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
			"device PCI:%d:%d:%d\n", dev->bus->number,
			PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
		irq = -1;
	}

	return irq;
}

static struct hw_pci ep80219_pci __initdata = {
	.swizzle	= pci_std_swizzle,
	.nr_controllers = 1,
	.setup		= iop3xx_pci_setup,
	.preinit	= iop3xx_pci_preinit,
	.scan		= iop3xx_pci_scan_bus,
	.map_irq	= ep80219_pci_map_irq,
};

static inline int __init
iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq;

	if (slot == 0) {
		/* CFlash */
		irq = IRQ_IOP32X_XINT1;
	} else if (slot == 1) {
		/* SATA */
		irq = IRQ_IOP32X_XINT2;
	} else if (slot == 2) {
		/* PCI-X Slot */
		irq = IRQ_IOP32X_XINT3;
	} else if (slot == 3) {
		/* 82546 GigE */
		irq = IRQ_IOP32X_XINT0;
	} else {
		printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
			"device PCI:%d:%d:%d\n", dev->bus->number,
			PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
		irq = -1;
	}

	return irq;
}

static struct hw_pci iq31244_pci __initdata = {
	.swizzle	= pci_std_swizzle,
	.nr_controllers = 1,
	.setup		= iop3xx_pci_setup,
	.preinit	= iop3xx_pci_preinit,
	.scan		= iop3xx_pci_scan_bus,
	.map_irq	= iq31244_pci_map_irq,
};

static int __init iq31244_pci_init(void)
{
	if (is_ep80219()) {
		if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
			pci_common_init(&ep80219_pci);
	} else if (machine_is_iq31244()) {
		if (is_80219()) {
			printk("note: iq31244 board type has been selected\n");
			printk("note: to select ep80219 operation:\n");
			printk("\t1/ specify \"force_ep80219\" on the kernel"
				" command line\n");
			printk("\t2/ update boot loader to pass"
				" the ep80219 id: %d\n", MACH_TYPE_EP80219);
		}

		if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
			pci_common_init(&iq31244_pci);
	}

	return 0;
}

subsys_initcall(iq31244_pci_init);


/*
 * IQ31244 machine initialisation.
 */
static struct physmap_flash_data iq31244_flash_data = {
	.width		= 2,
};

static struct resource iq31244_flash_resource = {
	.start		= 0xf0000000,
	.end		= 0xf07fffff,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device iq31244_flash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &iq31244_flash_data,
	},
	.num_resources	= 1,
	.resource	= &iq31244_flash_resource,
};

static struct plat_serial8250_port iq31244_serial_port[] = {
	{
		.mapbase	= IQ31244_UART,
		.membase	= (char *)IQ31244_UART,
		.irq		= IRQ_IOP32X_XINT1,
		.flags		= UPF_SKIP_TEST,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= 1843200,
	},
	{ },
};

static struct resource iq31244_uart_resource = {
	.start		= IQ31244_UART,
	.end		= IQ31244_UART + 7,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device iq31244_serial_device = {
	.name		= "serial8250",
	.id		= PLAT8250_DEV_PLATFORM,
	.dev		= {
		.platform_data		= iq31244_serial_port,
	},
	.num_resources	= 1,
	.resource	= &iq31244_uart_resource,
};

/*
 * This function will send a SHUTDOWN_COMPLETE message to the PIC
 * controller over I2C.  We are not using the i2c subsystem since
 * we are going to power off and it may be removed
 */
void ep80219_power_off(void)
{
	/*
	 * Send the Address byte w/ the start condition
	 */
	*IOP3XX_IDBR1 = 0x60;
	*IOP3XX_ICR1 = 0xE9;
	mdelay(1);

	/*
	 * Send the START_MSG byte w/ no start or stop condition
	 */
	*IOP3XX_IDBR1 = 0x0F;
	*IOP3XX_ICR1 = 0xE8;
	mdelay(1);

	/*
	 * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
	 * stop condition
	 */
	*IOP3XX_IDBR1 = 0x03;
	*IOP3XX_ICR1 = 0xE8;
	mdelay(1);

	/*
	 * Send an ignored byte w/ stop condition
	 */
	*IOP3XX_IDBR1 = 0x00;
	*IOP3XX_ICR1 = 0xEA;

	while (1)
		;
}

static void __init iq31244_init_machine(void)
{
	platform_device_register(&iop3xx_i2c0_device);
	platform_device_register(&iop3xx_i2c1_device);
	platform_device_register(&iq31244_flash_device);
	platform_device_register(&iq31244_serial_device);

	if (is_ep80219())
		pm_power_off = ep80219_power_off;
}

static int __init force_ep80219_setup(char *str)
{
	force_ep80219 = 1;
	return 1;
}

__setup("force_ep80219", force_ep80219_setup);

MACHINE_START(IQ31244, "Intel IQ31244")
	/* Maintainer: Intel Corp. */
	.phys_io	= IQ31244_UART,
	.io_pg_offst	= ((IQ31244_UART) >> 18) & 0xfffc,
	.boot_params	= 0xa0000100,
	.map_io		= iq31244_map_io,
	.init_irq	= iop32x_init_irq,
	.timer		= &iq31244_timer,
	.init_machine	= iq31244_init_machine,
MACHINE_END

/* There should have been an ep80219 machine identifier from the beginning.
 * Boot roms older than March 2007 do not know the ep80219 machine id.  Pass
 * "force_ep80219" on the kernel command line, otherwise iq31244 operation
 * will be selected.
 */
MACHINE_START(EP80219, "Intel EP80219")
	/* Maintainer: Intel Corp. */
	.phys_io	= IQ31244_UART,
	.io_pg_offst	= ((IQ31244_UART) >> 18) & 0xfffc,
	.boot_params	= 0xa0000100,
	.map_io		= iq31244_map_io,
	.init_irq	= iop32x_init_irq,
	.timer		= &iq31244_timer,
	.init_machine	= iq31244_init_machine,
MACHINE_END
Commit	Line	Data
c680b77e LB	1	/*
	2	* arch/arm/mach-iop32x/iq31244.c
	3	*
	4	* Board support code for the Intel EP80219 and IQ31244 platforms.
	5	*
	6	* Author: Rory Bolt <rorybolt@pacbell.net>
	7	* Copyright (C) 2002 Rory Bolt
	8	* Copyright 2003 (c) MontaVista, Software, Inc.
	9	* Copyright (C) 2004 Intel Corp.
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
	15	*/
	16
	17	#include <linux/mm.h>
	18	#include <linux/init.h>
	19	#include <linux/delay.h>
	20	#include <linux/kernel.h>
	21	#include <linux/pci.h>
	22	#include <linux/pm.h>
	23	#include <linux/string.h>
	24	#include <linux/slab.h>
	25	#include <linux/serial_core.h>
	26	#include <linux/serial_8250.h>
	27	#include <linux/mtd/physmap.h>
	28	#include <linux/platform_device.h>
	29	#include <asm/hardware.h>
	30	#include <asm/io.h>
	31	#include <asm/irq.h>
	32	#include <asm/mach/arch.h>
	33	#include <asm/mach/map.h>
	34	#include <asm/mach/pci.h>
	35	#include <asm/mach/time.h>
	36	#include <asm/mach-types.h>
	37	#include <asm/page.h>
	38	#include <asm/pgtable.h>
3668b45d	39	#include <asm/arch/time.h>
c680b77e LB	40
c680b77e LB	41	/*
094f1275 DW	42	* Until March of 2007 iq31244 platforms and ep80219 platforms shared the
	43	* same machine id, and the processor type was used to select board type.
	44	* However this assumption breaks for an iq80219 board which is an iop219
	45	* processor on an iq31244 board. The force_ep80219 flag has been added
	46	* for old boot loaders using the iq31244 machine id for an ep80219 platform.
c680b77e	47	*/
094f1275 DW	48	static int force_ep80219;
094f1275 DW	49
c680b77e LB	50	static int is_80219(void)
	51	{
	52	extern int processor_id;
	53	return !!((processor_id & 0xffffffe0) == 0x69052e20);
	54	}
	55
094f1275 DW	56	static int is_ep80219(void)
	57	{
	58	if (machine_is_ep80219() \|\| force_ep80219)
	59	return 1;
	60	else
	61	return 0;
	62	}
	63
c680b77e LB	64
	65	/*
	66	* EP80219/IQ31244 timer tick configuration.
	67	*/
	68	static void __init iq31244_timer_init(void)
	69	{
094f1275	70	if (is_ep80219()) {
c680b77e	71	/* 33.333 MHz crystal. */
3668b45d	72	iop_init_time(200000000);
c680b77e LB	73	} else {
c680b77e LB	74	/* 33.000 MHz crystal. */
3668b45d	75	iop_init_time(198000000);
c680b77e LB	76	}
	77	}
	78
	79	static struct sys_timer iq31244_timer = {
	80	.init = iq31244_timer_init,
3668b45d	81	.offset = iop_gettimeoffset,
c680b77e LB	82	};
	83
	84
	85	/*
	86	* IQ31244 I/O.
	87	*/
	88	static struct map_desc iq31244_io_desc[] __initdata = {
	89	{ /* on-board devices */
	90	.virtual = IQ31244_UART,
	91	.pfn = __phys_to_pfn(IQ31244_UART),
	92	.length = 0x00100000,
	93	.type = MT_DEVICE,
	94	},
	95	};
	96
	97	void __init iq31244_map_io(void)
	98	{
	99	iop3xx_map_io();
	100	iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
	101	}
	102
	103
	104	/*
	105	* EP80219/IQ31244 PCI.
	106	*/
	107	static inline int __init
	108	ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	109	{
	110	int irq;
	111
	112	if (slot == 0) {
	113	/* CFlash */
c852ac80	114	irq = IRQ_IOP32X_XINT1;
c680b77e LB	115	} else if (slot == 1) {
c680b77e LB	116	/* 82551 Pro 100 */
c852ac80	117	irq = IRQ_IOP32X_XINT0;
c680b77e LB	118	} else if (slot == 2) {
c680b77e LB	119	/* PCI-X Slot */
c852ac80	120	irq = IRQ_IOP32X_XINT3;
c680b77e LB	121	} else if (slot == 3) {
c680b77e LB	122	/* SATA */
c852ac80	123	irq = IRQ_IOP32X_XINT2;
c680b77e LB	124	} else {
	125	printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
	126	"device PCI:%d:%d:%d\n", dev->bus->number,
	127	PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
	128	irq = -1;
	129	}
	130
	131	return irq;
	132	}
	133
	134	static struct hw_pci ep80219_pci __initdata = {
	135	.swizzle = pci_std_swizzle,
	136	.nr_controllers = 1,
	137	.setup = iop3xx_pci_setup,
	138	.preinit = iop3xx_pci_preinit,
	139	.scan = iop3xx_pci_scan_bus,
	140	.map_irq = ep80219_pci_map_irq,
	141	};
	142
	143	static inline int __init
	144	iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	145	{
	146	int irq;
	147
	148	if (slot == 0) {
	149	/* CFlash */
c852ac80	150	irq = IRQ_IOP32X_XINT1;
c680b77e LB	151	} else if (slot == 1) {
c680b77e LB	152	/* SATA */
c852ac80	153	irq = IRQ_IOP32X_XINT2;
c680b77e LB	154	} else if (slot == 2) {
c680b77e LB	155	/* PCI-X Slot */
c852ac80	156	irq = IRQ_IOP32X_XINT3;
c680b77e LB	157	} else if (slot == 3) {
c680b77e LB	158	/* 82546 GigE */
c852ac80	159	irq = IRQ_IOP32X_XINT0;
c680b77e	160	} else {
c852ac80	161	printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
c680b77e LB	162	"device PCI:%d:%d:%d\n", dev->bus->number,
	163	PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
	164	irq = -1;
	165	}
	166
	167	return irq;
	168	}
	169
	170	static struct hw_pci iq31244_pci __initdata = {
	171	.swizzle = pci_std_swizzle,
	172	.nr_controllers = 1,
	173	.setup = iop3xx_pci_setup,
	174	.preinit = iop3xx_pci_preinit,
	175	.scan = iop3xx_pci_scan_bus,
	176	.map_irq = iq31244_pci_map_irq,
	177	};
	178
	179	static int __init iq31244_pci_init(void)
	180	{
e90ddd81 DW	181	if (is_ep80219()) {
	182	if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
	183	pci_common_init(&ep80219_pci);
	184	} else if (machine_is_iq31244()) {
c680b77e	185	if (is_80219()) {
094f1275 DW	186	printk("note: iq31244 board type has been selected\n");
	187	printk("note: to select ep80219 operation:\n");
	188	printk("\t1/ specify \"force_ep80219\" on the kernel"
	189	" command line\n");
	190	printk("\t2/ update boot loader to pass"
	191	" the ep80219 id: %d\n", MACH_TYPE_EP80219);
c680b77e	192	}
e90ddd81 DW	193
	194	if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
	195	pci_common_init(&iq31244_pci);
c680b77e LB	196	}
	197
	198	return 0;
	199	}
	200
	201	subsys_initcall(iq31244_pci_init);
	202
	203
	204	/*
	205	* IQ31244 machine initialisation.
	206	*/
	207	static struct physmap_flash_data iq31244_flash_data = {
	208	.width = 2,
	209	};
	210
	211	static struct resource iq31244_flash_resource = {
	212	.start = 0xf0000000,
	213	.end = 0xf07fffff,
	214	.flags = IORESOURCE_MEM,
	215	};
	216
	217	static struct platform_device iq31244_flash_device = {
	218	.name = "physmap-flash",
	219	.id = 0,
	220	.dev = {
	221	.platform_data = &iq31244_flash_data,
	222	},
	223	.num_resources = 1,
	224	.resource = &iq31244_flash_resource,
	225	};
	226
	227	static struct plat_serial8250_port iq31244_serial_port[] = {
	228	{
	229	.mapbase = IQ31244_UART,
	230	.membase = (char *)IQ31244_UART,
c852ac80	231	.irq = IRQ_IOP32X_XINT1,
c680b77e LB	232	.flags = UPF_SKIP_TEST,
	233	.iotype = UPIO_MEM,
	234	.regshift = 0,
	235	.uartclk = 1843200,
	236	},
	237	{ },
	238	};
	239
	240	static struct resource iq31244_uart_resource = {
	241	.start = IQ31244_UART,
	242	.end = IQ31244_UART + 7,
	243	.flags = IORESOURCE_MEM,
	244	};
	245
	246	static struct platform_device iq31244_serial_device = {
	247	.name = "serial8250",
	248	.id = PLAT8250_DEV_PLATFORM,
	249	.dev = {
	250	.platform_data = iq31244_serial_port,
	251	},
	252	.num_resources = 1,
	253	.resource = &iq31244_uart_resource,
	254	};
	255
	256	/*
	257	* This function will send a SHUTDOWN_COMPLETE message to the PIC
	258	* controller over I2C. We are not using the i2c subsystem since
	259	* we are going to power off and it may be removed
	260	*/
	261	void ep80219_power_off(void)
	262	{
	263	/*
	264	* Send the Address byte w/ the start condition
	265	*/
	266	*IOP3XX_IDBR1 = 0x60;
	267	*IOP3XX_ICR1 = 0xE9;
	268	mdelay(1);
	269
	270	/*
	271	* Send the START_MSG byte w/ no start or stop condition
	272	*/
	273	*IOP3XX_IDBR1 = 0x0F;
	274	*IOP3XX_ICR1 = 0xE8;
	275	mdelay(1);
	276
	277	/*
	278	* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
	279	* stop condition
	280	*/
	281	*IOP3XX_IDBR1 = 0x03;
	282	*IOP3XX_ICR1 = 0xE8;
	283	mdelay(1);
	284
	285	/*
	286	* Send an ignored byte w/ stop condition
	287	*/
	288	*IOP3XX_IDBR1 = 0x00;
	289	*IOP3XX_ICR1 = 0xEA;
	290
	291	while (1)
	292	;
	293	}
	294
	295	static void __init iq31244_init_machine(void)
296	{
297	platform_device_register(&iop3xx_i2c0_device);
298	platform_device_register(&iop3xx_i2c1_device);
299	platform_device_register(&iq31244_flash_device);
300	platform_device_register(&iq31244_serial_device);
301
094f1275	302	if (is_ep80219())
c680b77e LB	303	pm_power_off = ep80219_power_off;
	304	}
	305
094f1275 DW	306	static int __init force_ep80219_setup(char *str)
	307	{
	308	force_ep80219 = 1;
	309	return 1;
	310	}
	311
	312	__setup("force_ep80219", force_ep80219_setup);
	313
c680b77e LB	314	MACHINE_START(IQ31244, "Intel IQ31244")
	315	/* Maintainer: Intel Corp. */
	316	.phys_io = IQ31244_UART,
	317	.io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
	318	.boot_params = 0xa0000100,
	319	.map_io = iq31244_map_io,
c852ac80	320	.init_irq = iop32x_init_irq,
c680b77e LB	321	.timer = &iq31244_timer,
	322	.init_machine = iq31244_init_machine,
	323	MACHINE_END
094f1275 DW	324
	325	/* There should have been an ep80219 machine identifier from the beginning.
	326	* Boot roms older than March 2007 do not know the ep80219 machine id. Pass
	327	* "force_ep80219" on the kernel command line, otherwise iq31244 operation
	328	* will be selected.
	329	*/
	330	MACHINE_START(EP80219, "Intel EP80219")
	331	/* Maintainer: Intel Corp. */
	332	.phys_io = IQ31244_UART,
	333	.io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
	334	.boot_params = 0xa0000100,
	335	.map_io = iq31244_map_io,
	336	.init_irq = iop32x_init_irq,
	337	.timer = &iq31244_timer,
	338	.init_machine = iq31244_init_machine,
	339	MACHINE_END