Commit | Line | Data |
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c680b77e LB |
1 | /* |
2 | * arch/arm/mach-iop32x/iq31244.c | |
3 | * | |
4 | * Board support code for the Intel EP80219 and IQ31244 platforms. | |
5 | * | |
6 | * Author: Rory Bolt <rorybolt@pacbell.net> | |
7 | * Copyright (C) 2002 Rory Bolt | |
8 | * Copyright 2003 (c) MontaVista, Software, Inc. | |
9 | * Copyright (C) 2004 Intel Corp. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | */ | |
16 | ||
17 | #include <linux/mm.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/pm.h> | |
23 | #include <linux/string.h> | |
c680b77e LB |
24 | #include <linux/serial_core.h> |
25 | #include <linux/serial_8250.h> | |
26 | #include <linux/mtd/physmap.h> | |
27 | #include <linux/platform_device.h> | |
fced80c7 | 28 | #include <linux/io.h> |
a09e64fb | 29 | #include <mach/hardware.h> |
0ba8b9b2 | 30 | #include <asm/cputype.h> |
c680b77e LB |
31 | #include <asm/irq.h> |
32 | #include <asm/mach/arch.h> | |
33 | #include <asm/mach/map.h> | |
34 | #include <asm/mach/pci.h> | |
35 | #include <asm/mach/time.h> | |
36 | #include <asm/mach-types.h> | |
37 | #include <asm/page.h> | |
38 | #include <asm/pgtable.h> | |
a09e64fb | 39 | #include <mach/time.h> |
c680b77e LB |
40 | |
41 | /* | |
094f1275 DW |
42 | * Until March of 2007 iq31244 platforms and ep80219 platforms shared the |
43 | * same machine id, and the processor type was used to select board type. | |
44 | * However this assumption breaks for an iq80219 board which is an iop219 | |
45 | * processor on an iq31244 board. The force_ep80219 flag has been added | |
46 | * for old boot loaders using the iq31244 machine id for an ep80219 platform. | |
c680b77e | 47 | */ |
094f1275 DW |
48 | static int force_ep80219; |
49 | ||
c680b77e LB |
50 | static int is_80219(void) |
51 | { | |
0ba8b9b2 | 52 | return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20); |
c680b77e LB |
53 | } |
54 | ||
094f1275 DW |
55 | static int is_ep80219(void) |
56 | { | |
57 | if (machine_is_ep80219() || force_ep80219) | |
58 | return 1; | |
59 | else | |
60 | return 0; | |
61 | } | |
62 | ||
c680b77e LB |
63 | |
64 | /* | |
65 | * EP80219/IQ31244 timer tick configuration. | |
66 | */ | |
67 | static void __init iq31244_timer_init(void) | |
68 | { | |
094f1275 | 69 | if (is_ep80219()) { |
c680b77e | 70 | /* 33.333 MHz crystal. */ |
3668b45d | 71 | iop_init_time(200000000); |
c680b77e LB |
72 | } else { |
73 | /* 33.000 MHz crystal. */ | |
3668b45d | 74 | iop_init_time(198000000); |
c680b77e LB |
75 | } |
76 | } | |
77 | ||
78 | static struct sys_timer iq31244_timer = { | |
79 | .init = iq31244_timer_init, | |
c680b77e LB |
80 | }; |
81 | ||
82 | ||
83 | /* | |
84 | * IQ31244 I/O. | |
85 | */ | |
86 | static struct map_desc iq31244_io_desc[] __initdata = { | |
87 | { /* on-board devices */ | |
88 | .virtual = IQ31244_UART, | |
89 | .pfn = __phys_to_pfn(IQ31244_UART), | |
90 | .length = 0x00100000, | |
91 | .type = MT_DEVICE, | |
92 | }, | |
93 | }; | |
94 | ||
95 | void __init iq31244_map_io(void) | |
96 | { | |
97 | iop3xx_map_io(); | |
98 | iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc)); | |
99 | } | |
100 | ||
101 | ||
102 | /* | |
103 | * EP80219/IQ31244 PCI. | |
104 | */ | |
d73d8011 | 105 | static int __init |
c680b77e LB |
106 | ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
107 | { | |
108 | int irq; | |
109 | ||
110 | if (slot == 0) { | |
111 | /* CFlash */ | |
c852ac80 | 112 | irq = IRQ_IOP32X_XINT1; |
c680b77e LB |
113 | } else if (slot == 1) { |
114 | /* 82551 Pro 100 */ | |
c852ac80 | 115 | irq = IRQ_IOP32X_XINT0; |
c680b77e LB |
116 | } else if (slot == 2) { |
117 | /* PCI-X Slot */ | |
c852ac80 | 118 | irq = IRQ_IOP32X_XINT3; |
c680b77e LB |
119 | } else if (slot == 3) { |
120 | /* SATA */ | |
c852ac80 | 121 | irq = IRQ_IOP32X_XINT2; |
c680b77e LB |
122 | } else { |
123 | printk(KERN_ERR "ep80219_pci_map_irq() called for unknown " | |
124 | "device PCI:%d:%d:%d\n", dev->bus->number, | |
125 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); | |
126 | irq = -1; | |
127 | } | |
128 | ||
129 | return irq; | |
130 | } | |
131 | ||
132 | static struct hw_pci ep80219_pci __initdata = { | |
133 | .swizzle = pci_std_swizzle, | |
134 | .nr_controllers = 1, | |
135 | .setup = iop3xx_pci_setup, | |
136 | .preinit = iop3xx_pci_preinit, | |
137 | .scan = iop3xx_pci_scan_bus, | |
138 | .map_irq = ep80219_pci_map_irq, | |
139 | }; | |
140 | ||
d73d8011 | 141 | static int __init |
c680b77e LB |
142 | iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
143 | { | |
144 | int irq; | |
145 | ||
146 | if (slot == 0) { | |
147 | /* CFlash */ | |
c852ac80 | 148 | irq = IRQ_IOP32X_XINT1; |
c680b77e LB |
149 | } else if (slot == 1) { |
150 | /* SATA */ | |
c852ac80 | 151 | irq = IRQ_IOP32X_XINT2; |
c680b77e LB |
152 | } else if (slot == 2) { |
153 | /* PCI-X Slot */ | |
c852ac80 | 154 | irq = IRQ_IOP32X_XINT3; |
c680b77e LB |
155 | } else if (slot == 3) { |
156 | /* 82546 GigE */ | |
c852ac80 | 157 | irq = IRQ_IOP32X_XINT0; |
c680b77e | 158 | } else { |
c852ac80 | 159 | printk(KERN_ERR "iq31244_pci_map_irq called for unknown " |
c680b77e LB |
160 | "device PCI:%d:%d:%d\n", dev->bus->number, |
161 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); | |
162 | irq = -1; | |
163 | } | |
164 | ||
165 | return irq; | |
166 | } | |
167 | ||
168 | static struct hw_pci iq31244_pci __initdata = { | |
169 | .swizzle = pci_std_swizzle, | |
170 | .nr_controllers = 1, | |
171 | .setup = iop3xx_pci_setup, | |
172 | .preinit = iop3xx_pci_preinit, | |
173 | .scan = iop3xx_pci_scan_bus, | |
174 | .map_irq = iq31244_pci_map_irq, | |
175 | }; | |
176 | ||
177 | static int __init iq31244_pci_init(void) | |
178 | { | |
c34002c1 DW |
179 | if (is_ep80219()) |
180 | pci_common_init(&ep80219_pci); | |
181 | else if (machine_is_iq31244()) { | |
c680b77e | 182 | if (is_80219()) { |
094f1275 DW |
183 | printk("note: iq31244 board type has been selected\n"); |
184 | printk("note: to select ep80219 operation:\n"); | |
185 | printk("\t1/ specify \"force_ep80219\" on the kernel" | |
186 | " command line\n"); | |
187 | printk("\t2/ update boot loader to pass" | |
188 | " the ep80219 id: %d\n", MACH_TYPE_EP80219); | |
c680b77e | 189 | } |
c34002c1 | 190 | pci_common_init(&iq31244_pci); |
c680b77e LB |
191 | } |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | subsys_initcall(iq31244_pci_init); | |
197 | ||
198 | ||
199 | /* | |
200 | * IQ31244 machine initialisation. | |
201 | */ | |
202 | static struct physmap_flash_data iq31244_flash_data = { | |
203 | .width = 2, | |
204 | }; | |
205 | ||
206 | static struct resource iq31244_flash_resource = { | |
207 | .start = 0xf0000000, | |
208 | .end = 0xf07fffff, | |
209 | .flags = IORESOURCE_MEM, | |
210 | }; | |
211 | ||
212 | static struct platform_device iq31244_flash_device = { | |
213 | .name = "physmap-flash", | |
214 | .id = 0, | |
215 | .dev = { | |
216 | .platform_data = &iq31244_flash_data, | |
217 | }, | |
218 | .num_resources = 1, | |
219 | .resource = &iq31244_flash_resource, | |
220 | }; | |
221 | ||
222 | static struct plat_serial8250_port iq31244_serial_port[] = { | |
223 | { | |
224 | .mapbase = IQ31244_UART, | |
225 | .membase = (char *)IQ31244_UART, | |
c852ac80 | 226 | .irq = IRQ_IOP32X_XINT1, |
c680b77e LB |
227 | .flags = UPF_SKIP_TEST, |
228 | .iotype = UPIO_MEM, | |
229 | .regshift = 0, | |
230 | .uartclk = 1843200, | |
231 | }, | |
232 | { }, | |
233 | }; | |
234 | ||
235 | static struct resource iq31244_uart_resource = { | |
236 | .start = IQ31244_UART, | |
237 | .end = IQ31244_UART + 7, | |
238 | .flags = IORESOURCE_MEM, | |
239 | }; | |
240 | ||
241 | static struct platform_device iq31244_serial_device = { | |
242 | .name = "serial8250", | |
243 | .id = PLAT8250_DEV_PLATFORM, | |
244 | .dev = { | |
245 | .platform_data = iq31244_serial_port, | |
246 | }, | |
247 | .num_resources = 1, | |
248 | .resource = &iq31244_uart_resource, | |
249 | }; | |
250 | ||
251 | /* | |
252 | * This function will send a SHUTDOWN_COMPLETE message to the PIC | |
253 | * controller over I2C. We are not using the i2c subsystem since | |
254 | * we are going to power off and it may be removed | |
255 | */ | |
256 | void ep80219_power_off(void) | |
257 | { | |
258 | /* | |
259 | * Send the Address byte w/ the start condition | |
260 | */ | |
261 | *IOP3XX_IDBR1 = 0x60; | |
262 | *IOP3XX_ICR1 = 0xE9; | |
263 | mdelay(1); | |
264 | ||
265 | /* | |
266 | * Send the START_MSG byte w/ no start or stop condition | |
267 | */ | |
268 | *IOP3XX_IDBR1 = 0x0F; | |
269 | *IOP3XX_ICR1 = 0xE8; | |
270 | mdelay(1); | |
271 | ||
272 | /* | |
273 | * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or | |
274 | * stop condition | |
275 | */ | |
276 | *IOP3XX_IDBR1 = 0x03; | |
277 | *IOP3XX_ICR1 = 0xE8; | |
278 | mdelay(1); | |
279 | ||
280 | /* | |
281 | * Send an ignored byte w/ stop condition | |
282 | */ | |
283 | *IOP3XX_IDBR1 = 0x00; | |
284 | *IOP3XX_ICR1 = 0xEA; | |
285 | ||
286 | while (1) | |
287 | ; | |
288 | } | |
289 | ||
290 | static void __init iq31244_init_machine(void) | |
291 | { | |
292 | platform_device_register(&iop3xx_i2c0_device); | |
293 | platform_device_register(&iop3xx_i2c1_device); | |
294 | platform_device_register(&iq31244_flash_device); | |
295 | platform_device_register(&iq31244_serial_device); | |
2492c845 DW |
296 | platform_device_register(&iop3xx_dma_0_channel); |
297 | platform_device_register(&iop3xx_dma_1_channel); | |
c680b77e | 298 | |
094f1275 | 299 | if (is_ep80219()) |
c680b77e | 300 | pm_power_off = ep80219_power_off; |
2492c845 DW |
301 | |
302 | if (!is_80219()) | |
303 | platform_device_register(&iop3xx_aau_channel); | |
c680b77e LB |
304 | } |
305 | ||
094f1275 DW |
306 | static int __init force_ep80219_setup(char *str) |
307 | { | |
308 | force_ep80219 = 1; | |
309 | return 1; | |
310 | } | |
311 | ||
312 | __setup("force_ep80219", force_ep80219_setup); | |
313 | ||
c680b77e LB |
314 | MACHINE_START(IQ31244, "Intel IQ31244") |
315 | /* Maintainer: Intel Corp. */ | |
c680b77e LB |
316 | .boot_params = 0xa0000100, |
317 | .map_io = iq31244_map_io, | |
c852ac80 | 318 | .init_irq = iop32x_init_irq, |
c680b77e LB |
319 | .timer = &iq31244_timer, |
320 | .init_machine = iq31244_init_machine, | |
321 | MACHINE_END | |
094f1275 DW |
322 | |
323 | /* There should have been an ep80219 machine identifier from the beginning. | |
324 | * Boot roms older than March 2007 do not know the ep80219 machine id. Pass | |
325 | * "force_ep80219" on the kernel command line, otherwise iq31244 operation | |
326 | * will be selected. | |
327 | */ | |
328 | MACHINE_START(EP80219, "Intel EP80219") | |
329 | /* Maintainer: Intel Corp. */ | |
094f1275 DW |
330 | .boot_params = 0xa0000100, |
331 | .map_io = iq31244_map_io, | |
332 | .init_irq = iop32x_init_irq, | |
333 | .timer = &iq31244_timer, | |
334 | .init_machine = iq31244_init_machine, | |
335 | MACHINE_END |