projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[ARM] mm 9: add additional device memory types
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-iop13xx / pci.c
CommitLineData
285f5fa7
DW		 1/*
2 * iop13xx PCI support
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19
20#include <linux/pci.h>
21#include <linux/delay.h>
22
23#include <asm/irq.h>
24#include <asm/hardware.h>
25#include <asm/sizes.h>
26#include <asm/mach/pci.h>
27#include <asm/arch/pci.h>
28
29#define IOP13XX_PCI_DEBUG 0
30#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
31
32u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
33u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
34static struct pci_bus *pci_bus_atux = 0;
35static struct pci_bus *pci_bus_atue = 0;
36u32 iop13xx_atue_mem_base;
37u32 iop13xx_atux_mem_base;
38size_t iop13xx_atue_mem_size;
39size_t iop13xx_atux_mem_size;
40unsigned long iop13xx_pcibios_min_io = 0;
41unsigned long iop13xx_pcibios_min_mem = 0;
42
43EXPORT_SYMBOL(iop13xx_atue_mem_base);
44EXPORT_SYMBOL(iop13xx_atux_mem_base);
45EXPORT_SYMBOL(iop13xx_atue_mem_size);
46EXPORT_SYMBOL(iop13xx_atux_mem_size);
47
48int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
49static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
50 access */
51
52/* Scan the initialized busses and ioremap the requested memory range
53 */
54void iop13xx_map_pci_memory(void)
55{
56 int atu;
57 struct pci_bus *bus;
58 struct pci_dev *dev;
59 resource_size_t end = 0;
60
61 for (atu = 0; atu < 2; atu++) {
62 bus = atu ? pci_bus_atue : pci_bus_atux;
63 if (bus) {
64 list_for_each_entry(dev, &bus->devices, bus_list) {
65 int i;
66 int max = 7;
67
68 if (dev->subordinate)
69 max = DEVICE_COUNT_RESOURCE;
70
71 for (i = 0; i < max; i++) {
72 struct resource *res = &dev->resource[i];
73 if (res->flags & IORESOURCE_MEM)
74 end = max(res->end, end);
75 }
76 }
77
78 switch(atu) {
79 case 0:
80 iop13xx_atux_mem_size =
81 (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
82
83 /* 16MB align the request */
84 if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
85 iop13xx_atux_mem_size &= ~(SZ_16M - 1);
86 iop13xx_atux_mem_size += SZ_16M;
87 }
88
89 if (end) {
90 iop13xx_atux_mem_base =
91 (u32) __ioremap_pfn(
92 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
93 , 0, iop13xx_atux_mem_size, 0);
94 if (!iop13xx_atux_mem_base) {
95 printk("%s: atux allocation "
96 "failed\n", __FUNCTION__);
97 BUG();
98 }
99 } else
100 iop13xx_atux_mem_size = 0;
101 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
102 __FUNCTION__, atu, iop13xx_atux_mem_size,
103 iop13xx_atux_mem_base);
104 break;
105 case 1:
106 iop13xx_atue_mem_size =
107 (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
108
109 /* 16MB align the request */
110 if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
111 iop13xx_atue_mem_size &= ~(SZ_16M - 1);
112 iop13xx_atue_mem_size += SZ_16M;
113 }
114
115 if (end) {
116 iop13xx_atue_mem_base =
117 (u32) __ioremap_pfn(
118 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
119 , 0, iop13xx_atue_mem_size, 0);
120 if (!iop13xx_atue_mem_base) {
121 printk("%s: atue allocation "
122 "failed\n", __FUNCTION__);
123 BUG();
124 }
125 } else
126 iop13xx_atue_mem_size = 0;
127 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
128 __FUNCTION__, atu, iop13xx_atue_mem_size,
129 iop13xx_atue_mem_base);
130 break;
131 }
132
133 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
134 atu ? "ATUE" : "ATUX",
135 (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
136 SZ_1M,
137 atu ? IOP13XX_PCIE_LOWER_MEM_RA :
138 IOP13XX_PCIX_LOWER_MEM_RA,
139 atu ? iop13xx_atue_mem_base :
140 iop13xx_atux_mem_base);
141 end = 0;
142 }
143
144 }
145}
146
147static inline int iop13xx_atu_function(int atu)
148{
149 int func = 0;
150 /* the function number depends on the value of the
151 * IOP13XX_INTERFACE_SEL_PCIX reset strap
152 * see C-Spec section 3.17
153 */
154 switch(atu) {
155 case IOP13XX_INIT_ATU_ATUX:
156 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
157 func = 5;
158 else
159 func = 0;
160 break;
161 case IOP13XX_INIT_ATU_ATUE:
162 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
163 func = 0;
164 else
165 func = 5;
166 break;
167 default:
168 BUG();
169 }
170
171 return func;
172}
173
174/* iop13xx_atux_cfg_address - format a configuration address for atux
175 * @bus: Target bus to access
176 * @devfn: Combined device number and function number
177 * @where: Desired register's address offset
178 *
179 * Convert the parameters to a configuration address formatted
180 * according the PCI-X 2.0 specification
181 */
182static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
183{
184 struct pci_sys_data *sys = bus->sysdata;
185 u32 addr;
186
187 if (sys->busnr == bus->number)
188 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
189 else
190 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
191
192 addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
193 addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */
194
195 return addr;
196}
197
198/* iop13xx_atue_cfg_address - format a configuration address for atue
199 * @bus: Target bus to access
200 * @devfn: Combined device number and function number
201 * @where: Desired register's address offset
202 *
203 * Convert the parameters to an address usable by the ATUE_OCCAR
204 */
205static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
206{
207 struct pci_sys_data *sys = bus->sysdata;
208 u32 addr;
209
210 PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
211 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
212 addr = ((u32) bus->number) << IOP13XX_ATUE_OCCAR_BUS_NUM |
213 ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
214 ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
215 (where & ~0x3);
216
217 if (sys->busnr != bus->number)
218 addr |= 1; /* type 1 access */
219
220 return addr;
221}
222
223/* This routine checks the status of the last configuration cycle. If an error
224 * was detected it returns >0, else it returns a 0. The errors being checked
225 * are parity, master abort, target abort (master and target). These types of
226 * errors occure during a config cycle where there is no device, like during
227 * the discovery stage.
228 */
229static int iop13xx_atux_pci_status(int clear)
230{
231 unsigned int status;
232 int err = 0;
233
234 /*
235 * Check the status registers.
236 */
237 status = __raw_readw(IOP13XX_ATUX_ATUSR);
238 if (status & IOP_PCI_STATUS_ERROR)
239 {
240 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
241 if(clear)
242 __raw_writew(status & IOP_PCI_STATUS_ERROR,
243 IOP13XX_ATUX_ATUSR);
244 err = 1;
245 }
246 status = __raw_readl(IOP13XX_ATUX_ATUISR);
247 if (status & IOP13XX_ATUX_ATUISR_ERROR)
248 {
249 PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status);
250 if(clear)
251 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
252 IOP13XX_ATUX_ATUISR);
253 err = 1;
254 }
255 return err;
256}
257
258/* Simply write the address register and read the configuration
259 * data. Note that the data dependency on %0 encourages an abort
260 * to be detected before we return.
261 */
262static inline u32 iop13xx_atux_read(unsigned long addr)
263{
264 u32 val;
265
266 __asm__ __volatile__(
267 "str %1, [%2]\n\t"
268 "ldr %0, [%3]\n\t"
269 "mov %0, %0\n\t"
270 : "=r" (val)
271 : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
272
273 return val;
274}
275
276/* The read routines must check the error status of the last configuration
277 * cycle. If there was an error, the routine returns all hex f's.
278 */
279static int
280iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
281 int size, u32 *value)
282{
283 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
284 u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
285
286 if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
287 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
288 IOP13XX_XBG_BECSR);
289 val = 0xffffffff;
290 }
291
292 *value = val;
293
294 return PCIBIOS_SUCCESSFUL;
295}
296
297static int
298iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
299 int size, u32 value)
300{
301 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
302 u32 val;
303
304 if (size != 4) {
305 val = iop13xx_atux_read(addr);
306 if (!iop13xx_atux_pci_status(1) == 0)
307 return PCIBIOS_SUCCESSFUL;
308
309 where = (where & 3) * 8;
310
311 if (size == 1)
312 val &= ~(0xff << where);
313 else
314 val &= ~(0xffff << where);
315
316 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
317 } else {
318 __raw_writel(addr, IOP13XX_ATUX_OCCAR);
319 __raw_writel(value, IOP13XX_ATUX_OCCDR);
320 }
321
322 return PCIBIOS_SUCCESSFUL;
323}
324
325static struct pci_ops iop13xx_atux_ops = {
326 .read = iop13xx_atux_read_config,
327 .write = iop13xx_atux_write_config,
328};
329
330/* This routine checks the status of the last configuration cycle. If an error
331 * was detected it returns >0, else it returns a 0. The errors being checked
332 * are parity, master abort, target abort (master and target). These types of
333 * errors occure during a config cycle where there is no device, like during
334 * the discovery stage.
335 */
336static int iop13xx_atue_pci_status(int clear)
337{
338 unsigned int status;
339 int err = 0;
340
341 /*
342 * Check the status registers.
343 */
344
345 /* standard pci status register */
346 status = __raw_readw(IOP13XX_ATUE_ATUSR);
347 if (status & IOP_PCI_STATUS_ERROR) {
348 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
349 if(clear)
350 __raw_writew(status & IOP_PCI_STATUS_ERROR,
351 IOP13XX_ATUE_ATUSR);
352 err++;
353 }
354
355 /* check the normal status bits in the ATUISR */
356 status = __raw_readl(IOP13XX_ATUE_ATUISR);
357 if (status & IOP13XX_ATUE_ATUISR_ERROR) {
358 PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
359 if (clear)
360 __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
361 IOP13XX_ATUE_ATUISR);
362 err++;
363
364 /* check the PCI-E status if the ATUISR reports an interface error */
365 if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
366 /* get the unmasked errors */
367 status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
368 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
369
370 if (status) {
371 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
372 __raw_readl(IOP13XX_ATUE_PIE_STS));
373 err++;
374 } else {
375 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
376 __raw_readl(IOP13XX_ATUE_PIE_STS));
377 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
378 __raw_readl(IOP13XX_ATUE_PIE_MSK));
379 BUG();
380 }
381
382 if(clear)
383 __raw_writel(status, IOP13XX_ATUE_PIE_STS);
384 }
385 }
386
387 return err;
388}
389
390static inline int __init
391iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
392{
393 WARN_ON(idsel != 0);
394
395 switch (pin) {
396 case 1: return ATUE_INTA;
397 case 2: return ATUE_INTB;
398 case 3: return ATUE_INTC;
399 case 4: return ATUE_INTD;
400 default: return -1;
401 }
402}
403
404static inline u32 iop13xx_atue_read(unsigned long addr)
405{
406 u32 val;
407
408 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
409 val = __raw_readl(IOP13XX_ATUE_OCCDR);
410
411 rmb();
412
413 return val;
414}
415
416/* The read routines must check the error status of the last configuration
417 * cycle. If there was an error, the routine returns all hex f's.
418 */
419static int
420iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
421 int size, u32 *value)
422{
423 u32 val;
424 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
425
426 /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
427 if (!PCI_SLOT(devfn) || (addr & 1)) {
428 val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
429 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
430 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
431 IOP13XX_XBG_BECSR);
432 val = 0xffffffff;
433 }
434
435 PRINTK("addr=%#0lx, val=%#010x", addr, val);
436 } else
437 val = 0xffffffff;
438
439 *value = val;
440
441 return PCIBIOS_SUCCESSFUL;
442}
443
444static int
445iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
446 int size, u32 value)
447{
448 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
449 u32 val;
450
451 if (size != 4) {
452 val = iop13xx_atue_read(addr);
453 if (!iop13xx_atue_pci_status(1) == 0)
454 return PCIBIOS_SUCCESSFUL;
455
456 where = (where & 3) * 8;
457
458 if (size == 1)
459 val &= ~(0xff << where);
460 else
461 val &= ~(0xffff << where);
462
463 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
464 } else {
465 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
466 __raw_writel(value, IOP13XX_ATUE_OCCDR);
467 }
468
469 return PCIBIOS_SUCCESSFUL;
470}
471
472static struct pci_ops iop13xx_atue_ops = {
473 .read = iop13xx_atue_read_config,
474 .write = iop13xx_atue_write_config,
475};
476
477/* When a PCI device does not exist during config cycles, the XScale gets a
478 * bus error instead of returning 0xffffffff. We can't rely on the ATU status
479 * bits to tell us that it was indeed a configuration cycle that caused this
480 * error especially in the case when the ATUE link is down. Instead we rely
481 * on data from the south XSI bridge to validate the abort
482 */
483int
484iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
485{
486 PRINTK("Data abort: address = 0x%08lx "
487 "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
488 addr, fsr, regs->ARM_pc, regs->ARM_lr);
489
490 PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
491 PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
492 PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
493
494 /* If it was an imprecise abort, then we need to correct the
495 * return address to be _after_ the instruction.
496 */
497 if (fsr & (1 << 10))
498 regs->ARM_pc += 4;
499
500 if (is_atue_occdr_error() || is_atux_occdr_error())
501 return 0;
502 else
503 return 1;
504}
505
506/* Scan an IOP13XX PCI bus. nr selects which ATU we use.
507 */
508struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
509{
510 int which_atu;
511 struct pci_bus *bus = NULL;
512
513 switch (init_atu) {
514 case IOP13XX_INIT_ATU_ATUX:
515 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
516 break;
517 case IOP13XX_INIT_ATU_ATUE:
518 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
519 break;
520 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
521 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
522 break;
523 default:
524 which_atu = 0;
525 }
526
527 if (!which_atu) {
528 BUG();
529 return NULL;
530 }
531
532 switch (which_atu) {
533 case IOP13XX_INIT_ATU_ATUX:
534 if (time_after_eq(jiffies + msecs_to_jiffies(1000),
535 atux_trhfa_timeout)) /* ensure not wrap */
536 while(time_before(jiffies, atux_trhfa_timeout))
537 udelay(100);
538
539 bus = pci_bus_atux = pci_scan_bus(sys->busnr,
540 &iop13xx_atux_ops,
541 sys);
542 break;
543 case IOP13XX_INIT_ATU_ATUE:
544 bus = pci_bus_atue = pci_scan_bus(sys->busnr,
545 &iop13xx_atue_ops,
546 sys);
547 break;
548 }
549
550 return bus;
551}
552
553/* This function is called from iop13xx_pci_init() after assigning valid
554 * values to iop13xx_atue_pmmr_offset. This is the location for common
555 * setup of ATUE for all IOP13XX implementations.
556 */
557void __init iop13xx_atue_setup(void)
558{
559 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
560 u32 reg_val;
561
562 /* BAR 1 (1:1 mapping with Physical RAM) */
563 /* Set limit and enable */
564 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
565 IOP13XX_ATUE_IALR1);
566 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
567
568 /* Set base at the top of the reserved address space */
569 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
570 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
571
572 /* 1:1 mapping with physical ram
573 * (leave big endian byte swap disabled)
574 */
575 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
576 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
577
578 /* Outbound window 1 (PCIX/PCIE memory window) */
579 /* 32 bit Address Space */
580 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
581 /* PA[35:32] */
582 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
583 (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
584 IOP13XX_ATUE_OUMBAR1);
585
586 /* Setup the I/O Bar
587 * A[35-16] in 31-12
588 */
589 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
590 IOP13XX_ATUE_OIOBAR);
591 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
592
593 /* clear startup errors */
594 iop13xx_atue_pci_status(1);
595
596 /* OIOBAR function number
597 */
598 reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
599 reg_val &= ~0x7;
600 reg_val |= func;
601 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
602
603 /* OUMBAR function numbers
604 */
605 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
606 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
607 IOP13XX_ATU_OUMBAR_FUNC_NUM);
608 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
609 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
610
611 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
612 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
613 IOP13XX_ATU_OUMBAR_FUNC_NUM);
614 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
615 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
616
617 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
618 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
619 IOP13XX_ATU_OUMBAR_FUNC_NUM);
620 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
621 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
622
623 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
624 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
625 IOP13XX_ATU_OUMBAR_FUNC_NUM);
626 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
627 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
628
629 /* Enable inbound and outbound cycles
630 */
631 reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
632 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
633 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
634 __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
635
636 reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
637 reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
638 IOP13XX_ATUE_ATUCR_IVM;
639 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
640}
641
642void __init iop13xx_atue_disable(void)
643{
644 u32 reg_val;
645
646 __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
647 __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
648
649 /* wait for cycles to quiesce */
650 while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
651 IOP13XX_ATUE_PCSR_IN_Q_BUSY |
652 IOP13XX_ATUE_PCSR_LLRB_BUSY))
653 cpu_relax();
654
655 /* BAR 0 ( Disabled ) */
656 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
657 __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
658 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
659 __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
660 __raw_writel(0x0, IOP13XX_ATUE_IALR0);
661 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
662 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
663 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
664
665 /* BAR 1 ( Disabled ) */
666 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
667 __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
668 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
669 __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
670 __raw_writel(0x0, IOP13XX_ATUE_IALR1);
671 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
672 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
673 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
674
675 /* BAR 2 ( Disabled ) */
676 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
677 __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
678 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
679 __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
680 __raw_writel(0x0, IOP13XX_ATUE_IALR2);
681 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
682 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
683 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
684
685 /* BAR 3 ( Disabled ) */
686 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
687 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
688 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
689
690 /* Setup the I/O Bar
691 * A[35-16] in 31-12
692 */
693 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
694 IOP13XX_ATUE_OIOBAR);
695 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
696}
697
698/* This function is called from iop13xx_pci_init() after assigning valid
699 * values to iop13xx_atux_pmmr_offset. This is the location for common
700 * setup of ATUX for all IOP13XX implementations.
701 */
702void __init iop13xx_atux_setup(void)
703{
704 u32 reg_val;
705 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
706
707 /* Take PCI-X bus out of reset if bootloader hasn't already.
708 * According to spec, we should wait for 2^25 PCI clocks to meet
709 * the PCI timing parameter Trhfa (RST# high to first access).
710 * This is rarely necessary and often ignored.
711 */
712 reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
713 if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
714 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
715 msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
716 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
717 IOP13XX_ATUX_PCSR);
718 atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
719 }
720 else
721 atux_trhfa_timeout = jiffies;
722
723 /* BAR 1 (1:1 mapping with Physical RAM) */
724 /* Set limit and enable */
725 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
726 IOP13XX_ATUX_IALR1);
727 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
728
729 /* Set base at the top of the reserved address space */
730 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
731 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
732
733 /* 1:1 mapping with physical ram
734 * (leave big endian byte swap disabled)
735 */
736 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
737 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
738
739 /* Outbound window 1 (PCIX/PCIE memory window) */
740 /* 32 bit Address Space */
741 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
742 /* PA[35:32] */
743 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
744 IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
745 IOP13XX_ATUX_OUMBAR1);
746
747 /* Setup the I/O Bar
748 * A[35-16] in 31-12
749 */
750 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
751 IOP13XX_ATUX_OIOBAR);
752 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
753
754 /* clear startup errors */
755 iop13xx_atux_pci_status(1);
756
757 /* OIOBAR function number
758 */
759 reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
760 reg_val &= ~0x7;
761 reg_val |= func;
762 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
763
764 /* OUMBAR function numbers
765 */
766 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
767 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
768 IOP13XX_ATU_OUMBAR_FUNC_NUM);
769 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
770 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
771
772 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
773 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
774 IOP13XX_ATU_OUMBAR_FUNC_NUM);
775 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
776 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
777
778 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
779 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
780 IOP13XX_ATU_OUMBAR_FUNC_NUM);
781 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
782 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
783
784 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
785 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
786 IOP13XX_ATU_OUMBAR_FUNC_NUM);
787 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
788 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
789
790 /* Enable inbound and outbound cycles
791 */
792 reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
793 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
794 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
795 __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
796
797 reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
798 reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
799 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
800}
801
802void __init iop13xx_atux_disable(void)
803{
804 u32 reg_val;
805
806 __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
807 __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
808
809 /* wait for cycles to quiesce */
810 while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
811 IOP13XX_ATUX_PCSR_IN_Q_BUSY))
812 cpu_relax();
813
814 /* BAR 0 ( Disabled ) */
815 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
816 __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
817 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
818 __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
819 __raw_writel(0x0, IOP13XX_ATUX_IALR0);
820 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
821 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
822 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
823
824 /* BAR 1 ( Disabled ) */
825 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
826 __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
827 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
828 __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
829 __raw_writel(0x0, IOP13XX_ATUX_IALR1);
830 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
831 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
832 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
833
834 /* BAR 2 ( Disabled ) */
835 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
836 __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
837 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
838 __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
839 __raw_writel(0x0, IOP13XX_ATUX_IALR2);
840 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
841 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
842 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
843
844 /* BAR 3 ( Disabled ) */
845 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
846 __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
847 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
848 __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
849 __raw_writel(0x0, IOP13XX_ATUX_IALR3);
850 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
851 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
852 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
853
854 /* Setup the I/O Bar
855 * A[35-16] in 31-12
856 */
857 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
858 IOP13XX_ATUX_OIOBAR);
859 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
860}
861
862void __init iop13xx_set_atu_mmr_bases(void)
863{
864 /* Based on ESSR0, determine the ATU X/E offsets */
865 switch(__raw_readl(IOP13XX_ESSR0) &
866 (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
867 /* both asserted */
868 case 0:
869 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
870 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
871 break;
872 /* IOP13XX_CONTROLLER_ONLY = deasserted
873 * IOP13XX_INTERFACE_SEL_PCIX = asserted
874 */
875 case IOP13XX_CONTROLLER_ONLY:
876 iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
877 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
878 break;
879 /* IOP13XX_CONTROLLER_ONLY = asserted
880 * IOP13XX_INTERFACE_SEL_PCIX = deasserted
881 */
882 case IOP13XX_INTERFACE_SEL_PCIX:
883 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
884 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
885 break;
886 /* both deasserted */
887 case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
888 iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
889 iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
890 break;
891 default:
892 BUG();
893 }
894}
895
896void __init iop13xx_atu_select(struct hw_pci *plat_pci)
897{
898 int i;
899
900 /* set system defaults
901 * note: if "iop13xx_init_atu=" is specified this autodetect
902 * sequence will be bypassed
903 */
904 if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
905 /* check for single/dual interface */
906 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
907 /* ATUE must be present check the device id
908 * to see if ATUX is present.
909 */
910 init_atu |= IOP13XX_INIT_ATU_ATUE;
911 switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
912 case 0x70:
913 case 0x80:
914 case 0xc0:
915 init_atu |= IOP13XX_INIT_ATU_ATUX;
916 break;
917 }
918 } else {
919 /* ATUX must be present check the device id
920 * to see if ATUE is present.
921 */
922 init_atu |= IOP13XX_INIT_ATU_ATUX;
923 switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
924 case 0x70:
925 case 0x80:
926 case 0xc0:
927 init_atu |= IOP13XX_INIT_ATU_ATUE;
928 break;
929 }
930 }
931
932 /* check central resource and root complex capability */
933 if (init_atu & IOP13XX_INIT_ATU_ATUX)
934 if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
935 IOP13XX_ATUX_PCSR_CENTRAL_RES))
936 init_atu &= ~IOP13XX_INIT_ATU_ATUX;
937
938 if (init_atu & IOP13XX_INIT_ATU_ATUE)
939 if (__raw_readl(IOP13XX_ATUE_PCSR) &
940 IOP13XX_ATUE_PCSR_END_POINT)
941 init_atu &= ~IOP13XX_INIT_ATU_ATUE;
942 }
943
944 for (i = 0; i < 2; i++) {
945 if((init_atu & (1 << i)) == (1 << i))
946 plat_pci->nr_controllers++;
947 }
948}
949
950void __init iop13xx_pci_init(void)
951{
952 /* clear pre-existing south bridge errors */
953 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
954
955 /* Setup the Min Address for PCI memory... */
956 iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
957
958 /* if Linux is given control of an ATU
959 * clear out its prior configuration,
960 * otherwise do not touch the registers
961 */
962 if (init_atu & IOP13XX_INIT_ATU_ATUE) {
963 iop13xx_atue_disable();
964 iop13xx_atue_setup();
965 }
966
967 if (init_atu & IOP13XX_INIT_ATU_ATUX) {
968 iop13xx_atux_disable();
969 iop13xx_atux_setup();
970 }
971
972 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS,
973 "imprecise external abort");
974}
975
976/* intialize the pci memory space. handle any combination of
977 * atue and atux enabled/disabled
978 */
979int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
980{
981 struct resource *res;
982 int which_atu;
983 u32 pcixsr, pcsr;
984
985 if (nr > 1)
986 return 0;
987
988 res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
989 if (!res)
990 panic("PCI: unable to alloc resources");
991
992 memset(res, 0, sizeof(struct resource) * 2);
993
994 /* 'nr' assumptions:
995 * ATUX is always 0
996 * ATUE is 1 when ATUX is also enabled
997 * ATUE is 0 when ATUX is disabled
998 */
999 switch(init_atu) {
1000 case IOP13XX_INIT_ATU_ATUX:
1001 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
1002 break;
1003 case IOP13XX_INIT_ATU_ATUE:
1004 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
1005 break;
1006 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
1007 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
1008 break;
1009 default:
1010 which_atu = 0;
1011 }
1012
1013 if (!which_atu)
1014 return 0;
1015
1016 switch(which_atu) {
1017 case IOP13XX_INIT_ATU_ATUX:
1018 pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
1019 pcixsr &= ~0xffff;
1020 pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
1021 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
1022 iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
1023 << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1024 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1025
1026 res[0].start = IOP13XX_PCIX_LOWER_IO_PA;
1027 res[0].end = IOP13XX_PCIX_UPPER_IO_PA;
1028 res[0].name = "IQ81340 ATUX PCI I/O Space";
1029 res[0].flags = IORESOURCE_IO;
1030
1031 res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
1032 res[1].end = IOP13XX_PCIX_UPPER_MEM_RA;
1033 res[1].name = "IQ81340 ATUX PCI Memory Space";
1034 res[1].flags = IORESOURCE_MEM;
1035 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1036 sys->io_offset = IOP13XX_PCIX_IO_OFFSET;
1037 break;
1038 case IOP13XX_INIT_ATU_ATUE:
1039 /* Note: the function number field in the PCSR is ro */
1040 pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
1041 pcsr &= ~(0xfff8 << 16);
1042 pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
1043 0 << IOP13XX_ATUE_PCSR_DEV_NUM;
1044
1045 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1046
1047 res[0].start = IOP13XX_PCIE_LOWER_IO_PA;
1048 res[0].end = IOP13XX_PCIE_UPPER_IO_PA;
1049 res[0].name = "IQ81340 ATUE PCI I/O Space";
1050 res[0].flags = IORESOURCE_IO;
1051
1052 res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
1053 res[1].end = IOP13XX_PCIE_UPPER_MEM_RA;
1054 res[1].name = "IQ81340 ATUE PCI Memory Space";
1055 res[1].flags = IORESOURCE_MEM;
1056 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1057 sys->io_offset = IOP13XX_PCIE_IO_OFFSET;
1058 sys->map_irq = iop13xx_pcie_map_irq;
1059 break;
1060 default:
1061 return 0;
1062 }
1063
1064 request_resource(&ioport_resource, &res[0]);
1065 request_resource(&iomem_resource, &res[1]);
1066
1067 sys->resource[0] = &res[0];
1068 sys->resource[1] = &res[1];
1069 sys->resource[2] = NULL;
1070
1071 return 1;
1072}
1073
1074u16 iop13xx_dev_id(void)
1075{
1076 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
1077 return __raw_readw(IOP13XX_ATUE_DID);
1078 else
1079 return __raw_readw(IOP13XX_ATUX_DID);
1080}
1081
1082static int __init iop13xx_init_atu_setup(char *str)
1083{
1084 init_atu = IOP13XX_INIT_ATU_NONE;
1085 if (str) {
1086 while (*str != '\0') {
1087 switch (*str) {
1088 case 'x':
1089 case 'X':
1090 init_atu |= IOP13XX_INIT_ATU_ATUX;
1091 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1092 break;
1093 case 'e':
1094 case 'E':
1095 init_atu |= IOP13XX_INIT_ATU_ATUE;
1096 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1097 break;
1098 case ',':
1099 case '=':
1100 break;
1101 default:
1102 PRINTK("\"iop13xx_init_atu\" malformed at "
1103 "character: \'%c\'", *str);
1104 *(str + 1) = '\0';
1105 init_atu = IOP13XX_INIT_ATU_DEFAULT;
1106 }
1107 str++;
1108 }
1109 }
1110 return 1;
1111}
1112
1113__setup("iop13xx_init_atu", iop13xx_init_atu_setup);
kernel source for telekom puls (alcatel/mediatek)