[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-imx / mach-pca100.c

/*
 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
 * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/dma-mapping.h>
#include <linux/spi/spi.h>
#include <linux/spi/eeprom.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>

#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <asm/mach/time.h>
#include <mach/audmux.h>
#include <mach/mxc_nand.h>
#include <mach/irqs.h>
#include <mach/ulpi.h>

#include "devices-imx27.h"

#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
#define SPI1_SS0 (GPIO_PORTD + 28)
#define SPI1_SS1 (GPIO_PORTD + 27)
#define SD2_CD (GPIO_PORTC + 29)

static const int pca100_pins[] __initconst = {
	/* UART1 */
	PE12_PF_UART1_TXD,
	PE13_PF_UART1_RXD,
	PE14_PF_UART1_CTS,
	PE15_PF_UART1_RTS,
	/* SDHC */
	PB4_PF_SD2_D0,
	PB5_PF_SD2_D1,
	PB6_PF_SD2_D2,
	PB7_PF_SD2_D3,
	PB8_PF_SD2_CMD,
	PB9_PF_SD2_CLK,
	SD2_CD | GPIO_GPIO | GPIO_IN,
	/* FEC */
	PD0_AIN_FEC_TXD0,
	PD1_AIN_FEC_TXD1,
	PD2_AIN_FEC_TXD2,
	PD3_AIN_FEC_TXD3,
	PD4_AOUT_FEC_RX_ER,
	PD5_AOUT_FEC_RXD1,
	PD6_AOUT_FEC_RXD2,
	PD7_AOUT_FEC_RXD3,
	PD8_AF_FEC_MDIO,
	PD9_AIN_FEC_MDC,
	PD10_AOUT_FEC_CRS,
	PD11_AOUT_FEC_TX_CLK,
	PD12_AOUT_FEC_RXD0,
	PD13_AOUT_FEC_RX_DV,
	PD14_AOUT_FEC_RX_CLK,
	PD15_AOUT_FEC_COL,
	PD16_AIN_FEC_TX_ER,
	PF23_AIN_FEC_TX_EN,
	/* SSI1 */
	PC20_PF_SSI1_FS,
	PC21_PF_SSI1_RXD,
	PC22_PF_SSI1_TXD,
	PC23_PF_SSI1_CLK,
	/* onboard I2C */
	PC5_PF_I2C2_SDA,
	PC6_PF_I2C2_SCL,
	/* external I2C */
	PD17_PF_I2C_DATA,
	PD18_PF_I2C_CLK,
	/* SPI1 */
	PD25_PF_CSPI1_RDY,
	PD29_PF_CSPI1_SCLK,
	PD30_PF_CSPI1_MISO,
	PD31_PF_CSPI1_MOSI,
	/* OTG */
	OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
	PC7_PF_USBOTG_DATA5,
	PC8_PF_USBOTG_DATA6,
	PC9_PF_USBOTG_DATA0,
	PC10_PF_USBOTG_DATA2,
	PC11_PF_USBOTG_DATA1,
	PC12_PF_USBOTG_DATA4,
	PC13_PF_USBOTG_DATA3,
	PE0_PF_USBOTG_NXT,
	PE1_PF_USBOTG_STP,
	PE2_PF_USBOTG_DIR,
	PE24_PF_USBOTG_CLK,
	PE25_PF_USBOTG_DATA7,
	/* USBH2 */
	USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
	PA0_PF_USBH2_CLK,
	PA1_PF_USBH2_DIR,
	PA2_PF_USBH2_DATA7,
	PA3_PF_USBH2_NXT,
	PA4_PF_USBH2_STP,
	PD19_AF_USBH2_DATA4,
	PD20_AF_USBH2_DATA3,
	PD21_AF_USBH2_DATA6,
	PD22_AF_USBH2_DATA0,
	PD23_AF_USBH2_DATA2,
	PD24_AF_USBH2_DATA1,
	PD26_AF_USBH2_DATA5,
	/* display */
	PA5_PF_LSCLK,
	PA6_PF_LD0,
	PA7_PF_LD1,
	PA8_PF_LD2,
	PA9_PF_LD3,
	PA10_PF_LD4,
	PA11_PF_LD5,
	PA12_PF_LD6,
	PA13_PF_LD7,
	PA14_PF_LD8,
	PA15_PF_LD9,
	PA16_PF_LD10,
	PA17_PF_LD11,
	PA18_PF_LD12,
	PA19_PF_LD13,
	PA20_PF_LD14,
	PA21_PF_LD15,
	PA22_PF_LD16,
	PA23_PF_LD17,
	PA26_PF_PS,
	PA28_PF_HSYNC,
	PA29_PF_VSYNC,
	PA31_PF_OE_ACD,
	/* free GPIO */
	GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */
	GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */
	GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */
};

static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static const struct mxc_nand_platform_data
pca100_nand_board_info __initconst = {
	.width = 1,
	.hw_ecc = 1,
};

static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
	.bitrate = 100000,
};

static struct at24_platform_data board_eeprom = {
	.byte_len = 4096,
	.page_size = 32,
	.flags = AT24_FLAG_ADDR16,
};

static struct i2c_board_info pca100_i2c_devices[] = {
	{
		I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
		.platform_data = &board_eeprom,
	}, {
		I2C_BOARD_INFO("pcf8563", 0x51),
	}, {
		I2C_BOARD_INFO("lm75", 0x4a),
	}
};

#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
static struct spi_eeprom at25320 = {
	.name		= "at25320an",
	.byte_len	= 4096,
	.page_size	= 32,
	.flags		= EE_ADDR2,
};

static struct spi_board_info pca100_spi_board_info[] __initdata = {
	{
		.modalias = "at25",
		.max_speed_hz = 30000,
		.bus_num = 0,
		.chip_select = 1,
		.platform_data = &at25320,
	},
};

static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};

static const struct spi_imx_master pca100_spi0_data __initconst = {
	.chipselect	= pca100_spi_cs,
	.num_chipselect = ARRAY_SIZE(pca100_spi_cs),
};
#endif

static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
{
	mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);
	gpio_set_value(GPIO_PORTC + 20, 1);
	udelay(2);
	gpio_set_value(GPIO_PORTC + 20, 0);
	mxc_gpio_mode(PC20_PF_SSI1_FS);
	msleep(2);
}

static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
{
	mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);  /* FS */
	gpio_set_value(GPIO_PORTC + 20, 0);
	mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT);  /* TX */
	gpio_set_value(GPIO_PORTC + 22, 0);
	mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT);  /* reset */
	gpio_set_value(GPIO_PORTC + 28, 0);
	udelay(10);
	gpio_set_value(GPIO_PORTC + 28, 1);
	mxc_gpio_mode(PC20_PF_SSI1_FS);
	mxc_gpio_mode(PC22_PF_SSI1_TXD);
	msleep(2);
}

static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = {
	.ac97_reset		= pca100_ac97_cold_reset,
	.ac97_warm_reset	= pca100_ac97_warm_reset,
	.flags			= IMX_SSI_USE_AC97,
};

static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
		void *data)
{
	int ret;

	ret = request_irq(IRQ_GPIOC(29), detect_irq,
			  IRQF_DISABLED | IRQF_TRIGGER_FALLING,
			  "imx-mmc-detect", data);
	if (ret)
		printk(KERN_ERR
			"pca100: Failed to reuest irq for sd/mmc detection\n");

	return ret;
}

static void pca100_sdhc2_exit(struct device *dev, void *data)
{
	free_irq(IRQ_GPIOC(29), data);
}

static const struct imxmmc_platform_data sdhc_pdata __initconst = {
	.init = pca100_sdhc2_init,
	.exit = pca100_sdhc2_exit,
};

#if defined(CONFIG_USB_ULPI)
static int otg_phy_init(struct platform_device *pdev)
{
	gpio_set_value(OTG_PHY_CS_GPIO, 0);
	return 0;
}

static struct mxc_usbh_platform_data otg_pdata __initdata = {
	.init	= otg_phy_init,
	.portsc	= MXC_EHCI_MODE_ULPI,
	.flags	= MXC_EHCI_INTERFACE_DIFF_UNI,
};

static int usbh2_phy_init(struct platform_device *pdev)
{
	gpio_set_value(USBH2_PHY_CS_GPIO, 0);
	return 0;
}

static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
	.init	= usbh2_phy_init,
	.portsc	= MXC_EHCI_MODE_ULPI,
	.flags	= MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif

static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
	.operating_mode = FSL_USB2_DR_DEVICE,
	.phy_mode       = FSL_USB2_PHY_ULPI,
};

static int otg_mode_host;

static int __init pca100_otg_mode(char *options)
{
	if (!strcmp(options, "host"))
		otg_mode_host = 1;
	else if (!strcmp(options, "device"))
		otg_mode_host = 0;
	else
		pr_info("otg_mode neither \"host\" nor \"device\". "
			"Defaulting to device\n");
	return 0;
}
__setup("otg_mode=", pca100_otg_mode);

/* framebuffer info */
static struct imx_fb_videomode pca100_fb_modes[] = {
	{
		.mode = {
			.name		= "EMERGING-ETV570G0DHU",
			.refresh	= 60,
			.xres		= 640,
			.yres		= 480,
			.pixclock	= 39722, /* in ps (25.175 MHz) */
			.hsync_len	= 30,
			.left_margin	= 114,
			.right_margin	= 16,
			.vsync_len	= 3,
			.upper_margin	= 32,
			.lower_margin	= 0,
		},
		/*
		 * TFT
		 * Pixel pol active high
		 * HSYNC active low
		 * VSYNC active low
		 * use HSYNC for ACD count
		 * line clock disable while idle
		 * always enable line clock even if no data
		 */
		.pcr = 0xf0c08080,
		.bpp = 16,
	},
};

static const struct imx_fb_platform_data pca100_fb_data __initconst = {
	.mode = pca100_fb_modes,
	.num_modes = ARRAY_SIZE(pca100_fb_modes),

	.pwmr		= 0x00A903FF,
	.lscr1		= 0x00120300,
	.dmacr		= 0x00020010,
};

static void __init pca100_init(void)
{
	int ret;

	/* SSI unit */
	mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
				  MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
				  MXC_AUDMUX_V1_PCR_TFCSEL(3) |
				  MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
				  MXC_AUDMUX_V1_PCR_RXDSEL(3));
	mxc_audmux_v1_configure_port(3,
				  MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
				  MXC_AUDMUX_V1_PCR_TFCSEL(0) |
				  MXC_AUDMUX_V1_PCR_TFSDIR |
				  MXC_AUDMUX_V1_PCR_RXDSEL(0));

	ret = mxc_gpio_setup_multiple_pins(pca100_pins,
			ARRAY_SIZE(pca100_pins), "PCA100");
	if (ret)
		printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);

	imx27_add_imx_ssi(0, &pca100_ssi_pdata);

	imx27_add_imx_uart0(&uart_pdata);

	imx27_add_mxc_mmc(1, &sdhc_pdata);

	imx27_add_mxc_nand(&pca100_nand_board_info);

	/* only the i2c master 1 is used on this CPU card */
	i2c_register_board_info(1, pca100_i2c_devices,
				ARRAY_SIZE(pca100_i2c_devices));

	imx27_add_imx_i2c(1, &pca100_i2c1_data);

#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
	mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
	mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
	spi_register_board_info(pca100_spi_board_info,
				ARRAY_SIZE(pca100_spi_board_info));
	imx27_add_spi_imx0(&pca100_spi0_data);
#endif

	gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
	gpio_direction_output(OTG_PHY_CS_GPIO, 1);
	gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
	gpio_direction_output(USBH2_PHY_CS_GPIO, 1);

#if defined(CONFIG_USB_ULPI)
	if (otg_mode_host) {
		otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
				ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);

		imx27_add_mxc_ehci_otg(&otg_pdata);
	}

	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
				ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);

	imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
	if (!otg_mode_host) {
		gpio_set_value(OTG_PHY_CS_GPIO, 0);
		imx27_add_fsl_usb2_udc(&otg_device_pdata);
	}

	imx27_add_imx_fb(&pca100_fb_data);

	imx27_add_fec(NULL);
	imx27_add_imx2_wdt(NULL);
	imx27_add_mxc_w1(NULL);
}

static void __init pca100_timer_init(void)
{
	mx27_clocks_init(26000000);
}

static struct sys_timer pca100_timer = {
	.init = pca100_timer_init,
};

MACHINE_START(PCA100, "phyCARD-i.MX27")
	.boot_params    = MX27_PHYS_OFFSET + 0x100,
	.map_io         = mx27_map_io,
	.init_irq       = mx27_init_irq,
	.init_machine   = pca100_init,
	.timer          = &pca100_timer,
MACHINE_END
Commit	Line	Data
33731698 LF	1	/*
	2	* Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
	3	* Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de)
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	* MA 02110-1301, USA.
	18	*/
	19
	20	#include <linux/platform_device.h>
	21	#include <linux/io.h>
	22	#include <linux/i2c.h>
	23	#include <linux/i2c/at24.h>
	24	#include <linux/dma-mapping.h>
	25	#include <linux/spi/spi.h>
	26	#include <linux/spi/eeprom.h>
	27	#include <linux/irq.h>
c8a6885f	28	#include <linux/delay.h>
33731698	29	#include <linux/gpio.h>
eee7c497 SH	30	#include <linux/usb/otg.h>
eee7c497 SH	31	#include <linux/usb/ulpi.h>
33731698 LF	32
	33	#include <asm/mach/arch.h>
	34	#include <asm/mach-types.h>
	35	#include <mach/common.h>
	36	#include <mach/hardware.h>
e835d88e	37	#include <mach/iomux-mx27.h>
33731698	38	#include <asm/mach/time.h>
c8a6885f	39	#include <mach/audmux.h>
33731698 LF	40	#include <mach/mxc_nand.h>
33731698 LF	41	#include <mach/irqs.h>
eee7c497	42	#include <mach/ulpi.h>
33731698	43
0e7a29a8	44	#include "devices-imx27.h"
33731698	45
eee7c497 SH	46	#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
eee7c497 SH	47	#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
b725abad LF	48	#define SPI1_SS0 (GPIO_PORTD + 28)
	49	#define SPI1_SS1 (GPIO_PORTD + 27)
	50	#define SD2_CD (GPIO_PORTC + 29)
eee7c497	51
6c80ee51	52	static const int pca100_pins[] __initconst = {
33731698 LF	53	/* UART1 */
	54	PE12_PF_UART1_TXD,
	55	PE13_PF_UART1_RXD,
	56	PE14_PF_UART1_CTS,
	57	PE15_PF_UART1_RTS,
	58	/* SDHC */
	59	PB4_PF_SD2_D0,
	60	PB5_PF_SD2_D1,
	61	PB6_PF_SD2_D2,
	62	PB7_PF_SD2_D3,
	63	PB8_PF_SD2_CMD,
	64	PB9_PF_SD2_CLK,
b725abad	65	SD2_CD \| GPIO_GPIO \| GPIO_IN,
33731698 LF	66	/* FEC */
	67	PD0_AIN_FEC_TXD0,
	68	PD1_AIN_FEC_TXD1,
	69	PD2_AIN_FEC_TXD2,
	70	PD3_AIN_FEC_TXD3,
	71	PD4_AOUT_FEC_RX_ER,
	72	PD5_AOUT_FEC_RXD1,
	73	PD6_AOUT_FEC_RXD2,
	74	PD7_AOUT_FEC_RXD3,
	75	PD8_AF_FEC_MDIO,
	76	PD9_AIN_FEC_MDC,
	77	PD10_AOUT_FEC_CRS,
	78	PD11_AOUT_FEC_TX_CLK,
	79	PD12_AOUT_FEC_RXD0,
	80	PD13_AOUT_FEC_RX_DV,
	81	PD14_AOUT_FEC_RX_CLK,
	82	PD15_AOUT_FEC_COL,
	83	PD16_AIN_FEC_TX_ER,
	84	PF23_AIN_FEC_TX_EN,
	85	/* SSI1 */
	86	PC20_PF_SSI1_FS,
	87	PC21_PF_SSI1_RXD,
	88	PC22_PF_SSI1_TXD,
	89	PC23_PF_SSI1_CLK,
	90	/* onboard I2C */
	91	PC5_PF_I2C2_SDA,
	92	PC6_PF_I2C2_SCL,
	93	/* external I2C */
	94	PD17_PF_I2C_DATA,
	95	PD18_PF_I2C_CLK,
	96	/* SPI1 */
	97	PD25_PF_CSPI1_RDY,
	98	PD29_PF_CSPI1_SCLK,
	99	PD30_PF_CSPI1_MISO,
	100	PD31_PF_CSPI1_MOSI,
eee7c497 SH	101	/* OTG */
	102	OTG_PHY_CS_GPIO \| GPIO_GPIO \| GPIO_OUT,
	103	PC7_PF_USBOTG_DATA5,
	104	PC8_PF_USBOTG_DATA6,
	105	PC9_PF_USBOTG_DATA0,
	106	PC10_PF_USBOTG_DATA2,
	107	PC11_PF_USBOTG_DATA1,
	108	PC12_PF_USBOTG_DATA4,
	109	PC13_PF_USBOTG_DATA3,
	110	PE0_PF_USBOTG_NXT,
	111	PE1_PF_USBOTG_STP,
	112	PE2_PF_USBOTG_DIR,
	113	PE24_PF_USBOTG_CLK,
	114	PE25_PF_USBOTG_DATA7,
	115	/* USBH2 */
	116	USBH2_PHY_CS_GPIO \| GPIO_GPIO \| GPIO_OUT,
	117	PA0_PF_USBH2_CLK,
	118	PA1_PF_USBH2_DIR,
	119	PA2_PF_USBH2_DATA7,
	120	PA3_PF_USBH2_NXT,
	121	PA4_PF_USBH2_STP,
	122	PD19_AF_USBH2_DATA4,
	123	PD20_AF_USBH2_DATA3,
	124	PD21_AF_USBH2_DATA6,
	125	PD22_AF_USBH2_DATA0,
	126	PD23_AF_USBH2_DATA2,
	127	PD24_AF_USBH2_DATA1,
	128	PD26_AF_USBH2_DATA5,
42216fc5 LF	129	/* display */
	130	PA5_PF_LSCLK,
	131	PA6_PF_LD0,
	132	PA7_PF_LD1,
	133	PA8_PF_LD2,
	134	PA9_PF_LD3,
	135	PA10_PF_LD4,
	136	PA11_PF_LD5,
	137	PA12_PF_LD6,
	138	PA13_PF_LD7,
	139	PA14_PF_LD8,
	140	PA15_PF_LD9,
	141	PA16_PF_LD10,
	142	PA17_PF_LD11,
	143	PA18_PF_LD12,
	144	PA19_PF_LD13,
	145	PA20_PF_LD14,
	146	PA21_PF_LD15,
	147	PA22_PF_LD16,
	148	PA23_PF_LD17,
	149	PA26_PF_PS,
	150	PA28_PF_HSYNC,
	151	PA29_PF_VSYNC,
	152	PA31_PF_OE_ACD,
b725abad LF	153	/* free GPIO */
	154	GPIO_PORTC \| 31 \| GPIO_GPIO \| GPIO_IN, /* GPIO0_IRQ */
	155	GPIO_PORTC \| 25 \| GPIO_GPIO \| GPIO_IN, /* GPIO1_IRQ */
	156	GPIO_PORTE \| 5 \| GPIO_GPIO \| GPIO_IN, /* GPIO2_IRQ */
33731698 LF	157	};
33731698 LF	158
d5dac4a6	159	static const struct imxuart_platform_data uart_pdata __initconst = {
33731698 LF	160	.flags = IMXUART_HAVE_RTSCTS,
	161	};
	162
0e7a29a8 UKK	163	static const struct mxc_nand_platform_data
0e7a29a8 UKK	164	pca100_nand_board_info __initconst = {
33731698 LF	165	.width = 1,
	166	.hw_ecc = 1,
	167	};
	168
c6987159	169	static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
33731698 LF	170	.bitrate = 100000,
	171	};
	172
	173	static struct at24_platform_data board_eeprom = {
	174	.byte_len = 4096,
	175	.page_size = 32,
	176	.flags = AT24_FLAG_ADDR16,
	177	};
	178
	179	static struct i2c_board_info pca100_i2c_devices[] = {
	180	{
	181	I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
	182	.platform_data = &board_eeprom,
	183	}, {
bd9e310d	184	I2C_BOARD_INFO("pcf8563", 0x51),
33731698 LF	185	}, {
33731698 LF	186	I2C_BOARD_INFO("lm75", 0x4a),
33731698 LF	187	}
	188	};
	189
	190	#if defined(CONFIG_SPI_IMX) \|\| defined(CONFIG_SPI_IMX_MODULE)
	191	static struct spi_eeprom at25320 = {
	192	.name = "at25320an",
	193	.byte_len = 4096,
	194	.page_size = 32,
	195	.flags = EE_ADDR2,
	196	};
	197
	198	static struct spi_board_info pca100_spi_board_info[] __initdata = {
	199	{
	200	.modalias = "at25",
	201	.max_speed_hz = 30000,
	202	.bus_num = 0,
	203	.chip_select = 1,
	204	.platform_data = &at25320,
	205	},
	206	};
	207
b725abad	208	static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
33731698	209
7536cf99	210	static const struct spi_imx_master pca100_spi0_data __initconst = {
33731698 LF	211	.chipselect = pca100_spi_cs,
	212	.num_chipselect = ARRAY_SIZE(pca100_spi_cs),
	213	};
	214	#endif
	215
c8a6885f SH	216	static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
	217	{
	218	mxc_gpio_mode(GPIO_PORTC \| 20 \| GPIO_GPIO \| GPIO_OUT);
	219	gpio_set_value(GPIO_PORTC + 20, 1);
	220	udelay(2);
	221	gpio_set_value(GPIO_PORTC + 20, 0);
	222	mxc_gpio_mode(PC20_PF_SSI1_FS);
	223	msleep(2);
	224	}
	225
	226	static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
	227	{
	228	mxc_gpio_mode(GPIO_PORTC \| 20 \| GPIO_GPIO \| GPIO_OUT); /* FS */
	229	gpio_set_value(GPIO_PORTC + 20, 0);
	230	mxc_gpio_mode(GPIO_PORTC \| 22 \| GPIO_GPIO \| GPIO_OUT); /* TX */
	231	gpio_set_value(GPIO_PORTC + 22, 0);
	232	mxc_gpio_mode(GPIO_PORTC \| 28 \| GPIO_GPIO \| GPIO_OUT); /* reset */
	233	gpio_set_value(GPIO_PORTC + 28, 0);
	234	udelay(10);
	235	gpio_set_value(GPIO_PORTC + 28, 1);
	236	mxc_gpio_mode(PC20_PF_SSI1_FS);
	237	mxc_gpio_mode(PC22_PF_SSI1_TXD);
	238	msleep(2);
	239	}
	240
4697bb92	241	static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = {
c8a6885f SH	242	.ac97_reset = pca100_ac97_cold_reset,
	243	.ac97_warm_reset = pca100_ac97_warm_reset,
	244	.flags = IMX_SSI_USE_AC97,
	245	};
	246
33731698 LF	247	static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
	248	void *data)
	249	{
	250	int ret;
	251
	252	ret = request_irq(IRQ_GPIOC(29), detect_irq,
	253	IRQF_DISABLED \| IRQF_TRIGGER_FALLING,
	254	"imx-mmc-detect", data);
	255	if (ret)
	256	printk(KERN_ERR
	257	"pca100: Failed to reuest irq for sd/mmc detection\n");
	258
	259	return ret;
	260	}
	261
	262	static void pca100_sdhc2_exit(struct device dev, void data)
	263	{
	264	free_irq(IRQ_GPIOC(29), data);
	265	}
	266
9d3d945a	267	static const struct imxmmc_platform_data sdhc_pdata __initconst = {
33731698 LF	268	.init = pca100_sdhc2_init,
	269	.exit = pca100_sdhc2_exit,
	270	};
	271
c18e8fa5	272	#if defined(CONFIG_USB_ULPI)
eee7c497 SH	273	static int otg_phy_init(struct platform_device *pdev)
	274	{
	275	gpio_set_value(OTG_PHY_CS_GPIO, 0);
	276	return 0;
	277	}
	278
2eb42d5c	279	static struct mxc_usbh_platform_data otg_pdata __initdata = {
eee7c497 SH	280	.init = otg_phy_init,
	281	.portsc = MXC_EHCI_MODE_ULPI,
	282	.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
	283	};
	284
	285	static int usbh2_phy_init(struct platform_device *pdev)
	286	{
	287	gpio_set_value(USBH2_PHY_CS_GPIO, 0);
	288	return 0;
	289	}
	290
2eb42d5c	291	static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
eee7c497 SH	292	.init = usbh2_phy_init,
	293	.portsc = MXC_EHCI_MODE_ULPI,
	294	.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
	295	};
c18e8fa5	296	#endif
eee7c497	297
bd455ed3	298	static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
eee7c497 SH	299	.operating_mode = FSL_USB2_DR_DEVICE,
	300	.phy_mode = FSL_USB2_PHY_ULPI,
	301	};
	302
	303	static int otg_mode_host;
	304
	305	static int __init pca100_otg_mode(char *options)
	306	{
	307	if (!strcmp(options, "host"))
	308	otg_mode_host = 1;
	309	else if (!strcmp(options, "device"))
	310	otg_mode_host = 0;
	311	else
	312	pr_info("otg_mode neither \"host\" nor \"device\". "
	313	"Defaulting to device\n");
	314	return 0;
	315	}
	316	__setup("otg_mode=", pca100_otg_mode);
	317
42216fc5 LF	318	/* framebuffer info */
	319	static struct imx_fb_videomode pca100_fb_modes[] = {
	320	{
	321	.mode = {
	322	.name = "EMERGING-ETV570G0DHU",
	323	.refresh = 60,
	324	.xres = 640,
	325	.yres = 480,
	326	.pixclock = 39722, /* in ps (25.175 MHz) */
	327	.hsync_len = 30,
	328	.left_margin = 114,
	329	.right_margin = 16,
	330	.vsync_len = 3,
	331	.upper_margin = 32,
	332	.lower_margin = 0,
	333	},
	334	/*
	335	* TFT
	336	* Pixel pol active high
	337	* HSYNC active low
	338	* VSYNC active low
	339	* use HSYNC for ACD count
	340	* line clock disable while idle
	341	* always enable line clock even if no data
	342	*/
	343	.pcr = 0xf0c08080,
	344	.bpp = 16,
	345	},
	346	};
	347
ad851bff	348	static const struct imx_fb_platform_data pca100_fb_data __initconst = {
42216fc5 LF	349	.mode = pca100_fb_modes,
	350	.num_modes = ARRAY_SIZE(pca100_fb_modes),
	351
	352	.pwmr = 0x00A903FF,
	353	.lscr1 = 0x00120300,
	354	.dmacr = 0x00020010,
	355	};
	356
33731698 LF	357	static void __init pca100_init(void)
	358	{
	359	int ret;
	360
c8a6885f SH	361	/* SSI unit */
	362	mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
	363	MXC_AUDMUX_V1_PCR_SYN \| /* 4wire mode */
	364	MXC_AUDMUX_V1_PCR_TFCSEL(3) \|
	365	MXC_AUDMUX_V1_PCR_TCLKDIR \| /* clock is output */
	366	MXC_AUDMUX_V1_PCR_RXDSEL(3));
	367	mxc_audmux_v1_configure_port(3,
	368	MXC_AUDMUX_V1_PCR_SYN \| /* 4wire mode */
	369	MXC_AUDMUX_V1_PCR_TFCSEL(0) \|
	370	MXC_AUDMUX_V1_PCR_TFSDIR \|
	371	MXC_AUDMUX_V1_PCR_RXDSEL(0));
	372
33731698 LF	373	ret = mxc_gpio_setup_multiple_pins(pca100_pins,
	374	ARRAY_SIZE(pca100_pins), "PCA100");
	375	if (ret)
	376	printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
	377
4697bb92	378	imx27_add_imx_ssi(0, &pca100_ssi_pdata);
c8a6885f	379
d5dac4a6	380	imx27_add_imx_uart0(&uart_pdata);
33731698	381
9d3d945a	382	imx27_add_mxc_mmc(1, &sdhc_pdata);
33731698	383
0e7a29a8	384	imx27_add_mxc_nand(&pca100_nand_board_info);
33731698 LF	385
	386	/* only the i2c master 1 is used on this CPU card */
	387	i2c_register_board_info(1, pca100_i2c_devices,
	388	ARRAY_SIZE(pca100_i2c_devices));
	389
77a406da	390	imx27_add_imx_i2c(1, &pca100_i2c1_data);
33731698	391
33731698	392	#if defined(CONFIG_SPI_IMX) \|\| defined(CONFIG_SPI_IMX_MODULE)
b725abad LF	393	mxc_gpio_mode(GPIO_PORTD \| 28 \| GPIO_GPIO \| GPIO_IN);
b725abad LF	394	mxc_gpio_mode(GPIO_PORTD \| 27 \| GPIO_GPIO \| GPIO_IN);
33731698 LF	395	spi_register_board_info(pca100_spi_board_info,
33731698 LF	396	ARRAY_SIZE(pca100_spi_board_info));
4df772d7	397	imx27_add_spi_imx0(&pca100_spi0_data);
33731698 LF	398	#endif
33731698 LF	399
eee7c497 SH	400	gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
	401	gpio_direction_output(OTG_PHY_CS_GPIO, 1);
	402	gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
	403	gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
	404
	405	#if defined(CONFIG_USB_ULPI)
	406	if (otg_mode_host) {
	407	otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
70ddd47f	408	ULPI_OTG_DRVVBUS \| ULPI_OTG_DRVVBUS_EXT);
eee7c497	409
2eb42d5c	410	imx27_add_mxc_ehci_otg(&otg_pdata);
eee7c497 SH	411	}
	412
	413	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
70ddd47f	414	ULPI_OTG_DRVVBUS \| ULPI_OTG_DRVVBUS_EXT);
eee7c497	415
2eb42d5c	416	imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
eee7c497 SH	417	#endif
	418	if (!otg_mode_host) {
	419	gpio_set_value(OTG_PHY_CS_GPIO, 0);
bd455ed3	420	imx27_add_fsl_usb2_udc(&otg_device_pdata);
eee7c497 SH	421	}
eee7c497 SH	422
ad851bff	423	imx27_add_imx_fb(&pca100_fb_data);
42216fc5	424
6bd96f3c	425	imx27_add_fec(NULL);
e0a1961d	426	imx27_add_imx2_wdt(NULL);
ae71a562	427	imx27_add_mxc_w1(NULL);
33731698 LF	428	}
	429
	430	static void __init pca100_timer_init(void)
	431	{
	432	mx27_clocks_init(26000000);
	433	}
	434
	435	static struct sys_timer pca100_timer = {
	436	.init = pca100_timer_init,
	437	};
	438
	439	MACHINE_START(PCA100, "phyCARD-i.MX27")
34101237	440	.boot_params = MX27_PHYS_OFFSET + 0x100,
33731698	441	.map_io = mx27_map_io,
f6f1bc64	442	.init_irq = mx27_init_irq,
33731698 LF	443	.init_machine = pca100_init,
	444	.timer = &pca100_timer,
	445	MACHINE_END
	446