[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / arch / arm / mach-imx / mach-mx21ads.c

/*
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/physmap.h>
#include <linux/gpio.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/imx-uart.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx21.h>
#include <mach/mxc_nand.h>
#include <mach/mmc.h>

#include "devices.h"

/*
 * Memory-mapped I/O on MX21ADS base board
 */
#define MX21ADS_MMIO_BASE_ADDR   0xf5000000
#define MX21ADS_MMIO_SIZE        SZ_16M

#define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
		(MX21ADS_MMIO_BASE_ADDR + (offset))

#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
#define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
#define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)

/* MX21ADS_IO_REG bit definitions */
#define MX21ADS_IO_SD_WP        0x0001 /* read */
#define MX21ADS_IO_TP6          0x0001 /* write */
#define MX21ADS_IO_SW_SEL       0x0002 /* read */
#define MX21ADS_IO_TP7          0x0002 /* write */
#define MX21ADS_IO_RESET_E_UART 0x0004
#define MX21ADS_IO_RESET_BASE   0x0008
#define MX21ADS_IO_CSI_CTL2     0x0010
#define MX21ADS_IO_CSI_CTL1     0x0020
#define MX21ADS_IO_CSI_CTL0     0x0040
#define MX21ADS_IO_UART1_EN     0x0080
#define MX21ADS_IO_UART4_EN     0x0100
#define MX21ADS_IO_LCDON        0x0200
#define MX21ADS_IO_IRDA_EN      0x0400
#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
#define MX21ADS_IO_IRDA_MD0_B   0x1000
#define MX21ADS_IO_IRDA_MD1     0x2000
#define MX21ADS_IO_LED4_ON      0x4000
#define MX21ADS_IO_LED3_ON      0x8000

static unsigned int mx21ads_pins[] = {

	/* CS8900A */
	(GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),

	/* UART1 */
	PE12_PF_UART1_TXD,
	PE13_PF_UART1_RXD,
	PE14_PF_UART1_CTS,
	PE15_PF_UART1_RTS,

	/* UART3 (IrDA) - only TXD and RXD */
	PE8_PF_UART3_TXD,
	PE9_PF_UART3_RXD,

	/* UART4 */
	PB26_AF_UART4_RTS,
	PB28_AF_UART4_TXD,
	PB29_AF_UART4_CTS,
	PB31_AF_UART4_RXD,

	/* LCDC */
	PA5_PF_LSCLK,
	PA6_PF_LD0,
	PA7_PF_LD1,
	PA8_PF_LD2,
	PA9_PF_LD3,
	PA10_PF_LD4,
	PA11_PF_LD5,
	PA12_PF_LD6,
	PA13_PF_LD7,
	PA14_PF_LD8,
	PA15_PF_LD9,
	PA16_PF_LD10,
	PA17_PF_LD11,
	PA18_PF_LD12,
	PA19_PF_LD13,
	PA20_PF_LD14,
	PA21_PF_LD15,
	PA22_PF_LD16,
	PA24_PF_REV,     /* Sharp panel dedicated signal */
	PA25_PF_CLS,     /* Sharp panel dedicated signal */
	PA26_PF_PS,      /* Sharp panel dedicated signal */
	PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
	PA28_PF_HSYNC,
	PA29_PF_VSYNC,
	PA30_PF_CONTRAST,
	PA31_PF_OE_ACD,

	/* MMC/SDHC */
	PE18_PF_SD1_D0,
	PE19_PF_SD1_D1,
	PE20_PF_SD1_D2,
	PE21_PF_SD1_D3,
	PE22_PF_SD1_CMD,
	PE23_PF_SD1_CLK,

	/* NFC */
	PF0_PF_NRFB,
	PF1_PF_NFCE,
	PF2_PF_NFWP,
	PF3_PF_NFCLE,
	PF4_PF_NFALE,
	PF5_PF_NFRE,
	PF6_PF_NFWE,
	PF7_PF_NFIO0,
	PF8_PF_NFIO1,
	PF9_PF_NFIO2,
	PF10_PF_NFIO3,
	PF11_PF_NFIO4,
	PF12_PF_NFIO5,
	PF13_PF_NFIO6,
	PF14_PF_NFIO7,
};

/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
static struct physmap_flash_data mx21ads_flash_data = {
	.width = 4,
};

static struct resource mx21ads_flash_resource = {
	.start = MX21_CS0_BASE_ADDR,
	.end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
	.flags = IORESOURCE_MEM,
};

static struct platform_device mx21ads_nor_mtd_device = {
	.name = "physmap-flash",
	.id = 0,
	.dev = {
		.platform_data = &mx21ads_flash_data,
	},
	.num_resources = 1,
	.resource = &mx21ads_flash_resource,
};

static struct imxuart_platform_data uart_pdata = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static struct imxuart_platform_data uart_norts_pdata = {
};


static int mx21ads_fb_init(struct platform_device *pdev)
{
	u16 tmp;

	tmp = __raw_readw(MX21ADS_IO_REG);
	tmp |= MX21ADS_IO_LCDON;
	__raw_writew(tmp, MX21ADS_IO_REG);
	return 0;
}

static void mx21ads_fb_exit(struct platform_device *pdev)
{
	u16 tmp;

	tmp = __raw_readw(MX21ADS_IO_REG);
	tmp &= ~MX21ADS_IO_LCDON;
	__raw_writew(tmp, MX21ADS_IO_REG);
}

/*
 * Connected is a portrait Sharp-QVGA display
 * of type: LQ035Q7DB02
 */
static struct imx_fb_videomode mx21ads_modes[] = {
	{
		.mode = {
			.name		= "Sharp-LQ035Q7",
			.refresh	= 60,
			.xres		= 240,
			.yres		= 320,
			.pixclock	= 188679, /* in ps (5.3MHz) */
			.hsync_len	= 2,
			.left_margin	= 6,
			.right_margin	= 16,
			.vsync_len	= 1,
			.upper_margin	= 8,
			.lower_margin	= 10,
		},
		.pcr		= 0xfb108bc7,
		.bpp		= 16,
	},
};

static struct imx_fb_platform_data mx21ads_fb_data = {
	.mode = mx21ads_modes,
	.num_modes = ARRAY_SIZE(mx21ads_modes),

	.pwmr		= 0x00a903ff,
	.lscr1		= 0x00120300,
	.dmacr		= 0x00020008,

	.init = mx21ads_fb_init,
	.exit = mx21ads_fb_exit,
};

static int mx21ads_sdhc_get_ro(struct device *dev)
{
	return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
}

static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
	void *data)
{
	int ret;

	ret = request_irq(IRQ_GPIOD(25), detect_irq,
		IRQF_TRIGGER_FALLING, "mmc-detect", data);
	if (ret)
		goto out;
	return 0;
out:
	return ret;
}

static void mx21ads_sdhc_exit(struct device *dev, void *data)
{
	free_irq(IRQ_GPIOD(25), data);
}

static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
	.ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
	.get_ro = mx21ads_sdhc_get_ro,
	.init = mx21ads_sdhc_init,
	.exit = mx21ads_sdhc_exit,
};

static struct mxc_nand_platform_data mx21ads_nand_board_info = {
	.width = 1,
	.hw_ecc = 1,
};

static struct map_desc mx21ads_io_desc[] __initdata = {
	/*
	 * Memory-mapped I/O on MX21ADS Base board:
	 *   - CS8900A Ethernet controller
	 *   - ST16C2552CJ UART
	 *   - CPU and Base board version
	 *   - Base board I/O register
	 */
	{
		.virtual = MX21ADS_MMIO_BASE_ADDR,
		.pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
		.length = MX21ADS_MMIO_SIZE,
		.type = MT_DEVICE,
	},
};

static void __init mx21ads_map_io(void)
{
	mx21_map_io();
	iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
}

static struct platform_device *platform_devices[] __initdata = {
	&mx21ads_nor_mtd_device,
};

static void __init mx21ads_board_init(void)
{
	mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
			"mx21ads");

	mxc_register_device(&imx2x_uart_device0, &uart_pdata);
	mxc_register_device(&imx2x_uart_device2, &uart_norts_pdata);
	mxc_register_device(&imx2x_uart_device3, &uart_pdata);
	mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
	mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
	mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);

	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}

static void __init mx21ads_timer_init(void)
{
	mx21_clocks_init(32768, 26000000);
}

static struct sys_timer mx21ads_timer = {
	.init	= mx21ads_timer_init,
};

MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
	/* maintainer: Freescale Semiconductor, Inc. */
	.phys_io        = MX21_AIPI_BASE_ADDR,
	.io_pg_offst    = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
	.boot_params    = MX21_PHYS_OFFSET + 0x100,
	.map_io         = mx21ads_map_io,
	.init_irq       = mx21_init_irq,
	.init_machine   = mx21ads_board_init,
	.timer          = &mx21ads_timer,
MACHINE_END
Commit	Line	Data
6b91edde IC	1	/*
	2	* Copyright (C) 2000 Deep Blue Solutions Ltd
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
6b91edde IC	15	*/
	16
	17	#include <linux/platform_device.h>
	18	#include <linux/mtd/mtd.h>
	19	#include <linux/mtd/physmap.h>
	20	#include <linux/gpio.h>
	21	#include <mach/common.h>
	22	#include <mach/hardware.h>
	23	#include <asm/mach-types.h>
	24	#include <asm/mach/arch.h>
	25	#include <asm/mach/time.h>
	26	#include <asm/mach/map.h>
	27	#include <mach/imx-uart.h>
	28	#include <mach/imxfb.h>
e835d88e	29	#include <mach/iomux-mx21.h>
6b91edde IC	30	#include <mach/mxc_nand.h>
6b91edde IC	31	#include <mach/mmc.h>
6b91edde IC	32
	33	#include "devices.h"
	34
d393d43f UKK	35	/*
	36	* Memory-mapped I/O on MX21ADS base board
	37	*/
	38	#define MX21ADS_MMIO_BASE_ADDR 0xf5000000
	39	#define MX21ADS_MMIO_SIZE SZ_16M
	40
	41	#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
	42	(MX21ADS_MMIO_BASE_ADDR + (offset))
	43
	44	#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
	45	#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000)
	46	#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
	47	#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
	48	#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
	49
	50	/* MX21ADS_IO_REG bit definitions */
	51	#define MX21ADS_IO_SD_WP 0x0001 /* read */
	52	#define MX21ADS_IO_TP6 0x0001 /* write */
	53	#define MX21ADS_IO_SW_SEL 0x0002 /* read */
	54	#define MX21ADS_IO_TP7 0x0002 /* write */
	55	#define MX21ADS_IO_RESET_E_UART 0x0004
	56	#define MX21ADS_IO_RESET_BASE 0x0008
	57	#define MX21ADS_IO_CSI_CTL2 0x0010
	58	#define MX21ADS_IO_CSI_CTL1 0x0020
	59	#define MX21ADS_IO_CSI_CTL0 0x0040
	60	#define MX21ADS_IO_UART1_EN 0x0080
	61	#define MX21ADS_IO_UART4_EN 0x0100
	62	#define MX21ADS_IO_LCDON 0x0200
	63	#define MX21ADS_IO_IRDA_EN 0x0400
	64	#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
	65	#define MX21ADS_IO_IRDA_MD0_B 0x1000
	66	#define MX21ADS_IO_IRDA_MD1 0x2000
	67	#define MX21ADS_IO_LED4_ON 0x4000
	68	#define MX21ADS_IO_LED3_ON 0x8000
	69
6b91edde IC	70	static unsigned int mx21ads_pins[] = {
	71
	72	/* CS8900A */
	73	(GPIO_PORTE \| GPIO_GPIO \| GPIO_IN \| 11),
	74
	75	/* UART1 */
	76	PE12_PF_UART1_TXD,
	77	PE13_PF_UART1_RXD,
	78	PE14_PF_UART1_CTS,
	79	PE15_PF_UART1_RTS,
	80
	81	/* UART3 (IrDA) - only TXD and RXD */
	82	PE8_PF_UART3_TXD,
	83	PE9_PF_UART3_RXD,
	84
	85	/* UART4 */
	86	PB26_AF_UART4_RTS,
	87	PB28_AF_UART4_TXD,
	88	PB29_AF_UART4_CTS,
	89	PB31_AF_UART4_RXD,
	90
	91	/* LCDC */
	92	PA5_PF_LSCLK,
	93	PA6_PF_LD0,
	94	PA7_PF_LD1,
	95	PA8_PF_LD2,
	96	PA9_PF_LD3,
	97	PA10_PF_LD4,
	98	PA11_PF_LD5,
	99	PA12_PF_LD6,
	100	PA13_PF_LD7,
	101	PA14_PF_LD8,
	102	PA15_PF_LD9,
	103	PA16_PF_LD10,
	104	PA17_PF_LD11,
	105	PA18_PF_LD12,
	106	PA19_PF_LD13,
	107	PA20_PF_LD14,
	108	PA21_PF_LD15,
	109	PA22_PF_LD16,
	110	PA24_PF_REV, /* Sharp panel dedicated signal */
	111	PA25_PF_CLS, /* Sharp panel dedicated signal */
	112	PA26_PF_PS, /* Sharp panel dedicated signal */
	113	PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
	114	PA28_PF_HSYNC,
	115	PA29_PF_VSYNC,
	116	PA30_PF_CONTRAST,
	117	PA31_PF_OE_ACD,
	118
	119	/* MMC/SDHC */
	120	PE18_PF_SD1_D0,
	121	PE19_PF_SD1_D1,
	122	PE20_PF_SD1_D2,
	123	PE21_PF_SD1_D3,
	124	PE22_PF_SD1_CMD,
	125	PE23_PF_SD1_CLK,
	126
	127	/* NFC */
	128	PF0_PF_NRFB,
	129	PF1_PF_NFCE,
	130	PF2_PF_NFWP,
	131	PF3_PF_NFCLE,
	132	PF4_PF_NFALE,
	133	PF5_PF_NFRE,
134	PF6_PF_NFWE,
135	PF7_PF_NFIO0,
136	PF8_PF_NFIO1,
137	PF9_PF_NFIO2,
138	PF10_PF_NFIO3,
139	PF11_PF_NFIO4,
140	PF12_PF_NFIO5,
141	PF13_PF_NFIO6,
142	PF14_PF_NFIO7,
143	};
144
145	/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
146	static struct physmap_flash_data mx21ads_flash_data = {
147	.width = 4,
148	};
149
150	static struct resource mx21ads_flash_resource = {
3f35d1f5 UKK	151	.start = MX21_CS0_BASE_ADDR,
3f35d1f5 UKK	152	.end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
6b91edde IC	153	.flags = IORESOURCE_MEM,
	154	};
	155
	156	static struct platform_device mx21ads_nor_mtd_device = {
	157	.name = "physmap-flash",
	158	.id = 0,
	159	.dev = {
	160	.platform_data = &mx21ads_flash_data,
	161	},
	162	.num_resources = 1,
	163	.resource = &mx21ads_flash_resource,
	164	};
	165
	166	static struct imxuart_platform_data uart_pdata = {
	167	.flags = IMXUART_HAVE_RTSCTS,
	168	};
	169
	170	static struct imxuart_platform_data uart_norts_pdata = {
	171	};
	172
	173
	174	static int mx21ads_fb_init(struct platform_device *pdev)
	175	{
	176	u16 tmp;
	177
	178	tmp = __raw_readw(MX21ADS_IO_REG);
	179	tmp \|= MX21ADS_IO_LCDON;
	180	__raw_writew(tmp, MX21ADS_IO_REG);
	181	return 0;
	182	}
	183
	184	static void mx21ads_fb_exit(struct platform_device *pdev)
	185	{
	186	u16 tmp;
	187
	188	tmp = __raw_readw(MX21ADS_IO_REG);
	189	tmp &= ~MX21ADS_IO_LCDON;
	190	__raw_writew(tmp, MX21ADS_IO_REG);
	191	}
	192
	193	/*
	194	* Connected is a portrait Sharp-QVGA display
	195	* of type: LQ035Q7DB02
	196	*/
c35d3a41 SH	197	static struct imx_fb_videomode mx21ads_modes[] = {
	198	{
	199	.mode = {
	200	.name = "Sharp-LQ035Q7",
	201	.refresh = 60,
	202	.xres = 240,
	203	.yres = 320,
	204	.pixclock = 188679, /* in ps (5.3MHz) */
	205	.hsync_len = 2,
	206	.left_margin = 6,
	207	.right_margin = 16,
	208	.vsync_len = 1,
	209	.upper_margin = 8,
	210	.lower_margin = 10,
	211	},
	212	.pcr = 0xfb108bc7,
	213	.bpp = 16,
	214	},
	215	};
	216
6b91edde	217	static struct imx_fb_platform_data mx21ads_fb_data = {
c35d3a41 SH	218	.mode = mx21ads_modes,
	219	.num_modes = ARRAY_SIZE(mx21ads_modes),
	220
	221	.pwmr = 0x00a903ff,
	222	.lscr1 = 0x00120300,
	223	.dmacr = 0x00020008,
6b91edde IC	224
	225	.init = mx21ads_fb_init,
	226	.exit = mx21ads_fb_exit,
	227	};
	228
	229	static int mx21ads_sdhc_get_ro(struct device *dev)
	230	{
	231	return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
	232	}
	233
	234	static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
	235	void *data)
	236	{
	237	int ret;
	238
	239	ret = request_irq(IRQ_GPIOD(25), detect_irq,
	240	IRQF_TRIGGER_FALLING, "mmc-detect", data);
	241	if (ret)
	242	goto out;
	243	return 0;
	244	out:
	245	return ret;
	246	}
	247
	248	static void mx21ads_sdhc_exit(struct device dev, void data)
	249	{
	250	free_irq(IRQ_GPIOD(25), data);
	251	}
	252
	253	static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
	254	.ocr_avail = MMC_VDD_29_30 \| MMC_VDD_30_31, /* 3.0V */
	255	.get_ro = mx21ads_sdhc_get_ro,
	256	.init = mx21ads_sdhc_init,
	257	.exit = mx21ads_sdhc_exit,
	258	};
	259
	260	static struct mxc_nand_platform_data mx21ads_nand_board_info = {
	261	.width = 1,
	262	.hw_ecc = 1,
	263	};
	264
	265	static struct map_desc mx21ads_io_desc[] __initdata = {
	266	/*
	267	* Memory-mapped I/O on MX21ADS Base board:
	268	* - CS8900A Ethernet controller
	269	* - ST16C2552CJ UART
	270	* - CPU and Base board version
	271	* - Base board I/O register
	272	*/
	273	{
	274	.virtual = MX21ADS_MMIO_BASE_ADDR,
3f35d1f5	275	.pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
6b91edde IC	276	.length = MX21ADS_MMIO_SIZE,
	277	.type = MT_DEVICE,
	278	},
	279	};
	280
	281	static void __init mx21ads_map_io(void)
	282	{
	283	mx21_map_io();
	284	iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
	285	}
	286
	287	static struct platform_device *platform_devices[] __initdata = {
	288	&mx21ads_nor_mtd_device,
	289	};
	290
	291	static void __init mx21ads_board_init(void)
	292	{
	293	mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
	294	"mx21ads");
	295
551823e7 UKK	296	mxc_register_device(&imx2x_uart_device0, &uart_pdata);
	297	mxc_register_device(&imx2x_uart_device2, &uart_norts_pdata);
	298	mxc_register_device(&imx2x_uart_device3, &uart_pdata);
6b91edde IC	299	mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
6b91edde IC	300	mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
3636a145	301	mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
6b91edde IC	302
	303	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
	304	}
	305
	306	static void __init mx21ads_timer_init(void)
	307	{
	308	mx21_clocks_init(32768, 26000000);
	309	}
	310
	311	static struct sys_timer mx21ads_timer = {
	312	.init = mx21ads_timer_init,
	313	};
	314
	315	MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
	316	/* maintainer: Freescale Semiconductor, Inc. */
3f35d1f5 UKK	317	.phys_io = MX21_AIPI_BASE_ADDR,
3f35d1f5 UKK	318	.io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
34101237	319	.boot_params = MX21_PHYS_OFFSET + 0x100,
6b91edde	320	.map_io = mx21ads_map_io,
c5aa0ad0	321	.init_irq = mx21_init_irq,
6b91edde IC	322	.init_machine = mx21ads_board_init,
	323	.timer = &mx21ads_timer,
	324	MACHINE_END