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Merge tag 'for-linus-v3.10-rc3' of git://oss.sgi.com/xfs/xfs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-imx / clk-imx6q.c
CommitLineData
2acd1b6f 1/*
e7b82d64 2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
2acd1b6f
SG		 3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/types.h>
15#include <linux/clk.h>
16#include <linux/clkdev.h>
263475d4 17#include <linux/delay.h>
2acd1b6f
SG		 18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
e3372474 23
2acd1b6f 24#include "clk.h"
e3372474 25#include "common.h"
2df1d026 26#include "hardware.h"
2acd1b6f 27
e7b82d64
AH		 28#define CCR 0x0
29#define BM_CCR_WB_COUNT (0x7 << 16)
263475d4
AH		 30#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
31#define BM_CCR_RBC_EN (0x1 << 27)
e7b82d64 32
2acd1b6f
SG		 33#define CCGR0 0x68
34#define CCGR1 0x6c
35#define CCGR2 0x70
36#define CCGR3 0x74
37#define CCGR4 0x78
38#define CCGR5 0x7c
39#define CCGR6 0x80
40#define CCGR7 0x84
41
42#define CLPCR 0x54
43#define BP_CLPCR_LPM 0
44#define BM_CLPCR_LPM (0x3 << 0)
45#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
46#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
47#define BM_CLPCR_SBYOS (0x1 << 6)
48#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
49#define BM_CLPCR_VSTBY (0x1 << 8)
50#define BP_CLPCR_STBY_COUNT 9
51#define BM_CLPCR_STBY_COUNT (0x3 << 9)
52#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
53#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
54#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
55#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
56#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
57#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
58#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
59#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
60#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
61#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
62#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
63
e5f9dec8
SG		 64#define CGPR 0x64
65#define BM_CGPR_CHICKEN_BIT (0x1 << 17)
66
2acd1b6f
SG		 67static void __iomem *ccm_base;
68
e5f9dec8
SG		 69void imx6q_set_chicken_bit(void)
70{
71 u32 val = readl_relaxed(ccm_base + CGPR);
72
73 val |= BM_CGPR_CHICKEN_BIT;
74 writel_relaxed(val, ccm_base + CGPR);
75}
2acd1b6f 76
263475d4
AH		 77static void imx6q_enable_rbc(bool enable)
78{
79 u32 val;
80 static bool last_rbc_mode;
81
82 if (last_rbc_mode == enable)
83 return;
84 /*
85 * need to mask all interrupts in GPC before
86 * operating RBC configurations
87 */
88 imx_gpc_mask_all();
89
90 /* configure RBC enable bit */
91 val = readl_relaxed(ccm_base + CCR);
92 val &= ~BM_CCR_RBC_EN;
93 val |= enable ? BM_CCR_RBC_EN : 0;
94 writel_relaxed(val, ccm_base + CCR);
95
96 /* configure RBC count */
97 val = readl_relaxed(ccm_base + CCR);
98 val &= ~BM_CCR_RBC_BYPASS_COUNT;
99 val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
100 writel(val, ccm_base + CCR);
101
102 /*
103 * need to delay at least 2 cycles of CKIL(32K)
104 * due to hardware design requirement, which is
105 * ~61us, here we use 65us for safe
106 */
107 udelay(65);
108
109 /* restore GPC interrupt mask settings */
110 imx_gpc_restore_all();
111
112 last_rbc_mode = enable;
113}
114
e7b82d64
AH		 115static void imx6q_enable_wb(bool enable)
116{
117 u32 val;
118 static bool last_wb_mode;
119
120 if (last_wb_mode == enable)
121 return;
122
123 /* configure well bias enable bit */
124 val = readl_relaxed(ccm_base + CLPCR);
125 val &= ~BM_CLPCR_WB_PER_AT_LPM;
126 val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
127 writel_relaxed(val, ccm_base + CLPCR);
128
129 /* configure well bias count */
130 val = readl_relaxed(ccm_base + CCR);
131 val &= ~BM_CCR_WB_COUNT;
132 val |= enable ? BM_CCR_WB_COUNT : 0;
133 writel_relaxed(val, ccm_base + CCR);
134
135 last_wb_mode = enable;
136}
137
2acd1b6f
SG		 138int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
139{
140 u32 val = readl_relaxed(ccm_base + CLPCR);
141
142 val &= ~BM_CLPCR_LPM;
143 switch (mode) {
144 case WAIT_CLOCKED:
e7b82d64 145 imx6q_enable_wb(false);
263475d4 146 imx6q_enable_rbc(false);
2acd1b6f
SG		 147 break;
148 case WAIT_UNCLOCKED:
149 val |= 0x1 << BP_CLPCR_LPM;
e5f9dec8 150 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
2acd1b6f
SG		 151 break;
152 case STOP_POWER_ON:
153 val |= 0x2 << BP_CLPCR_LPM;
154 break;
155 case WAIT_UNCLOCKED_POWER_OFF:
156 val |= 0x1 << BP_CLPCR_LPM;
157 val &= ~BM_CLPCR_VSTBY;
158 val &= ~BM_CLPCR_SBYOS;
159 break;
160 case STOP_POWER_OFF:
161 val |= 0x2 << BP_CLPCR_LPM;
162 val |= 0x3 << BP_CLPCR_STBY_COUNT;
163 val |= BM_CLPCR_VSTBY;
164 val |= BM_CLPCR_SBYOS;
e7b82d64 165 imx6q_enable_wb(true);
263475d4 166 imx6q_enable_rbc(true);
2acd1b6f
SG		 167 break;
168 default:
169 return -EINVAL;
170 }
171
172 writel_relaxed(val, ccm_base + CLPCR);
173
174 return 0;
175}
176
177static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
178static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
179static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
72cd7447
PZ		 180static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
181static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
2acd1b6f
SG		 182static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
183static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
184static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
2df1d026 185static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
2acd1b6f
SG		 186static const char *gpu_axi_sels[] = { "axi", "ahb", };
187static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
188static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
de78a23d 189static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
2acd1b6f 190static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
e8094b2c 191static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
2df1d026 192static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
2acd1b6f
SG		 193static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
194static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
195static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
196static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
197static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", };
198static const char *pcie_axi_sels[] = { "axi", "ahb", };
2df1d026 199static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", };
2acd1b6f
SG		 200static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
201static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
202static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
203static const char *vdo_axi_sels[] = { "axi", "ahb", };
204static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
2df1d026 205static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
2acd1b6f 206 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
2df1d026 207 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };
2acd1b6f 208
2acd1b6f
SG		 209enum mx6q_clks {
210 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
211 pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
212 pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
213 periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
214 esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
215 gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
216 ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
217 ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
218 ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
219 usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
220 emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
221 periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
222 asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
223 gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
224 ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
225 ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
226 ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
227 usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
228 emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
229 mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
230 can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
231 esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
232 hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
233 ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
77ac32ad 234 mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
2acd1b6f
SG		 235 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
236 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
237 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
13861701 238 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
16339464 239 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
a5120e89 240 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
2df1d026 241 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
2acd1b6f
SG		 242};
243
244static struct clk *clk[clk_max];
0e87e043 245static struct clk_onecell_data clk_data;
2acd1b6f 246
b0286f20 247static enum mx6q_clks const clks_init_on[] __initconst = {
39581662 248 mmdc_ch0_axi, rom, pll1_sys,
b0286f20
RZ		 249};
250
7a04092c
SH		 251static struct clk_div_table clk_enet_ref_table[] = {
252 { .val = 0, .div = 20, },
253 { .val = 1, .div = 10, },
254 { .val = 2, .div = 5, },
255 { .val = 3, .div = 4, },
256};
257
2df1d026
PZ		 258static struct clk_div_table post_div_table[] = {
259 { .val = 2, .div = 1, },
260 { .val = 1, .div = 2, },
261 { .val = 0, .div = 4, },
262 { }
263};
264
265static struct clk_div_table video_div_table[] = {
266 { .val = 0, .div = 1, },
267 { .val = 1, .div = 2, },
268 { .val = 2, .div = 1, },
269 { .val = 3, .div = 4, },
270 { }
271};
272
2acd1b6f
SG		 273int __init mx6q_clocks_init(void)
274{
275 struct device_node *np;
276 void __iomem *base;
2acd1b6f
SG		 277 int i, irq;
278
279 clk[dummy] = imx_clk_fixed("dummy", 0);
280
281 /* retrieve the freqency of fixed clocks from device tree */
282 for_each_compatible_node(np, NULL, "fixed-clock") {
283 u32 rate;
284 if (of_property_read_u32(np, "clock-frequency", &rate))
285 continue;
286
287 if (of_device_is_compatible(np, "fsl,imx-ckil"))
288 clk[ckil] = imx_clk_fixed("ckil", rate);
289 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
290 clk[ckih] = imx_clk_fixed("ckih", rate);
291 else if (of_device_is_compatible(np, "fsl,imx-osc"))
292 clk[osc] = imx_clk_fixed("osc", rate);
293 }
294
295 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
296 base = of_iomap(np, 0);
297 WARN_ON(!base);
298
2df1d026 299 /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
3c03a2fe 300 if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) {
2df1d026
PZ		 301 post_div_table[1].div = 1;
302 post_div_table[2].div = 1;
303 video_div_table[1].div = 1;
304 video_div_table[2].div = 1;
305 };
306
2b254693
SH		 307 /* type name parent_name base div_mask */
308 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
309 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
310 clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
311 clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
312 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
313 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
314 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
315 clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
2acd1b6f 316
a5120e89
PC		 317 /*
318 * Bit 20 is the reserved and read-only bit, we do this only for:
319 * - Do nothing for usbphy clk_enable/disable
320 * - Keep refcount when do usbphy clk_enable/disable, in that case,
321 * the clk framework may need to enable/disable usbphy's parent
322 */
323 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
324 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
325
326 /*
327 * usbphy*_gate needs to be on after system boots up, and software
328 * never needs to control it anymore.
329 */
330 clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
331 clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
7571d283 332
7a04092c
SH		 333 clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
334 clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
335
336 clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
337 clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
338
339 clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
340 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
341 &imx_ccm_lock);
342
2acd1b6f
SG		 343 /* name parent_name reg idx */
344 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
345 clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
346 clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
347 clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
348 clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
349 clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
350 clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
351
352 /* name parent_name mult div */
353 clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
354 clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
355 clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
356 clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
357 clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
358
2df1d026
PZ		 359 clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
360 clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
361 clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
362
2acd1b6f
SG		 363 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
364 base = of_iomap(np, 0);
365 WARN_ON(!base);
366 ccm_base = base;
367
368 /* name reg shift width parent_names num_parents */
369 clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
370 clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
371 clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
372 clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
72cd7447
PZ		 373 clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
374 clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
2acd1b6f
SG		 375 clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
376 clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
377 clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
378 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
379 clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
380 clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
381 clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
382 clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
383 clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
384 clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
385 clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
d19dacb7
PZ		 386 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
387 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
2acd1b6f
SG		 388 clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
389 clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
390 clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
391 clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
392 clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
393 clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
394 clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
395 clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
396 clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
397 clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
398 clk[ssi1_sel] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
399 clk[ssi2_sel] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
400 clk[ssi3_sel] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
401 clk[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
402 clk[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
403 clk[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
404 clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
405 clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
406 clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels));
407 clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels));
408 clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
409 clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
410 clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
411
412 /* name reg shift width busy: reg, shift parent_names num_parents */
413 clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
414 clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
415
416 /* name parent_name reg shift width */
417 clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
418 clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
419 clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
420 clk[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6);
421 clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
422 clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
423 clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
424 clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
425 clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
426 clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
427 clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6);
428 clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
429 clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
430 clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
431 clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
432 clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
433 clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
16339464 434 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
d19dacb7 435 clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
16339464 436 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
d19dacb7 437 clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
2acd1b6f
SG		 438 clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
439 clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
440 clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
441 clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
442 clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
443 clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
444 clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
445 clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
446 clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
447 clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
448 clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
449 clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
450 clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
451 clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
452 clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
453 clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
454 clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
455 clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
456 clk[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3);
457 clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3);
458 clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
459 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
460
461 /* name parent_name reg shift width busy: reg, shift */
462 clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
463 clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
464 clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
465 clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
466 clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
467
468 /* name parent_name reg shift */
10a81378 469 clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
2acd1b6f
SG		 470 clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
471 clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
472 clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
473 clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
474 clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
475 clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
476 clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
477 clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
478 clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
479 clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
480 clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
481 clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
482 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
483 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
484 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
485 clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
486 clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
487 clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
488 clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
489 clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
490 clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
491 clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
492 clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
493 clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
494 clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
495 clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
496 clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
497 clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
498 clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
499 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
500 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
501 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
0e574461 502 clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
2acd1b6f
SG		 503 clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
504 clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
505 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
506 clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
507 clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
77ac32ad 508 clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
2acd1b6f
SG		 509 clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
510 clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
511 clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
512 clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
513 clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
514 clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
515 clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
516 clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
5ae95aef 517 clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
2acd1b6f
SG		 518 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
519 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
520 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
0987b598
RZ		 521 clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
522 clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
523 clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
2acd1b6f
SG		 524 clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
525 clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
526 clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
527 clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
528 clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
529 clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
530 clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
531 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
532 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
533 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
534
535 for (i = 0; i < ARRAY_SIZE(clk); i++)
536 if (IS_ERR(clk[i]))
537 pr_err("i.MX6q clk %d: register failed with %ld\n",
538 i, PTR_ERR(clk[i]));
539
0e87e043
SG		 540 clk_data.clks = clk;
541 clk_data.clk_num = ARRAY_SIZE(clk);
542 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
543
2acd1b6f
SG		 544 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
545 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
a258561d
RZ		 546 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
547 clk_register_clkdev(clk[ahb], "ahb", NULL);
548 clk_register_clkdev(clk[cko1], "cko1", NULL);
d90df978 549 clk_register_clkdev(clk[arm], NULL, "cpu0");
2acd1b6f 550
32f3b8da
PZ		 551 if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
552 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
553 clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
554 }
555
cc7887c3
HS		 556 /*
557 * The gpmi needs 100MHz frequency in the EDO/Sync mode,
558 * We can not get the 100MHz from the pll2_pfd0_352m.
559 * So choose pll2_pfd2_396m as enfc_sel's parent.
560 */
561 clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
562
b0286f20
RZ		 563 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
564 clk_prepare_enable(clk[clks_init_on[i]]);
2acd1b6f 565
a5120e89
PC		 566 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
567 clk_prepare_enable(clk[usbphy1_gate]);
568 clk_prepare_enable(clk[usbphy2_gate]);
569 }
570
83ae2098
SG		 571 /* Set initial power mode */
572 imx6q_set_lpm(WAIT_CLOCKED);
573
2acd1b6f
SG		 574 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
575 base = of_iomap(np, 0);
576 WARN_ON(!base);
577 irq = irq_of_parse_and_map(np, 0);
2cfb4518 578 mxc_timer_init(base, irq);
2acd1b6f
SG		 579
580 return 0;
581}
kernel source for telekom puls (alcatel/mediatek)