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clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-exynos / common.c
CommitLineData
cc511b8d
KK		 1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
a900e5d9 15#include <linux/irqchip.h>
cc511b8d 16#include <linux/io.h>
7affca35 17#include <linux/device.h>
cc511b8d
KK		 18#include <linux/gpio.h>
19#include <linux/sched.h>
20#include <linux/serial_core.h>
237c78be 21#include <linux/of.h>
5b7897db 22#include <linux/of_fdt.h>
237c78be 23#include <linux/of_irq.h>
1e60bc0b
TA		 24#include <linux/export.h>
25#include <linux/irqdomain.h>
0529e315 26#include <linux/irqchip.h>
e873a47c 27#include <linux/of_address.h>
6923ae4b
TA		 28#include <linux/clocksource.h>
29#include <linux/clk-provider.h>
520f7bd7 30#include <linux/irqchip/arm-gic.h>
cc511b8d
KK		 31
32#include <asm/proc-fns.h>
40ba95fd 33#include <asm/exception.h>
cc511b8d 34#include <asm/hardware/cache-l2x0.h>
cc511b8d
KK		 35#include <asm/mach/map.h>
36#include <asm/mach/irq.h>
b756a50f 37#include <asm/cacheflush.h>
cc511b8d
KK		 38
39#include <mach/regs-irq.h>
40#include <mach/regs-pmu.h>
41#include <mach/regs-gpio.h>
42
43#include <plat/cpu.h>
cc511b8d
KK		 44#include <plat/devs.h>
45#include <plat/pm.h>
cc511b8d
KK		 46#include <plat/sdhci.h>
47#include <plat/gpio-cfg.h>
48#include <plat/adc-core.h>
49#include <plat/fb-core.h>
50#include <plat/fimc-core.h>
51#include <plat/iic-core.h>
52#include <plat/tv-core.h>
308b3afb 53#include <plat/spi-core.h>
cc511b8d
KK		 54#include <plat/regs-serial.h>
55
56#include "common.h"
6cdeddcc
ADK		 57#define L2_AUX_VAL 0x7C470001
58#define L2_AUX_MASK 0xC200ffff
cc511b8d 59
cc511b8d
KK		 60static const char name_exynos4210[] = "EXYNOS4210";
61static const char name_exynos4212[] = "EXYNOS4212";
62static const char name_exynos4412[] = "EXYNOS4412";
94c7ca71 63static const char name_exynos5250[] = "EXYNOS5250";
2edb36c4 64static const char name_exynos5440[] = "EXYNOS5440";
cc511b8d 65
906c789c 66static void exynos4_map_io(void);
94c7ca71 67static void exynos5_map_io(void);
2edb36c4 68static void exynos5440_map_io(void);
55b6ef7a 69static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
906c789c 70static int exynos_init(void);
cc511b8d 71
92744274
TA		 72unsigned long xxti_f = 0, xusbxti_f = 0;
73
cc511b8d
KK		 74static struct cpu_table cpu_ids[] __initdata = {
75 {
76 .idcode = EXYNOS4210_CPU_ID,
77 .idmask = EXYNOS4_CPU_MASK,
78 .map_io = exynos4_map_io,
55b6ef7a 79 .init_uarts = exynos4_init_uarts,
cc511b8d
KK		 80 .init = exynos_init,
81 .name = name_exynos4210,
82 }, {
83 .idcode = EXYNOS4212_CPU_ID,
84 .idmask = EXYNOS4_CPU_MASK,
85 .map_io = exynos4_map_io,
55b6ef7a 86 .init_uarts = exynos4_init_uarts,
cc511b8d
KK		 87 .init = exynos_init,
88 .name = name_exynos4212,
89 }, {
90 .idcode = EXYNOS4412_CPU_ID,
91 .idmask = EXYNOS4_CPU_MASK,
92 .map_io = exynos4_map_io,
55b6ef7a 93 .init_uarts = exynos4_init_uarts,
cc511b8d
KK		 94 .init = exynos_init,
95 .name = name_exynos4412,
94c7ca71
KK		 96 }, {
97 .idcode = EXYNOS5250_SOC_ID,
98 .idmask = EXYNOS5_SOC_MASK,
99 .map_io = exynos5_map_io,
94c7ca71
KK		 100 .init = exynos_init,
101 .name = name_exynos5250,
2edb36c4
KK		 102 }, {
103 .idcode = EXYNOS5440_SOC_ID,
104 .idmask = EXYNOS5_SOC_MASK,
105 .map_io = exynos5440_map_io,
106 .init = exynos_init,
107 .name = name_exynos5440,
cc511b8d
KK		 108 },
109};
110
111/* Initial IO mappings */
112
113static struct map_desc exynos_iodesc[] __initdata = {
114 {
115 .virtual = (unsigned long)S5P_VA_CHIPID,
94c7ca71 116 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
cc511b8d
KK		 117 .length = SZ_4K,
118 .type = MT_DEVICE,
94c7ca71
KK		 119 },
120};
121
5b7897db 122#ifdef CONFIG_ARCH_EXYNOS5
2edb36c4
KK		 123static struct map_desc exynos5440_iodesc[] __initdata = {
124 {
125 .virtual = (unsigned long)S5P_VA_CHIPID,
126 .pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
127 .length = SZ_4K,
128 .type = MT_DEVICE,
129 },
130};
5b7897db 131#endif
2edb36c4 132
94c7ca71
KK		 133static struct map_desc exynos4_iodesc[] __initdata = {
134 {
cc511b8d
KK		 135 .virtual = (unsigned long)S3C_VA_SYS,
136 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
137 .length = SZ_64K,
138 .type = MT_DEVICE,
139 }, {
140 .virtual = (unsigned long)S3C_VA_TIMER,
141 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
142 .length = SZ_16K,
143 .type = MT_DEVICE,
144 }, {
145 .virtual = (unsigned long)S3C_VA_WATCHDOG,
146 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
147 .length = SZ_4K,
148 .type = MT_DEVICE,
149 }, {
150 .virtual = (unsigned long)S5P_VA_SROMC,
151 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
152 .length = SZ_4K,
153 .type = MT_DEVICE,
154 }, {
155 .virtual = (unsigned long)S5P_VA_SYSTIMER,
156 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
157 .length = SZ_4K,
158 .type = MT_DEVICE,
159 }, {
160 .virtual = (unsigned long)S5P_VA_PMU,
161 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
162 .length = SZ_64K,
163 .type = MT_DEVICE,
164 }, {
165 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
166 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
167 .length = SZ_4K,
168 .type = MT_DEVICE,
169 }, {
170 .virtual = (unsigned long)S5P_VA_GIC_CPU,
171 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
172 .length = SZ_64K,
173 .type = MT_DEVICE,
174 }, {
175 .virtual = (unsigned long)S5P_VA_GIC_DIST,
176 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
177 .length = SZ_64K,
178 .type = MT_DEVICE,
179 }, {
180 .virtual = (unsigned long)S3C_VA_UART,
181 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
182 .length = SZ_512K,
183 .type = MT_DEVICE,
94c7ca71 184 }, {
cc511b8d
KK		 185 .virtual = (unsigned long)S5P_VA_CMU,
186 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
187 .length = SZ_128K,
188 .type = MT_DEVICE,
189 }, {
190 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
191 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
192 .length = SZ_8K,
193 .type = MT_DEVICE,
194 }, {
195 .virtual = (unsigned long)S5P_VA_L2CC,
196 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
197 .length = SZ_4K,
198 .type = MT_DEVICE,
cc511b8d
KK		 199 }, {
200 .virtual = (unsigned long)S5P_VA_DMC0,
201 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
2bde0b08
MH		 202 .length = SZ_64K,
203 .type = MT_DEVICE,
204 }, {
205 .virtual = (unsigned long)S5P_VA_DMC1,
206 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
207 .length = SZ_64K,
cc511b8d 208 .type = MT_DEVICE,
cc511b8d
KK		 209 }, {
210 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
211 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
212 .length = SZ_4K,
213 .type = MT_DEVICE,
214 },
215};
216
217static struct map_desc exynos4_iodesc0[] __initdata = {
218 {
219 .virtual = (unsigned long)S5P_VA_SYSRAM,
220 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
221 .length = SZ_4K,
222 .type = MT_DEVICE,
223 },
224};
225
226static struct map_desc exynos4_iodesc1[] __initdata = {
227 {
228 .virtual = (unsigned long)S5P_VA_SYSRAM,
229 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
230 .length = SZ_4K,
231 .type = MT_DEVICE,
232 },
233};
234
94c7ca71
KK		 235static struct map_desc exynos5_iodesc[] __initdata = {
236 {
237 .virtual = (unsigned long)S3C_VA_SYS,
238 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
239 .length = SZ_64K,
240 .type = MT_DEVICE,
241 }, {
242 .virtual = (unsigned long)S3C_VA_TIMER,
243 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
244 .length = SZ_16K,
245 .type = MT_DEVICE,
246 }, {
247 .virtual = (unsigned long)S3C_VA_WATCHDOG,
248 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
249 .length = SZ_4K,
250 .type = MT_DEVICE,
251 }, {
252 .virtual = (unsigned long)S5P_VA_SROMC,
253 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
254 .length = SZ_4K,
255 .type = MT_DEVICE,
94c7ca71
KK		 256 }, {
257 .virtual = (unsigned long)S5P_VA_SYSRAM,
258 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
259 .length = SZ_4K,
260 .type = MT_DEVICE,
261 }, {
262 .virtual = (unsigned long)S5P_VA_CMU,
263 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
264 .length = 144 * SZ_1K,
265 .type = MT_DEVICE,
266 }, {
267 .virtual = (unsigned long)S5P_VA_PMU,
268 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
269 .length = SZ_64K,
270 .type = MT_DEVICE,
94c7ca71
KK		 271 }, {
272 .virtual = (unsigned long)S3C_VA_UART,
273 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
274 .length = SZ_512K,
275 .type = MT_DEVICE,
94c7ca71
KK		 276 },
277};
278
2edb36c4
KK		 279static struct map_desc exynos5440_iodesc0[] __initdata = {
280 {
281 .virtual = (unsigned long)S3C_VA_UART,
282 .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
283 .length = SZ_512K,
284 .type = MT_DEVICE,
285 },
286};
287
9eb48595 288void exynos4_restart(char mode, const char *cmd)
cc511b8d
KK		 289{
290 __raw_writel(0x1, S5P_SWRESET);
291}
292
94c7ca71
KK		 293void exynos5_restart(char mode, const char *cmd)
294{
60db7e5f 295 struct device_node *np;
2edb36c4
KK		 296 u32 val;
297 void __iomem *addr;
298
299 if (of_machine_is_compatible("samsung,exynos5250")) {
300 val = 0x1;
301 addr = EXYNOS_SWRESET;
302 } else if (of_machine_is_compatible("samsung,exynos5440")) {
60db7e5f
TA		 303 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
304 addr = of_iomap(np, 0) + 0xcc;
305 val = (0xfff << 20) | (0x1 << 16);
2edb36c4
KK		 306 } else {
307 pr_err("%s: cannot support non-DT\n", __func__);
308 return;
309 }
310
311 __raw_writel(val, addr);
94c7ca71
KK		 312}
313
bb13fabc
SG		 314void __init exynos_init_late(void)
315{
2edb36c4
KK		 316 if (of_machine_is_compatible("samsung,exynos5440"))
317 /* to be supported later */
318 return;
319
bb13fabc
SG		 320 exynos_pm_late_initcall();
321}
322
cc511b8d
KK		 323/*
324 * exynos_map_io
325 *
326 * register the standard cpu IO areas
327 */
328
329void __init exynos_init_io(struct map_desc *mach_desc, int size)
330{
5b7897db
DA		 331 struct map_desc *iodesc = exynos_iodesc;
332 int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
333#if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
334 unsigned long root = of_get_flat_dt_root();
335
cc511b8d 336 /* initialize the io descriptors we need for initialization */
5b7897db
DA		 337 if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
338 iodesc = exynos5440_iodesc;
339 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
340 }
341#endif
342
343 iotable_init(iodesc, iodesc_sz);
2edb36c4 344
cc511b8d
KK		 345 if (mach_desc)
346 iotable_init(mach_desc, size);
347
348 /* detect cpu id and rev. */
349 s5p_init_cpu(S5P_VA_CHIPID);
350
351 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
352}
353
906c789c 354static void __init exynos4_map_io(void)
cc511b8d
KK		 355{
356 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
357
358 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
359 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
360 else
361 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
362
363 /* initialize device information early */
364 exynos4_default_sdhci0();
365 exynos4_default_sdhci1();
366 exynos4_default_sdhci2();
367 exynos4_default_sdhci3();
368
369 s3c_adc_setname("samsung-adc-v3");
370
371 s3c_fimc_setname(0, "exynos4-fimc");
372 s3c_fimc_setname(1, "exynos4-fimc");
373 s3c_fimc_setname(2, "exynos4-fimc");
374 s3c_fimc_setname(3, "exynos4-fimc");
375
8482c81c
TA		 376 s3c_sdhci_setname(0, "exynos4-sdhci");
377 s3c_sdhci_setname(1, "exynos4-sdhci");
378 s3c_sdhci_setname(2, "exynos4-sdhci");
379 s3c_sdhci_setname(3, "exynos4-sdhci");
380
cc511b8d
KK		 381 /* The I2C bus controllers are directly compatible with s3c2440 */
382 s3c_i2c0_setname("s3c2440-i2c");
383 s3c_i2c1_setname("s3c2440-i2c");
384 s3c_i2c2_setname("s3c2440-i2c");
385
386 s5p_fb_setname(0, "exynos4-fb");
387 s5p_hdmi_setname("exynos4-hdmi");
308b3afb
HS		 388
389 s3c64xx_spi_setname("exynos4210-spi");
cc511b8d
KK		 390}
391
94c7ca71
KK		 392static void __init exynos5_map_io(void)
393{
394 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
94c7ca71
KK		 395}
396
2edb36c4
KK		 397static void __init exynos5440_map_io(void)
398{
399 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
400}
401
6923ae4b
TA		 402void __init exynos_init_time(void)
403{
404 if (of_have_populated_dt()) {
405#ifdef CONFIG_OF
406 of_clk_init(NULL);
407 clocksource_of_init();
408#endif
409 } else {
410 /* todo: remove after migrating legacy E4 platforms to dt */
411 exynos4_clk_init(NULL);
92744274 412 exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
6923ae4b
TA		 413 mct_init();
414 }
415}
416
cc511b8d
KK		 417void __init exynos4_init_irq(void)
418{
40ba95fd 419 unsigned int gic_bank_offset;
cc511b8d
KK		 420
421 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
422
237c78be 423 if (!of_have_populated_dt())
75294957 424 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
237c78be
AB		 425#ifdef CONFIG_OF
426 else
0529e315 427 irqchip_init();
237c78be 428#endif
cc511b8d 429
e873a47c
TA		 430 if (!of_have_populated_dt())
431 combiner_init(S5P_VA_COMBINER_BASE, NULL);
cc511b8d
KK		 432
433 /*
434 * The parameters of s5p_init_irq() are for VIC init.
435 * Theses parameters should be NULL and 0 because EXYNOS4
436 * uses GIC instead of VIC.
437 */
438 s5p_init_irq(NULL, 0);
439}
440
94c7ca71
KK		 441void __init exynos5_init_irq(void)
442{
6fff5a11 443#ifdef CONFIG_OF
0529e315 444 irqchip_init();
6fff5a11 445#endif
cc511b8d
KK		 446 /*
447 * The parameters of s5p_init_irq() are for VIC init.
448 * Theses parameters should be NULL and 0 because EXYNOS4
449 * uses GIC instead of VIC.
450 */
12fee194
KK		 451 if (!of_machine_is_compatible("samsung,exynos5440"))
452 s5p_init_irq(NULL, 0);
3445513c
IS		 453
454 gic_arch_extn.irq_set_wake = s3c_irq_wake;
cc511b8d
KK		 455}
456
9ee6af9c
TA		 457struct bus_type exynos_subsys = {
458 .name = "exynos-core",
459 .dev_name = "exynos-core",
94c7ca71
KK		 460};
461
7affca35 462static struct device exynos4_dev = {
9ee6af9c 463 .bus = &exynos_subsys,
94c7ca71
KK		 464};
465
466static int __init exynos_core_init(void)
cc511b8d 467{
9ee6af9c 468 return subsys_system_register(&exynos_subsys, NULL);
cc511b8d 469}
94c7ca71 470core_initcall(exynos_core_init);
cc511b8d
KK		 471
472#ifdef CONFIG_CACHE_L2X0
473static int __init exynos4_l2x0_cache_init(void)
474{
e1b1994e
IH		 475 int ret;
476
2edb36c4 477 if (soc_is_exynos5250() || soc_is_exynos5440())
94c7ca71
KK		 478 return 0;
479
6cdeddcc
ADK		 480 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
481 if (!ret) {
482 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
483 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
484 return 0;
485 }
cc511b8d 486
b756a50f
ADK		 487 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
488 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
489 /* TAG, Data Latency Control: 2 cycles */
490 l2x0_saved_regs.tag_latency = 0x110;
cc511b8d 491
b756a50f
ADK		 492 if (soc_is_exynos4212() || soc_is_exynos4412())
493 l2x0_saved_regs.data_latency = 0x120;
494 else
495 l2x0_saved_regs.data_latency = 0x110;
496
497 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
498 l2x0_saved_regs.pwr_ctrl =
499 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
cc511b8d 500
b756a50f 501 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
cc511b8d 502
b756a50f
ADK		 503 __raw_writel(l2x0_saved_regs.tag_latency,
504 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
505 __raw_writel(l2x0_saved_regs.data_latency,
506 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
cc511b8d 507
b756a50f
ADK		 508 /* L2X0 Prefetch Control */
509 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
510 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
511
512 /* L2X0 Power Control */
513 __raw_writel(l2x0_saved_regs.pwr_ctrl,
514 S5P_VA_L2CC + L2X0_POWER_CTRL);
515
516 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
517 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
518 }
cc511b8d 519
6cdeddcc 520 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
cc511b8d
KK		 521 return 0;
522}
cc511b8d
KK		 523early_initcall(exynos4_l2x0_cache_init);
524#endif
525
906c789c 526static int __init exynos_init(void)
cc511b8d
KK		 527{
528 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
94c7ca71 529
9ee6af9c 530 return device_register(&exynos4_dev);
cc511b8d
KK		 531}
532
cc511b8d
KK		 533/* uart registration process */
534
55b6ef7a 535static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
cc511b8d
KK		 536{
537 struct s3c2410_uartcfg *tcfg = cfg;
538 u32 ucnt;
539
237c78be
AB		 540 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
541 tcfg->has_fracval = 1;
cc511b8d 542
55b6ef7a 543 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
cc511b8d
KK		 544}
545
330c90a5
EK		 546static void __iomem *exynos_eint_base;
547
cc511b8d
KK		 548static DEFINE_SPINLOCK(eint_lock);
549
550static unsigned int eint0_15_data[16];
551
330c90a5 552static inline int exynos4_irq_to_gpio(unsigned int irq)
cc511b8d 553{
330c90a5
EK		 554 if (irq < IRQ_EINT(0))
555 return -EINVAL;
cc511b8d 556
330c90a5
EK		 557 irq -= IRQ_EINT(0);
558 if (irq < 8)
559 return EXYNOS4_GPX0(irq);
560
561 irq -= 8;
562 if (irq < 8)
563 return EXYNOS4_GPX1(irq);
564
565 irq -= 8;
566 if (irq < 8)
567 return EXYNOS4_GPX2(irq);
568
569 irq -= 8;
570 if (irq < 8)
571 return EXYNOS4_GPX3(irq);
572
573 return -EINVAL;
574}
575
576static inline int exynos5_irq_to_gpio(unsigned int irq)
577{
578 if (irq < IRQ_EINT(0))
579 return -EINVAL;
580
581 irq -= IRQ_EINT(0);
582 if (irq < 8)
583 return EXYNOS5_GPX0(irq);
584
585 irq -= 8;
586 if (irq < 8)
587 return EXYNOS5_GPX1(irq);
588
589 irq -= 8;
590 if (irq < 8)
591 return EXYNOS5_GPX2(irq);
cc511b8d 592
330c90a5
EK		 593 irq -= 8;
594 if (irq < 8)
595 return EXYNOS5_GPX3(irq);
596
597 return -EINVAL;
cc511b8d
KK		 598}
599
bb19a751
KK		 600static unsigned int exynos4_eint0_15_src_int[16] = {
601 EXYNOS4_IRQ_EINT0,
602 EXYNOS4_IRQ_EINT1,
603 EXYNOS4_IRQ_EINT2,
604 EXYNOS4_IRQ_EINT3,
605 EXYNOS4_IRQ_EINT4,
606 EXYNOS4_IRQ_EINT5,
607 EXYNOS4_IRQ_EINT6,
608 EXYNOS4_IRQ_EINT7,
609 EXYNOS4_IRQ_EINT8,
610 EXYNOS4_IRQ_EINT9,
611 EXYNOS4_IRQ_EINT10,
612 EXYNOS4_IRQ_EINT11,
613 EXYNOS4_IRQ_EINT12,
614 EXYNOS4_IRQ_EINT13,
615 EXYNOS4_IRQ_EINT14,
616 EXYNOS4_IRQ_EINT15,
617};
cc511b8d 618
bb19a751
KK		 619static unsigned int exynos5_eint0_15_src_int[16] = {
620 EXYNOS5_IRQ_EINT0,
621 EXYNOS5_IRQ_EINT1,
622 EXYNOS5_IRQ_EINT2,
623 EXYNOS5_IRQ_EINT3,
624 EXYNOS5_IRQ_EINT4,
625 EXYNOS5_IRQ_EINT5,
626 EXYNOS5_IRQ_EINT6,
627 EXYNOS5_IRQ_EINT7,
628 EXYNOS5_IRQ_EINT8,
629 EXYNOS5_IRQ_EINT9,
630 EXYNOS5_IRQ_EINT10,
631 EXYNOS5_IRQ_EINT11,
632 EXYNOS5_IRQ_EINT12,
633 EXYNOS5_IRQ_EINT13,
634 EXYNOS5_IRQ_EINT14,
635 EXYNOS5_IRQ_EINT15,
636};
330c90a5 637static inline void exynos_irq_eint_mask(struct irq_data *data)
cc511b8d
KK		 638{
639 u32 mask;
640
641 spin_lock(&eint_lock);
330c90a5
EK		 642 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
643 mask |= EINT_OFFSET_BIT(data->irq);
644 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
cc511b8d
KK		 645 spin_unlock(&eint_lock);
646}
647
330c90a5 648static void exynos_irq_eint_unmask(struct irq_data *data)
cc511b8d
KK		 649{
650 u32 mask;
651
652 spin_lock(&eint_lock);
330c90a5
EK		 653 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
654 mask &= ~(EINT_OFFSET_BIT(data->irq));
655 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
cc511b8d
KK		 656 spin_unlock(&eint_lock);
657}
658
330c90a5 659static inline void exynos_irq_eint_ack(struct irq_data *data)
cc511b8d 660{
330c90a5
EK		 661 __raw_writel(EINT_OFFSET_BIT(data->irq),
662 EINT_PEND(exynos_eint_base, data->irq));
cc511b8d
KK		 663}
664
330c90a5 665static void exynos_irq_eint_maskack(struct irq_data *data)
cc511b8d 666{
330c90a5
EK		 667 exynos_irq_eint_mask(data);
668 exynos_irq_eint_ack(data);
cc511b8d
KK		 669}
670
330c90a5 671static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
cc511b8d
KK		 672{
673 int offs = EINT_OFFSET(data->irq);
674 int shift;
675 u32 ctrl, mask;
676 u32 newvalue = 0;
677
678 switch (type) {
679 case IRQ_TYPE_EDGE_RISING:
680 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
681 break;
682
683 case IRQ_TYPE_EDGE_FALLING:
684 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
685 break;
686
687 case IRQ_TYPE_EDGE_BOTH:
688 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
689 break;
690
691 case IRQ_TYPE_LEVEL_LOW:
692 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
693 break;
694
695 case IRQ_TYPE_LEVEL_HIGH:
696 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
697 break;
698
699 default:
700 printk(KERN_ERR "No such irq type %d", type);
701 return -EINVAL;
702 }
703
704 shift = (offs & 0x7) * 4;
705 mask = 0x7 << shift;
706
707 spin_lock(&eint_lock);
330c90a5 708 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
cc511b8d
KK		 709 ctrl &= ~mask;
710 ctrl |= newvalue << shift;
330c90a5 711 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
cc511b8d
KK		 712 spin_unlock(&eint_lock);
713
330c90a5
EK		 714 if (soc_is_exynos5250())
715 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
716 else
717 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
cc511b8d
KK		 718
719 return 0;
720}
721
330c90a5
EK		 722static struct irq_chip exynos_irq_eint = {
723 .name = "exynos-eint",
724 .irq_mask = exynos_irq_eint_mask,
725 .irq_unmask = exynos_irq_eint_unmask,
726 .irq_mask_ack = exynos_irq_eint_maskack,
727 .irq_ack = exynos_irq_eint_ack,
728 .irq_set_type = exynos_irq_eint_set_type,
cc511b8d
KK		 729#ifdef CONFIG_PM
730 .irq_set_wake = s3c_irqext_wake,
731#endif
732};
733
734/*
735 * exynos4_irq_demux_eint
736 *
737 * This function demuxes the IRQ from from EINTs 16 to 31.
738 * It is designed to be inlined into the specific handler
739 * s5p_irq_demux_eintX_Y.
740 *
741 * Each EINT pend/mask registers handle eight of them.
742 */
330c90a5 743static inline void exynos_irq_demux_eint(unsigned int start)
cc511b8d
KK		 744{
745 unsigned int irq;
746
330c90a5
EK		 747 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
748 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
cc511b8d
KK		 749
750 status &= ~mask;
751 status &= 0xff;
752
753 while (status) {
754 irq = fls(status) - 1;
755 generic_handle_irq(irq + start);
756 status &= ~(1 << irq);
757 }
758}
759
330c90a5 760static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
cc511b8d
KK		 761{
762 struct irq_chip *chip = irq_get_chip(irq);
763 chained_irq_enter(chip, desc);
330c90a5
EK		 764 exynos_irq_demux_eint(IRQ_EINT(16));
765 exynos_irq_demux_eint(IRQ_EINT(24));
cc511b8d
KK		 766 chained_irq_exit(chip, desc);
767}
768
bb19a751 769static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
cc511b8d
KK		 770{
771 u32 *irq_data = irq_get_handler_data(irq);
772 struct irq_chip *chip = irq_get_chip(irq);
773
774 chained_irq_enter(chip, desc);
cc511b8d 775 generic_handle_irq(*irq_data);
cc511b8d
KK		 776 chained_irq_exit(chip, desc);
777}
778
330c90a5 779static int __init exynos_init_irq_eint(void)
cc511b8d
KK		 780{
781 int irq;
782
fef05c29
TA		 783#ifdef CONFIG_PINCTRL_SAMSUNG
784 /*
785 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
786 * functionality along with support for external gpio and wakeup
787 * interrupts. If the samsung pinctrl driver is enabled and includes
788 * the wakeup interrupt support, then the setting up external wakeup
789 * interrupts here can be skipped. This check here is temporary to
790 * allow exynos4 platforms that do not use Samsung pinctrl driver to
791 * co-exist with platforms that do. When all of the Samsung Exynos4
792 * platforms switch over to using the pinctrl driver, the wakeup
793 * interrupt support code here can be completely removed.
794 */
ab7b51ff 795 static const struct of_device_id exynos_pinctrl_ids[] = {
b533c868
KK		 796 { .compatible = "samsung,exynos4210-pinctrl", },
797 { .compatible = "samsung,exynos4x12-pinctrl", },
ab7b51ff 798 };
fef05c29 799 struct device_node *pctrl_np, *wkup_np;
fef05c29
TA		 800 const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
801
ab7b51ff 802 for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
fef05c29
TA		 803 if (of_device_is_available(pctrl_np)) {
804 wkup_np = of_find_compatible_node(pctrl_np, NULL,
805 wkup_compat);
806 if (wkup_np)
807 return -ENODEV;
808 }
809 }
810#endif
2edb36c4
KK		 811 if (soc_is_exynos5440())
812 return 0;
fef05c29 813
94c7ca71 814 if (soc_is_exynos5250())
330c90a5
EK		 815 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
816 else
817 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
818
819 if (exynos_eint_base == NULL) {
820 pr_err("unable to ioremap for EINT base address\n");
821 return -ENOMEM;
822 }
94c7ca71 823
cc511b8d 824 for (irq = 0 ; irq <= 31 ; irq++) {
330c90a5 825 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
cc511b8d
KK		 826 handle_level_irq);
827 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
828 }
829
330c90a5 830 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
cc511b8d
KK		 831
832 for (irq = 0 ; irq <= 15 ; irq++) {
833 eint0_15_data[irq] = IRQ_EINT(irq);
834
bb19a751
KK		 835 if (soc_is_exynos5250()) {
836 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
837 &eint0_15_data[irq]);
838 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
839 exynos_irq_eint0_15);
840 } else {
841 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
842 &eint0_15_data[irq]);
843 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
844 exynos_irq_eint0_15);
845 }
cc511b8d
KK		 846 }
847
848 return 0;
849}
330c90a5 850arch_initcall(exynos_init_irq_eint);
kernel source for telekom puls (alcatel/mediatek)