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Merge tag 'at91-cleanup' of git://github.com/at91linux/linux-at91 into next/cleanup
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-exynos / common.c
CommitLineData
cc511b8d
KK		 1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
7affca35 16#include <linux/device.h>
cc511b8d
KK		 17#include <linux/gpio.h>
18#include <linux/sched.h>
19#include <linux/serial_core.h>
237c78be 20#include <linux/of.h>
5b7897db 21#include <linux/of_fdt.h>
237c78be 22#include <linux/of_irq.h>
1e60bc0b
TA		 23#include <linux/export.h>
24#include <linux/irqdomain.h>
0529e315 25#include <linux/irqchip.h>
e873a47c 26#include <linux/of_address.h>
520f7bd7 27#include <linux/irqchip/arm-gic.h>
cc511b8d
KK		 28
29#include <asm/proc-fns.h>
40ba95fd 30#include <asm/exception.h>
cc511b8d 31#include <asm/hardware/cache-l2x0.h>
cc511b8d
KK		 32#include <asm/mach/map.h>
33#include <asm/mach/irq.h>
b756a50f 34#include <asm/cacheflush.h>
cc511b8d
KK		 35
36#include <mach/regs-irq.h>
37#include <mach/regs-pmu.h>
38#include <mach/regs-gpio.h>
39
40#include <plat/cpu.h>
41#include <plat/clock.h>
42#include <plat/devs.h>
43#include <plat/pm.h>
cc511b8d
KK		 44#include <plat/sdhci.h>
45#include <plat/gpio-cfg.h>
46#include <plat/adc-core.h>
47#include <plat/fb-core.h>
48#include <plat/fimc-core.h>
49#include <plat/iic-core.h>
50#include <plat/tv-core.h>
308b3afb 51#include <plat/spi-core.h>
cc511b8d
KK		 52#include <plat/regs-serial.h>
53
54#include "common.h"
6cdeddcc
ADK		 55#define L2_AUX_VAL 0x7C470001
56#define L2_AUX_MASK 0xC200ffff
cc511b8d 57
cc511b8d
KK		 58static const char name_exynos4210[] = "EXYNOS4210";
59static const char name_exynos4212[] = "EXYNOS4212";
60static const char name_exynos4412[] = "EXYNOS4412";
94c7ca71 61static const char name_exynos5250[] = "EXYNOS5250";
2edb36c4 62static const char name_exynos5440[] = "EXYNOS5440";
cc511b8d 63
906c789c 64static void exynos4_map_io(void);
94c7ca71 65static void exynos5_map_io(void);
2edb36c4 66static void exynos5440_map_io(void);
906c789c 67static void exynos4_init_clocks(int xtal);
94c7ca71 68static void exynos5_init_clocks(int xtal);
55b6ef7a 69static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
906c789c 70static int exynos_init(void);
cc511b8d
KK		 71
72static struct cpu_table cpu_ids[] __initdata = {
73 {
74 .idcode = EXYNOS4210_CPU_ID,
75 .idmask = EXYNOS4_CPU_MASK,
76 .map_io = exynos4_map_io,
77 .init_clocks = exynos4_init_clocks,
55b6ef7a 78 .init_uarts = exynos4_init_uarts,
cc511b8d
KK		 79 .init = exynos_init,
80 .name = name_exynos4210,
81 }, {
82 .idcode = EXYNOS4212_CPU_ID,
83 .idmask = EXYNOS4_CPU_MASK,
84 .map_io = exynos4_map_io,
85 .init_clocks = exynos4_init_clocks,
55b6ef7a 86 .init_uarts = exynos4_init_uarts,
cc511b8d
KK		 87 .init = exynos_init,
88 .name = name_exynos4212,
89 }, {
90 .idcode = EXYNOS4412_CPU_ID,
91 .idmask = EXYNOS4_CPU_MASK,
92 .map_io = exynos4_map_io,
93 .init_clocks = exynos4_init_clocks,
55b6ef7a 94 .init_uarts = exynos4_init_uarts,
cc511b8d
KK		 95 .init = exynos_init,
96 .name = name_exynos4412,
94c7ca71
KK		 97 }, {
98 .idcode = EXYNOS5250_SOC_ID,
99 .idmask = EXYNOS5_SOC_MASK,
100 .map_io = exynos5_map_io,
101 .init_clocks = exynos5_init_clocks,
94c7ca71
KK		 102 .init = exynos_init,
103 .name = name_exynos5250,
2edb36c4
KK		 104 }, {
105 .idcode = EXYNOS5440_SOC_ID,
106 .idmask = EXYNOS5_SOC_MASK,
107 .map_io = exynos5440_map_io,
108 .init = exynos_init,
109 .name = name_exynos5440,
cc511b8d
KK		 110 },
111};
112
113/* Initial IO mappings */
114
115static struct map_desc exynos_iodesc[] __initdata = {
116 {
117 .virtual = (unsigned long)S5P_VA_CHIPID,
94c7ca71 118 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
cc511b8d
KK		 119 .length = SZ_4K,
120 .type = MT_DEVICE,
94c7ca71
KK		 121 },
122};
123
5b7897db 124#ifdef CONFIG_ARCH_EXYNOS5
2edb36c4
KK		 125static struct map_desc exynos5440_iodesc[] __initdata = {
126 {
127 .virtual = (unsigned long)S5P_VA_CHIPID,
128 .pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
129 .length = SZ_4K,
130 .type = MT_DEVICE,
131 },
132};
5b7897db 133#endif
2edb36c4 134
94c7ca71
KK		 135static struct map_desc exynos4_iodesc[] __initdata = {
136 {
cc511b8d
KK		 137 .virtual = (unsigned long)S3C_VA_SYS,
138 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
139 .length = SZ_64K,
140 .type = MT_DEVICE,
141 }, {
142 .virtual = (unsigned long)S3C_VA_TIMER,
143 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
144 .length = SZ_16K,
145 .type = MT_DEVICE,
146 }, {
147 .virtual = (unsigned long)S3C_VA_WATCHDOG,
148 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
149 .length = SZ_4K,
150 .type = MT_DEVICE,
151 }, {
152 .virtual = (unsigned long)S5P_VA_SROMC,
153 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
154 .length = SZ_4K,
155 .type = MT_DEVICE,
156 }, {
157 .virtual = (unsigned long)S5P_VA_SYSTIMER,
158 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
159 .length = SZ_4K,
160 .type = MT_DEVICE,
161 }, {
162 .virtual = (unsigned long)S5P_VA_PMU,
163 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
164 .length = SZ_64K,
165 .type = MT_DEVICE,
166 }, {
167 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
168 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
169 .length = SZ_4K,
170 .type = MT_DEVICE,
171 }, {
172 .virtual = (unsigned long)S5P_VA_GIC_CPU,
173 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
174 .length = SZ_64K,
175 .type = MT_DEVICE,
176 }, {
177 .virtual = (unsigned long)S5P_VA_GIC_DIST,
178 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
179 .length = SZ_64K,
180 .type = MT_DEVICE,
181 }, {
182 .virtual = (unsigned long)S3C_VA_UART,
183 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
184 .length = SZ_512K,
185 .type = MT_DEVICE,
94c7ca71 186 }, {
cc511b8d
KK		 187 .virtual = (unsigned long)S5P_VA_CMU,
188 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
189 .length = SZ_128K,
190 .type = MT_DEVICE,
191 }, {
192 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
193 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
194 .length = SZ_8K,
195 .type = MT_DEVICE,
196 }, {
197 .virtual = (unsigned long)S5P_VA_L2CC,
198 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
199 .length = SZ_4K,
200 .type = MT_DEVICE,
cc511b8d
KK		 201 }, {
202 .virtual = (unsigned long)S5P_VA_DMC0,
203 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
2bde0b08
MH		 204 .length = SZ_64K,
205 .type = MT_DEVICE,
206 }, {
207 .virtual = (unsigned long)S5P_VA_DMC1,
208 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
209 .length = SZ_64K,
cc511b8d 210 .type = MT_DEVICE,
cc511b8d
KK		 211 }, {
212 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
213 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
214 .length = SZ_4K,
215 .type = MT_DEVICE,
216 },
217};
218
219static struct map_desc exynos4_iodesc0[] __initdata = {
220 {
221 .virtual = (unsigned long)S5P_VA_SYSRAM,
222 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
223 .length = SZ_4K,
224 .type = MT_DEVICE,
225 },
226};
227
228static struct map_desc exynos4_iodesc1[] __initdata = {
229 {
230 .virtual = (unsigned long)S5P_VA_SYSRAM,
231 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
232 .length = SZ_4K,
233 .type = MT_DEVICE,
234 },
235};
236
94c7ca71
KK		 237static struct map_desc exynos5_iodesc[] __initdata = {
238 {
239 .virtual = (unsigned long)S3C_VA_SYS,
240 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
241 .length = SZ_64K,
242 .type = MT_DEVICE,
243 }, {
244 .virtual = (unsigned long)S3C_VA_TIMER,
245 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
246 .length = SZ_16K,
247 .type = MT_DEVICE,
248 }, {
249 .virtual = (unsigned long)S3C_VA_WATCHDOG,
250 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
251 .length = SZ_4K,
252 .type = MT_DEVICE,
253 }, {
254 .virtual = (unsigned long)S5P_VA_SROMC,
255 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
256 .length = SZ_4K,
257 .type = MT_DEVICE,
258 }, {
259 .virtual = (unsigned long)S5P_VA_SYSTIMER,
260 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
261 .length = SZ_4K,
262 .type = MT_DEVICE,
263 }, {
264 .virtual = (unsigned long)S5P_VA_SYSRAM,
265 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
266 .length = SZ_4K,
267 .type = MT_DEVICE,
268 }, {
269 .virtual = (unsigned long)S5P_VA_CMU,
270 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
271 .length = 144 * SZ_1K,
272 .type = MT_DEVICE,
273 }, {
274 .virtual = (unsigned long)S5P_VA_PMU,
275 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
276 .length = SZ_64K,
277 .type = MT_DEVICE,
94c7ca71
KK		 278 }, {
279 .virtual = (unsigned long)S3C_VA_UART,
280 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
281 .length = SZ_512K,
282 .type = MT_DEVICE,
94c7ca71
KK		 283 },
284};
285
2edb36c4
KK		 286static struct map_desc exynos5440_iodesc0[] __initdata = {
287 {
288 .virtual = (unsigned long)S3C_VA_UART,
289 .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
290 .length = SZ_512K,
291 .type = MT_DEVICE,
292 },
293};
294
9eb48595 295void exynos4_restart(char mode, const char *cmd)
cc511b8d
KK		 296{
297 __raw_writel(0x1, S5P_SWRESET);
298}
299
94c7ca71
KK		 300void exynos5_restart(char mode, const char *cmd)
301{
2edb36c4
KK		 302 u32 val;
303 void __iomem *addr;
304
305 if (of_machine_is_compatible("samsung,exynos5250")) {
306 val = 0x1;
307 addr = EXYNOS_SWRESET;
308 } else if (of_machine_is_compatible("samsung,exynos5440")) {
309 val = (0x10 << 20) | (0x1 << 16);
310 addr = EXYNOS5440_SWRESET;
311 } else {
312 pr_err("%s: cannot support non-DT\n", __func__);
313 return;
314 }
315
316 __raw_writel(val, addr);
94c7ca71
KK		 317}
318
bb13fabc
SG		 319void __init exynos_init_late(void)
320{
2edb36c4
KK		 321 if (of_machine_is_compatible("samsung,exynos5440"))
322 /* to be supported later */
323 return;
324
bb13fabc
SG		 325 exynos_pm_late_initcall();
326}
327
cc511b8d
KK		 328/*
329 * exynos_map_io
330 *
331 * register the standard cpu IO areas
332 */
333
334void __init exynos_init_io(struct map_desc *mach_desc, int size)
335{
5b7897db
DA		 336 struct map_desc *iodesc = exynos_iodesc;
337 int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
338#if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
339 unsigned long root = of_get_flat_dt_root();
340
cc511b8d 341 /* initialize the io descriptors we need for initialization */
5b7897db
DA		 342 if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
343 iodesc = exynos5440_iodesc;
344 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
345 }
346#endif
347
348 iotable_init(iodesc, iodesc_sz);
2edb36c4 349
cc511b8d
KK		 350 if (mach_desc)
351 iotable_init(mach_desc, size);
352
353 /* detect cpu id and rev. */
354 s5p_init_cpu(S5P_VA_CHIPID);
355
356 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
357}
358
906c789c 359static void __init exynos4_map_io(void)
cc511b8d
KK		 360{
361 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
362
363 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
364 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
365 else
366 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
367
368 /* initialize device information early */
369 exynos4_default_sdhci0();
370 exynos4_default_sdhci1();
371 exynos4_default_sdhci2();
372 exynos4_default_sdhci3();
373
374 s3c_adc_setname("samsung-adc-v3");
375
376 s3c_fimc_setname(0, "exynos4-fimc");
377 s3c_fimc_setname(1, "exynos4-fimc");
378 s3c_fimc_setname(2, "exynos4-fimc");
379 s3c_fimc_setname(3, "exynos4-fimc");
380
8482c81c
TA		 381 s3c_sdhci_setname(0, "exynos4-sdhci");
382 s3c_sdhci_setname(1, "exynos4-sdhci");
383 s3c_sdhci_setname(2, "exynos4-sdhci");
384 s3c_sdhci_setname(3, "exynos4-sdhci");
385
cc511b8d
KK		 386 /* The I2C bus controllers are directly compatible with s3c2440 */
387 s3c_i2c0_setname("s3c2440-i2c");
388 s3c_i2c1_setname("s3c2440-i2c");
389 s3c_i2c2_setname("s3c2440-i2c");
390
391 s5p_fb_setname(0, "exynos4-fb");
392 s5p_hdmi_setname("exynos4-hdmi");
308b3afb
HS		 393
394 s3c64xx_spi_setname("exynos4210-spi");
cc511b8d
KK		 395}
396
94c7ca71
KK		 397static void __init exynos5_map_io(void)
398{
399 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
94c7ca71
KK		 400}
401
906c789c 402static void __init exynos4_init_clocks(int xtal)
cc511b8d
KK		 403{
404 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
405
406 s3c24xx_register_baseclocks(xtal);
407 s5p_register_clocks(xtal);
408
409 if (soc_is_exynos4210())
410 exynos4210_register_clocks();
411 else if (soc_is_exynos4212() || soc_is_exynos4412())
412 exynos4212_register_clocks();
413
414 exynos4_register_clocks();
415 exynos4_setup_clocks();
416}
417
2edb36c4
KK		 418static void __init exynos5440_map_io(void)
419{
420 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
421}
422
94c7ca71
KK		 423static void __init exynos5_init_clocks(int xtal)
424{
425 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
426
61bcbc2a
KK		 427 /* EXYNOS5440 can support only common clock framework */
428
429 if (soc_is_exynos5440())
430 return;
431
432#ifdef CONFIG_SOC_EXYNOS5250
94c7ca71
KK		 433 s3c24xx_register_baseclocks(xtal);
434 s5p_register_clocks(xtal);
435
436 exynos5_register_clocks();
437 exynos5_setup_clocks();
61bcbc2a 438#endif
94c7ca71
KK		 439}
440
cc511b8d
KK		 441#define COMBINER_ENABLE_SET 0x0
442#define COMBINER_ENABLE_CLEAR 0x4
443#define COMBINER_INT_STATUS 0xC
444
445static DEFINE_SPINLOCK(irq_controller_lock);
446
447struct combiner_chip_data {
448 unsigned int irq_offset;
449 unsigned int irq_mask;
450 void __iomem *base;
451};
452
1e60bc0b 453static struct irq_domain *combiner_irq_domain;
cc511b8d
KK		 454static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
455
456static inline void __iomem *combiner_base(struct irq_data *data)
457{
458 struct combiner_chip_data *combiner_data =
459 irq_data_get_irq_chip_data(data);
460
461 return combiner_data->base;
462}
463
464static void combiner_mask_irq(struct irq_data *data)
465{
1e60bc0b 466 u32 mask = 1 << (data->hwirq % 32);
cc511b8d
KK		 467
468 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
469}
470
471static void combiner_unmask_irq(struct irq_data *data)
472{
1e60bc0b 473 u32 mask = 1 << (data->hwirq % 32);
cc511b8d
KK		 474
475 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
476}
477
478static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
479{
480 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
481 struct irq_chip *chip = irq_get_chip(irq);
482 unsigned int cascade_irq, combiner_irq;
483 unsigned long status;
484
485 chained_irq_enter(chip, desc);
486
487 spin_lock(&irq_controller_lock);
488 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
489 spin_unlock(&irq_controller_lock);
490 status &= chip_data->irq_mask;
491
492 if (status == 0)
493 goto out;
494
495 combiner_irq = __ffs(status);
496
497 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
498 if (unlikely(cascade_irq >= NR_IRQS))
499 do_bad_IRQ(cascade_irq, desc);
500 else
501 generic_handle_irq(cascade_irq);
502
503 out:
504 chained_irq_exit(chip, desc);
505}
506
507static struct irq_chip combiner_chip = {
508 .name = "COMBINER",
509 .irq_mask = combiner_mask_irq,
510 .irq_unmask = combiner_unmask_irq,
511};
512
513static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
514{
bb19a751
KK		 515 unsigned int max_nr;
516
517 if (soc_is_exynos5250())
518 max_nr = EXYNOS5_MAX_COMBINER_NR;
519 else
520 max_nr = EXYNOS4_MAX_COMBINER_NR;
521
522 if (combiner_nr >= max_nr)
cc511b8d
KK		 523 BUG();
524 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
525 BUG();
526 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
527}
528
1e60bc0b
TA		 529static void __init combiner_init_one(unsigned int combiner_nr,
530 void __iomem *base)
cc511b8d 531{
cc511b8d 532 combiner_data[combiner_nr].base = base;
1e60bc0b
TA		 533 combiner_data[combiner_nr].irq_offset = irq_find_mapping(
534 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
cc511b8d
KK		 535 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
536
537 /* Disable all interrupts */
cc511b8d
KK		 538 __raw_writel(combiner_data[combiner_nr].irq_mask,
539 base + COMBINER_ENABLE_CLEAR);
1e60bc0b 540}
cc511b8d 541
e873a47c
TA		 542#ifdef CONFIG_OF
543static int combiner_irq_domain_xlate(struct irq_domain *d,
544 struct device_node *controller,
545 const u32 *intspec, unsigned int intsize,
546 unsigned long *out_hwirq,
547 unsigned int *out_type)
548{
549 if (d->of_node != controller)
550 return -EINVAL;
551
552 if (intsize < 2)
553 return -EINVAL;
554
555 *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
556 *out_type = 0;
557
558 return 0;
559}
560#else
561static int combiner_irq_domain_xlate(struct irq_domain *d,
562 struct device_node *controller,
563 const u32 *intspec, unsigned int intsize,
564 unsigned long *out_hwirq,
565 unsigned int *out_type)
566{
567 return -EINVAL;
568}
569#endif
570
1e60bc0b
TA		 571static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
572 irq_hw_number_t hw)
573{
574 irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
575 irq_set_chip_data(irq, &combiner_data[hw >> 3]);
576 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
577
578 return 0;
579}
cc511b8d 580
1e60bc0b 581static struct irq_domain_ops combiner_irq_domain_ops = {
e873a47c 582 .xlate = combiner_irq_domain_xlate,
1e60bc0b
TA		 583 .map = combiner_irq_domain_map,
584};
585
2a2b0e20
SK		 586static void __init combiner_init(void __iomem *combiner_base,
587 struct device_node *np)
1e60bc0b 588{
e873a47c 589 int i, irq, irq_base;
1e60bc0b
TA		 590 unsigned int max_nr, nr_irq;
591
e873a47c
TA		 592 if (np) {
593 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
594 pr_warning("%s: number of combiners not specified, "
595 "setting default as %d.\n",
596 __func__, EXYNOS4_MAX_COMBINER_NR);
597 max_nr = EXYNOS4_MAX_COMBINER_NR;
598 }
599 } else {
600 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
601 EXYNOS4_MAX_COMBINER_NR;
602 }
1e60bc0b
TA		 603 nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
604
605 irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
606 if (IS_ERR_VALUE(irq_base)) {
607 irq_base = COMBINER_IRQ(0, 0);
608 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
609 }
610
611 combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
612 &combiner_irq_domain_ops, &combiner_data);
613 if (WARN_ON(!combiner_irq_domain)) {
614 pr_warning("%s: irq domain init failed\n", __func__);
615 return;
616 }
617
618 for (i = 0; i < max_nr; i++) {
619 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
820f3dd7
AB		 620 irq = IRQ_SPI(i);
621#ifdef CONFIG_OF
622 if (np)
623 irq = irq_of_parse_and_map(np, i);
624#endif
e873a47c 625 combiner_cascade_irq(i, irq);
cc511b8d
KK		 626 }
627}
628
237c78be 629#ifdef CONFIG_OF
96046ea3
SK		 630static int __init combiner_of_init(struct device_node *np,
631 struct device_node *parent)
e873a47c
TA		 632{
633 void __iomem *combiner_base;
634
635 combiner_base = of_iomap(np, 0);
636 if (!combiner_base) {
637 pr_err("%s: failed to map combiner registers\n", __func__);
638 return -ENXIO;
639 }
640
641 combiner_init(combiner_base, np);
642
643 return 0;
644}
645
2edb36c4 646static const struct of_device_id exynos_dt_irq_match[] = {
e873a47c
TA		 647 { .compatible = "samsung,exynos4210-combiner",
648 .data = combiner_of_init, },
237c78be
AB		 649 {},
650};
651#endif
cc511b8d
KK		 652
653void __init exynos4_init_irq(void)
654{
40ba95fd 655 unsigned int gic_bank_offset;
cc511b8d
KK		 656
657 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
658
237c78be 659 if (!of_have_populated_dt())
75294957 660 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
237c78be 661#ifdef CONFIG_OF
0529e315
RH		 662 else {
663 irqchip_init();
2edb36c4 664 of_irq_init(exynos_dt_irq_match);
0529e315 665 }
237c78be 666#endif
cc511b8d 667
e873a47c
TA		 668 if (!of_have_populated_dt())
669 combiner_init(S5P_VA_COMBINER_BASE, NULL);
cc511b8d
KK		 670
671 /*
672 * The parameters of s5p_init_irq() are for VIC init.
673 * Theses parameters should be NULL and 0 because EXYNOS4
674 * uses GIC instead of VIC.
675 */
676 s5p_init_irq(NULL, 0);
677}
678
94c7ca71
KK		 679void __init exynos5_init_irq(void)
680{
6fff5a11 681#ifdef CONFIG_OF
0529e315 682 irqchip_init();
2edb36c4 683 of_irq_init(exynos_dt_irq_match);
6fff5a11 684#endif
cc511b8d
KK		 685 /*
686 * The parameters of s5p_init_irq() are for VIC init.
687 * Theses parameters should be NULL and 0 because EXYNOS4
688 * uses GIC instead of VIC.
689 */
12fee194
KK		 690 if (!of_machine_is_compatible("samsung,exynos5440"))
691 s5p_init_irq(NULL, 0);
3445513c
IS		 692
693 gic_arch_extn.irq_set_wake = s3c_irq_wake;
cc511b8d
KK		 694}
695
9ee6af9c
TA		 696struct bus_type exynos_subsys = {
697 .name = "exynos-core",
698 .dev_name = "exynos-core",
94c7ca71
KK		 699};
700
7affca35 701static struct device exynos4_dev = {
9ee6af9c 702 .bus = &exynos_subsys,
94c7ca71
KK		 703};
704
705static int __init exynos_core_init(void)
cc511b8d 706{
9ee6af9c 707 return subsys_system_register(&exynos_subsys, NULL);
cc511b8d 708}
94c7ca71 709core_initcall(exynos_core_init);
cc511b8d
KK		 710
711#ifdef CONFIG_CACHE_L2X0
712static int __init exynos4_l2x0_cache_init(void)
713{
e1b1994e
IH		 714 int ret;
715
2edb36c4 716 if (soc_is_exynos5250() || soc_is_exynos5440())
94c7ca71
KK		 717 return 0;
718
6cdeddcc
ADK		 719 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
720 if (!ret) {
721 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
722 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
723 return 0;
724 }
cc511b8d 725
b756a50f
ADK		 726 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
727 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
728 /* TAG, Data Latency Control: 2 cycles */
729 l2x0_saved_regs.tag_latency = 0x110;
cc511b8d 730
b756a50f
ADK		 731 if (soc_is_exynos4212() || soc_is_exynos4412())
732 l2x0_saved_regs.data_latency = 0x120;
733 else
734 l2x0_saved_regs.data_latency = 0x110;
735
736 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
737 l2x0_saved_regs.pwr_ctrl =
738 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
cc511b8d 739
b756a50f 740 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
cc511b8d 741
b756a50f
ADK		 742 __raw_writel(l2x0_saved_regs.tag_latency,
743 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
744 __raw_writel(l2x0_saved_regs.data_latency,
745 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
cc511b8d 746
b756a50f
ADK		 747 /* L2X0 Prefetch Control */
748 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
749 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
750
751 /* L2X0 Power Control */
752 __raw_writel(l2x0_saved_regs.pwr_ctrl,
753 S5P_VA_L2CC + L2X0_POWER_CTRL);
754
755 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
756 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
757 }
cc511b8d 758
6cdeddcc 759 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
cc511b8d
KK		 760 return 0;
761}
cc511b8d
KK		 762early_initcall(exynos4_l2x0_cache_init);
763#endif
764
906c789c 765static int __init exynos_init(void)
cc511b8d
KK		 766{
767 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
94c7ca71 768
9ee6af9c 769 return device_register(&exynos4_dev);
cc511b8d
KK		 770}
771
cc511b8d
KK		 772/* uart registration process */
773
55b6ef7a 774static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
cc511b8d
KK		 775{
776 struct s3c2410_uartcfg *tcfg = cfg;
777 u32 ucnt;
778
237c78be
AB		 779 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
780 tcfg->has_fracval = 1;
cc511b8d 781
55b6ef7a 782 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
cc511b8d
KK		 783}
784
330c90a5
EK		 785static void __iomem *exynos_eint_base;
786
cc511b8d
KK		 787static DEFINE_SPINLOCK(eint_lock);
788
789static unsigned int eint0_15_data[16];
790
330c90a5 791static inline int exynos4_irq_to_gpio(unsigned int irq)
cc511b8d 792{
330c90a5
EK		 793 if (irq < IRQ_EINT(0))
794 return -EINVAL;
cc511b8d 795
330c90a5
EK		 796 irq -= IRQ_EINT(0);
797 if (irq < 8)
798 return EXYNOS4_GPX0(irq);
799
800 irq -= 8;
801 if (irq < 8)
802 return EXYNOS4_GPX1(irq);
803
804 irq -= 8;
805 if (irq < 8)
806 return EXYNOS4_GPX2(irq);
807
808 irq -= 8;
809 if (irq < 8)
810 return EXYNOS4_GPX3(irq);
811
812 return -EINVAL;
813}
814
815static inline int exynos5_irq_to_gpio(unsigned int irq)
816{
817 if (irq < IRQ_EINT(0))
818 return -EINVAL;
819
820 irq -= IRQ_EINT(0);
821 if (irq < 8)
822 return EXYNOS5_GPX0(irq);
823
824 irq -= 8;
825 if (irq < 8)
826 return EXYNOS5_GPX1(irq);
827
828 irq -= 8;
829 if (irq < 8)
830 return EXYNOS5_GPX2(irq);
cc511b8d 831
330c90a5
EK		 832 irq -= 8;
833 if (irq < 8)
834 return EXYNOS5_GPX3(irq);
835
836 return -EINVAL;
cc511b8d
KK		 837}
838
bb19a751
KK		 839static unsigned int exynos4_eint0_15_src_int[16] = {
840 EXYNOS4_IRQ_EINT0,
841 EXYNOS4_IRQ_EINT1,
842 EXYNOS4_IRQ_EINT2,
843 EXYNOS4_IRQ_EINT3,
844 EXYNOS4_IRQ_EINT4,
845 EXYNOS4_IRQ_EINT5,
846 EXYNOS4_IRQ_EINT6,
847 EXYNOS4_IRQ_EINT7,
848 EXYNOS4_IRQ_EINT8,
849 EXYNOS4_IRQ_EINT9,
850 EXYNOS4_IRQ_EINT10,
851 EXYNOS4_IRQ_EINT11,
852 EXYNOS4_IRQ_EINT12,
853 EXYNOS4_IRQ_EINT13,
854 EXYNOS4_IRQ_EINT14,
855 EXYNOS4_IRQ_EINT15,
856};
cc511b8d 857
bb19a751
KK		 858static unsigned int exynos5_eint0_15_src_int[16] = {
859 EXYNOS5_IRQ_EINT0,
860 EXYNOS5_IRQ_EINT1,
861 EXYNOS5_IRQ_EINT2,
862 EXYNOS5_IRQ_EINT3,
863 EXYNOS5_IRQ_EINT4,
864 EXYNOS5_IRQ_EINT5,
865 EXYNOS5_IRQ_EINT6,
866 EXYNOS5_IRQ_EINT7,
867 EXYNOS5_IRQ_EINT8,
868 EXYNOS5_IRQ_EINT9,
869 EXYNOS5_IRQ_EINT10,
870 EXYNOS5_IRQ_EINT11,
871 EXYNOS5_IRQ_EINT12,
872 EXYNOS5_IRQ_EINT13,
873 EXYNOS5_IRQ_EINT14,
874 EXYNOS5_IRQ_EINT15,
875};
330c90a5 876static inline void exynos_irq_eint_mask(struct irq_data *data)
cc511b8d
KK		 877{
878 u32 mask;
879
880 spin_lock(&eint_lock);
330c90a5
EK		 881 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
882 mask |= EINT_OFFSET_BIT(data->irq);
883 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
cc511b8d
KK		 884 spin_unlock(&eint_lock);
885}
886
330c90a5 887static void exynos_irq_eint_unmask(struct irq_data *data)
cc511b8d
KK		 888{
889 u32 mask;
890
891 spin_lock(&eint_lock);
330c90a5
EK		 892 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
893 mask &= ~(EINT_OFFSET_BIT(data->irq));
894 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
cc511b8d
KK		 895 spin_unlock(&eint_lock);
896}
897
330c90a5 898static inline void exynos_irq_eint_ack(struct irq_data *data)
cc511b8d 899{
330c90a5
EK		 900 __raw_writel(EINT_OFFSET_BIT(data->irq),
901 EINT_PEND(exynos_eint_base, data->irq));
cc511b8d
KK		 902}
903
330c90a5 904static void exynos_irq_eint_maskack(struct irq_data *data)
cc511b8d 905{
330c90a5
EK		 906 exynos_irq_eint_mask(data);
907 exynos_irq_eint_ack(data);
cc511b8d
KK		 908}
909
330c90a5 910static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
cc511b8d
KK		 911{
912 int offs = EINT_OFFSET(data->irq);
913 int shift;
914 u32 ctrl, mask;
915 u32 newvalue = 0;
916
917 switch (type) {
918 case IRQ_TYPE_EDGE_RISING:
919 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
920 break;
921
922 case IRQ_TYPE_EDGE_FALLING:
923 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
924 break;
925
926 case IRQ_TYPE_EDGE_BOTH:
927 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
928 break;
929
930 case IRQ_TYPE_LEVEL_LOW:
931 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
932 break;
933
934 case IRQ_TYPE_LEVEL_HIGH:
935 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
936 break;
937
938 default:
939 printk(KERN_ERR "No such irq type %d", type);
940 return -EINVAL;
941 }
942
943 shift = (offs & 0x7) * 4;
944 mask = 0x7 << shift;
945
946 spin_lock(&eint_lock);
330c90a5 947 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
cc511b8d
KK		 948 ctrl &= ~mask;
949 ctrl |= newvalue << shift;
330c90a5 950 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
cc511b8d
KK		 951 spin_unlock(&eint_lock);
952
330c90a5
EK		 953 if (soc_is_exynos5250())
954 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
955 else
956 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
cc511b8d
KK		 957
958 return 0;
959}
960
330c90a5
EK		 961static struct irq_chip exynos_irq_eint = {
962 .name = "exynos-eint",
963 .irq_mask = exynos_irq_eint_mask,
964 .irq_unmask = exynos_irq_eint_unmask,
965 .irq_mask_ack = exynos_irq_eint_maskack,
966 .irq_ack = exynos_irq_eint_ack,
967 .irq_set_type = exynos_irq_eint_set_type,
cc511b8d
KK		 968#ifdef CONFIG_PM
969 .irq_set_wake = s3c_irqext_wake,
970#endif
971};
972
973/*
974 * exynos4_irq_demux_eint
975 *
976 * This function demuxes the IRQ from from EINTs 16 to 31.
977 * It is designed to be inlined into the specific handler
978 * s5p_irq_demux_eintX_Y.
979 *
980 * Each EINT pend/mask registers handle eight of them.
981 */
330c90a5 982static inline void exynos_irq_demux_eint(unsigned int start)
cc511b8d
KK		 983{
984 unsigned int irq;
985
330c90a5
EK		 986 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
987 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
cc511b8d
KK		 988
989 status &= ~mask;
990 status &= 0xff;
991
992 while (status) {
993 irq = fls(status) - 1;
994 generic_handle_irq(irq + start);
995 status &= ~(1 << irq);
996 }
997}
998
330c90a5 999static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
cc511b8d
KK		 1000{
1001 struct irq_chip *chip = irq_get_chip(irq);
1002 chained_irq_enter(chip, desc);
330c90a5
EK		 1003 exynos_irq_demux_eint(IRQ_EINT(16));
1004 exynos_irq_demux_eint(IRQ_EINT(24));
cc511b8d
KK		 1005 chained_irq_exit(chip, desc);
1006}
1007
bb19a751 1008static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
cc511b8d
KK		 1009{
1010 u32 *irq_data = irq_get_handler_data(irq);
1011 struct irq_chip *chip = irq_get_chip(irq);
1012
1013 chained_irq_enter(chip, desc);
cc511b8d 1014 generic_handle_irq(*irq_data);
cc511b8d
KK		 1015 chained_irq_exit(chip, desc);
1016}
1017
330c90a5 1018static int __init exynos_init_irq_eint(void)
cc511b8d
KK		 1019{
1020 int irq;
1021
fef05c29
TA		 1022#ifdef CONFIG_PINCTRL_SAMSUNG
1023 /*
1024 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
1025 * functionality along with support for external gpio and wakeup
1026 * interrupts. If the samsung pinctrl driver is enabled and includes
1027 * the wakeup interrupt support, then the setting up external wakeup
1028 * interrupts here can be skipped. This check here is temporary to
1029 * allow exynos4 platforms that do not use Samsung pinctrl driver to
1030 * co-exist with platforms that do. When all of the Samsung Exynos4
1031 * platforms switch over to using the pinctrl driver, the wakeup
1032 * interrupt support code here can be completely removed.
1033 */
ab7b51ff
TF		 1034 static const struct of_device_id exynos_pinctrl_ids[] = {
1035 { .compatible = "samsung,pinctrl-exynos4210", },
1036 { .compatible = "samsung,pinctrl-exynos4x12", },
1037 };
fef05c29 1038 struct device_node *pctrl_np, *wkup_np;
fef05c29
TA		 1039 const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
1040
ab7b51ff 1041 for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
fef05c29
TA		 1042 if (of_device_is_available(pctrl_np)) {
1043 wkup_np = of_find_compatible_node(pctrl_np, NULL,
1044 wkup_compat);
1045 if (wkup_np)
1046 return -ENODEV;
1047 }
1048 }
1049#endif
2edb36c4
KK		 1050 if (soc_is_exynos5440())
1051 return 0;
fef05c29 1052
94c7ca71 1053 if (soc_is_exynos5250())
330c90a5
EK		 1054 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
1055 else
1056 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
1057
1058 if (exynos_eint_base == NULL) {
1059 pr_err("unable to ioremap for EINT base address\n");
1060 return -ENOMEM;
1061 }
94c7ca71 1062
cc511b8d 1063 for (irq = 0 ; irq <= 31 ; irq++) {
330c90a5 1064 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
cc511b8d
KK		 1065 handle_level_irq);
1066 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
1067 }
1068
330c90a5 1069 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
cc511b8d
KK		 1070
1071 for (irq = 0 ; irq <= 15 ; irq++) {
1072 eint0_15_data[irq] = IRQ_EINT(irq);
1073
bb19a751
KK		 1074 if (soc_is_exynos5250()) {
1075 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
1076 &eint0_15_data[irq]);
1077 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
1078 exynos_irq_eint0_15);
1079 } else {
1080 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
1081 &eint0_15_data[irq]);
1082 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
1083 exynos_irq_eint0_15);
1084 }
cc511b8d
KK		 1085 }
1086
1087 return 0;
1088}
330c90a5 1089arch_initcall(exynos_init_irq_eint);
kernel source for telekom puls (alcatel/mediatek)