[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-dove / common.c

/*
 * arch/arm/mach-dove/common.c
 *
 * Core functions for Marvell Dove 88AP510 System On Chip
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk-provider.h>
#include <linux/clk/mvebu.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_data/dma-mv_xor.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <linux/platform_device.h>
#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/bridge-regs.h>
#include <mach/pm.h>
#include <plat/common.h>
#include <plat/irq.h>
#include <plat/time.h>
#include "common.h"

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc dove_io_desc[] __initdata = {
	{
		.virtual	= (unsigned long) DOVE_SB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
		.length		= DOVE_SB_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long) DOVE_NB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
		.length		= DOVE_NB_REGS_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init dove_map_io(void)
{
	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
}

/*****************************************************************************
 * CLK tree
 ****************************************************************************/
static int dove_tclk;

static DEFINE_SPINLOCK(gating_lock);
static struct clk *tclk;

static struct clk __init *dove_register_gate(const char *name,
					     const char *parent, u8 bit_idx)
{
	return clk_register_gate(NULL, name, parent, 0,
				 (void __iomem *)CLOCK_GATING_CONTROL,
				 bit_idx, 0, &gating_lock);
}

static void __init dove_clk_init(void)
{
	struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
	struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
	struct clk *xor0, *xor1, *ge, *gephy;

	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
				       dove_tclk);

	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
	pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
	gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);

	orion_clkdev_add(NULL, "orion_spi.0", tclk);
	orion_clkdev_add(NULL, "orion_spi.1", tclk);
	orion_clkdev_add(NULL, "orion_wdt", tclk);
	orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);

	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
	orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
	orion_clkdev_add(NULL, "sata_mv.0", sata);
	orion_clkdev_add("0", "pcie", pex0);
	orion_clkdev_add("1", "pcie", pex1);
	orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
	orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
	orion_clkdev_add(NULL, "orion_nand", nand);
	orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
	orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
	orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
	orion_clkdev_add(NULL, "mv_crypto", crypto);
	orion_clkdev_add(NULL, "dove-ac97", ac97);
	orion_clkdev_add(NULL, "dove-pdma", pdma);
	orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
	orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
}

/*****************************************************************************
 * EHCI0
 ****************************************************************************/
void __init dove_ehci0_init(void)
{
	orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
}

/*****************************************************************************
 * EHCI1
 ****************************************************************************/
void __init dove_ehci1_init(void)
{
	orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
}

/*****************************************************************************
 * GE00
 ****************************************************************************/
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
			IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
			1600);
}

/*****************************************************************************
 * SoC RTC
 ****************************************************************************/
void __init dove_rtc_init(void)
{
	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
}

/*****************************************************************************
 * SATA
 ****************************************************************************/
void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
	orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);

}

/*****************************************************************************
 * UART0
 ****************************************************************************/
void __init dove_uart0_init(void)
{
	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
			 IRQ_DOVE_UART_0, tclk);
}

/*****************************************************************************
 * UART1
 ****************************************************************************/
void __init dove_uart1_init(void)
{
	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
			 IRQ_DOVE_UART_1, tclk);
}

/*****************************************************************************
 * UART2
 ****************************************************************************/
void __init dove_uart2_init(void)
{
	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
			 IRQ_DOVE_UART_2, tclk);
}

/*****************************************************************************
 * UART3
 ****************************************************************************/
void __init dove_uart3_init(void)
{
	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
			 IRQ_DOVE_UART_3, tclk);
}

/*****************************************************************************
 * SPI
 ****************************************************************************/
void __init dove_spi0_init(void)
{
	orion_spi_init(DOVE_SPI0_PHYS_BASE);
}

void __init dove_spi1_init(void)
{
	orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
}

/*****************************************************************************
 * I2C
 ****************************************************************************/
void __init dove_i2c_init(void)
{
	orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
}

/*****************************************************************************
 * Time handling
 ****************************************************************************/
void __init dove_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
}

static int __init dove_find_tclk(void)
{
	return 166666667;
}

void __init dove_timer_init(void)
{
	dove_tclk = dove_find_tclk();
	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
			IRQ_DOVE_BRIDGE, dove_tclk);
}

/*****************************************************************************
 * Cryptographic Engines and Security Accelerator (CESA)
 ****************************************************************************/
void __init dove_crypto_init(void)
{
	orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
			  DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
}

/*****************************************************************************
 * XOR 0
 ****************************************************************************/
void __init dove_xor0_init(void)
{
	orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
			IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
}

/*****************************************************************************
 * XOR 1
 ****************************************************************************/
void __init dove_xor1_init(void)
{
	orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
			IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
}

/*****************************************************************************
 * SDIO
 ****************************************************************************/
static u64 sdio_dmamask = DMA_BIT_MASK(32);

static struct resource dove_sdio0_resources[] = {
	{
		.start	= DOVE_SDIO0_PHYS_BASE,
		.end	= DOVE_SDIO0_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO0,
		.end	= IRQ_DOVE_SDIO0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio0 = {
	.name		= "sdhci-dove",
	.id		= 0,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio0_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio0_resources),
};

void __init dove_sdio0_init(void)
{
	platform_device_register(&dove_sdio0);
}

static struct resource dove_sdio1_resources[] = {
	{
		.start	= DOVE_SDIO1_PHYS_BASE,
		.end	= DOVE_SDIO1_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO1,
		.end	= IRQ_DOVE_SDIO1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio1 = {
	.name		= "sdhci-dove",
	.id		= 1,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio1_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio1_resources),
};

void __init dove_sdio1_init(void)
{
	platform_device_register(&dove_sdio1);
}

void __init dove_init(void)
{
	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
		(dove_tclk + 499999) / 1000000);

#ifdef CONFIG_CACHE_TAUROS2
	tauros2_init(0);
#endif
	dove_setup_cpu_mbus();

	/* Setup root of clk tree */
	dove_clk_init();

	/* internal devices that every board has */
	dove_rtc_init();
	dove_xor0_init();
	dove_xor1_init();
}

void dove_restart(char mode, const char *cmd)
{
	/*
	 * Enable soft reset to assert RSTOUTn.
	 */
	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);

	/*
	 * Assert soft reset.
	 */
	writel(SOFT_RESET, SYSTEM_SOFT_RESET);

	while (1)
		;
}

#if defined(CONFIG_MACH_DOVE_DT)
/*
 * There are still devices that doesn't even know about DT,
 * get clock gates here and add a clock lookup.
 */
static void __init dove_legacy_clk_init(void)
{
	struct device_node *np = of_find_compatible_node(NULL, NULL,
					 "marvell,dove-gating-clock");
	struct of_phandle_args clkspec;

	clkspec.np = np;
	clkspec.args_count = 1;

	clkspec.args[0] = CLOCK_GATING_BIT_USB0;
	orion_clkdev_add(NULL, "orion-ehci.0",
			 of_clk_get_from_provider(&clkspec));

	clkspec.args[0] = CLOCK_GATING_BIT_USB1;
	orion_clkdev_add(NULL, "orion-ehci.1",
			 of_clk_get_from_provider(&clkspec));

	clkspec.args[0] = CLOCK_GATING_BIT_GBE;
	orion_clkdev_add(NULL, "mv643xx_eth_port.0",
			 of_clk_get_from_provider(&clkspec));

	clkspec.args[0] = CLOCK_GATING_BIT_PCIE0;
	orion_clkdev_add("0", "pcie",
			 of_clk_get_from_provider(&clkspec));

	clkspec.args[0] = CLOCK_GATING_BIT_PCIE1;
	orion_clkdev_add("1", "pcie",
			 of_clk_get_from_provider(&clkspec));
}

static void __init dove_of_clk_init(void)
{
	mvebu_clocks_init();
	dove_legacy_clk_init();
}

static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
	.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
};

static void __init dove_dt_init(void)
{
	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
		(dove_tclk + 499999) / 1000000);

#ifdef CONFIG_CACHE_TAUROS2
	tauros2_init(0);
#endif
	dove_setup_cpu_mbus();

	/* Setup root of clk tree */
	dove_of_clk_init();

	/* Internal devices not ported to DT yet */
	dove_rtc_init();

	dove_ge00_init(&dove_dt_ge00_data);
	dove_ehci0_init();
	dove_ehci1_init();
	dove_pcie_init(1, 1);

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

static const char * const dove_dt_board_compat[] = {
	"marvell,dove",
	NULL
};

DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
	.map_io		= dove_map_io,
	.init_early	= dove_init_early,
	.init_irq	= orion_dt_init_irq,
	.init_time	= dove_timer_init,
	.init_machine	= dove_dt_init,
	.restart	= dove_restart,
	.dt_compat	= dove_dt_board_compat,
MACHINE_END
#endif
Commit	Line	Data
edabd38e SB	1	/*
	2	* arch/arm/mach-dove/common.c
	3	*
	4	* Core functions for Marvell Dove 88AP510 System On Chip
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
2f129bf4	11	#include <linux/clk-provider.h>
5b03df9a	12	#include <linux/clk/mvebu.h>
b3af7a1f SH	13	#include <linux/dma-mapping.h>
b3af7a1f SH	14	#include <linux/init.h>
81d2ef7c SH	15	#include <linux/of.h>
81d2ef7c SH	16	#include <linux/of_platform.h>
b3af7a1f SH	17	#include <linux/platform_data/dma-mv_xor.h>
	18	#include <linux/platform_data/usb-ehci-orion.h>
	19	#include <linux/platform_device.h>
573a652f	20	#include <asm/hardware/cache-tauros2.h>
b3af7a1f	21	#include <asm/mach/arch.h>
edabd38e SB	22	#include <asm/mach/map.h>
edabd38e SB	23	#include <asm/mach/time.h>
edabd38e	24	#include <mach/bridge-regs.h>
b3af7a1f	25	#include <mach/pm.h>
28a2b450	26	#include <plat/common.h>
b3af7a1f SH	27	#include <plat/irq.h>
b3af7a1f SH	28	#include <plat/time.h>
edabd38e SB	29	#include "common.h"
	30
	31	/*****************************************************************************
	32	* I/O Address Mapping
	33	****************************************************************************/
	34	static struct map_desc dove_io_desc[] __initdata = {
	35	{
c3c5a281	36	.virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
edabd38e SB	37	.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
	38	.length = DOVE_SB_REGS_SIZE,
	39	.type = MT_DEVICE,
	40	}, {
c3c5a281	41	.virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
edabd38e SB	42	.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
	43	.length = DOVE_NB_REGS_SIZE,
	44	.type = MT_DEVICE,
edabd38e SB	45	},
	46	};
	47
	48	void __init dove_map_io(void)
	49	{
	50	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
	51	}
	52
2f129bf4 AL	53	/*****************************************************************************
	54	* CLK tree
	55	****************************************************************************/
5817d10b	56	static int dove_tclk;
52167471 SH	57
52167471 SH	58	static DEFINE_SPINLOCK(gating_lock);
2f129bf4 AL	59	static struct clk *tclk;
2f129bf4 AL	60
52167471 SH	61	static struct clk __init dove_register_gate(const char name,
52167471 SH	62	const char *parent, u8 bit_idx)
2f129bf4	63	{
52167471 SH	64	return clk_register_gate(NULL, name, parent, 0,
	65	(void __iomem *)CLOCK_GATING_CONTROL,
	66	bit_idx, 0, &gating_lock);
	67	}
	68
5817d10b	69	static void __init dove_clk_init(void)
2f129bf4	70	{
52167471 SH	71	struct clk usb0, usb1, sata, pex0, pex1, sdio0, *sdio1;
	72	struct clk nand, camera, i2s0, i2s1, crypto, ac97, *pdma;
	73	struct clk xor0, xor1, ge, gephy;
4574b886	74
2f129bf4	75	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
5817d10b	76	dove_tclk);
4574b886	77
52167471 SH	78	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
	79	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
	80	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
	81	pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
	82	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
	83	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
	84	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
	85	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
	86	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
	87	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
	88	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
	89	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
	90	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
	91	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
	92	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
	93	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
	94	gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
	95	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
	96
	97	orion_clkdev_add(NULL, "orion_spi.0", tclk);
	98	orion_clkdev_add(NULL, "orion_spi.1", tclk);
	99	orion_clkdev_add(NULL, "orion_wdt", tclk);
	100	orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
	101
	102	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
	103	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
3fbcd3d0 SH	104	orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
3fbcd3d0 SH	105	orion_clkdev_add(NULL, "sata_mv.0", sata);
52167471 SH	106	orion_clkdev_add("0", "pcie", pex0);
	107	orion_clkdev_add("1", "pcie", pex1);
	108	orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
	109	orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
	110	orion_clkdev_add(NULL, "orion_nand", nand);
	111	orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
	112	orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
	113	orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
	114	orion_clkdev_add(NULL, "mv_crypto", crypto);
	115	orion_clkdev_add(NULL, "dove-ac97", ac97);
	116	orion_clkdev_add(NULL, "dove-pdma", pdma);
0dddee7a TP	117	orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
0dddee7a TP	118	orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
2f129bf4 AL	119	}
2f129bf4 AL	120
edabd38e SB	121	/*****************************************************************************
	122	* EHCI0
	123	****************************************************************************/
edabd38e SB	124	void __init dove_ehci0_init(void)
edabd38e SB	125	{
72053353	126	orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
edabd38e SB	127	}
	128
	129	/*****************************************************************************
	130	* EHCI1
	131	****************************************************************************/
edabd38e SB	132	void __init dove_ehci1_init(void)
edabd38e SB	133	{
db33f4de	134	orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
edabd38e SB	135	}
	136
	137	/*****************************************************************************
	138	* GE00
	139	****************************************************************************/
edabd38e SB	140	void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
edabd38e SB	141	{
30e0f580	142	orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
58569aee AP	143	IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
58569aee AP	144	1600);
edabd38e SB	145	}
	146
	147	/*****************************************************************************
	148	* SoC RTC
	149	****************************************************************************/
edabd38e SB	150	void __init dove_rtc_init(void)
edabd38e SB	151	{
f6eaccb3	152	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
edabd38e SB	153	}
	154
	155	/*****************************************************************************
	156	* SATA
	157	****************************************************************************/
edabd38e SB	158	void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
edabd38e SB	159	{
db33f4de	160	orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
9e613f8a	161
edabd38e SB	162	}
	163
	164	/*****************************************************************************
	165	* UART0
	166	****************************************************************************/
edabd38e SB	167	void __init dove_uart0_init(void)
edabd38e SB	168	{
28a2b450	169	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
74c33576	170	IRQ_DOVE_UART_0, tclk);
edabd38e SB	171	}
	172
	173	/*****************************************************************************
	174	* UART1
	175	****************************************************************************/
edabd38e SB	176	void __init dove_uart1_init(void)
edabd38e SB	177	{
28a2b450	178	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
74c33576	179	IRQ_DOVE_UART_1, tclk);
edabd38e SB	180	}
	181
	182	/*****************************************************************************
	183	* UART2
	184	****************************************************************************/
edabd38e SB	185	void __init dove_uart2_init(void)
edabd38e SB	186	{
28a2b450	187	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
74c33576	188	IRQ_DOVE_UART_2, tclk);
edabd38e SB	189	}
	190
	191	/*****************************************************************************
	192	* UART3
	193	****************************************************************************/
edabd38e SB	194	void __init dove_uart3_init(void)
edabd38e SB	195	{
28a2b450	196	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
74c33576	197	IRQ_DOVE_UART_3, tclk);
edabd38e SB	198	}
	199
	200	/*****************************************************************************
980f9f60	201	* SPI
edabd38e	202	****************************************************************************/
edabd38e SB	203	void __init dove_spi0_init(void)
edabd38e SB	204	{
4574b886	205	orion_spi_init(DOVE_SPI0_PHYS_BASE);
edabd38e SB	206	}
edabd38e SB	207
edabd38e SB	208	void __init dove_spi1_init(void)
edabd38e SB	209	{
4574b886	210	orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
edabd38e SB	211	}
	212
	213	/*****************************************************************************
	214	* I2C
	215	****************************************************************************/
edabd38e SB	216	void __init dove_i2c_init(void)
edabd38e SB	217	{
aac7ffa3	218	orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
edabd38e SB	219	}
	220
	221	/*****************************************************************************
	222	* Time handling
	223	****************************************************************************/
4ee1f6b5 LB	224	void __init dove_init_early(void)
	225	{
	226	orion_time_set_base(TIMER_VIRT_BASE);
	227	}
	228
5817d10b	229	static int __init dove_find_tclk(void)
edabd38e	230	{
edabd38e SB	231	return 166666667;
	232	}
	233
6bb27d73	234	void __init dove_timer_init(void)
edabd38e	235	{
5817d10b	236	dove_tclk = dove_find_tclk();
4ee1f6b5	237	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
5817d10b	238	IRQ_DOVE_BRIDGE, dove_tclk);
edabd38e SB	239	}
edabd38e SB	240
624d0b52 SH	241	/*****************************************************************************
	242	* Cryptographic Engines and Security Accelerator (CESA)
	243	****************************************************************************/
	244	void __init dove_crypto_init(void)
	245	{
	246	orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
	247	DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
	248	}
	249
edabd38e SB	250	/*****************************************************************************
	251	* XOR 0
	252	****************************************************************************/
edabd38e SB	253	void __init dove_xor0_init(void)
edabd38e SB	254	{
db33f4de	255	orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
ee962723	256	IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
edabd38e SB	257	}
	258
	259	/*****************************************************************************
	260	* XOR 1
	261	****************************************************************************/
edabd38e SB	262	void __init dove_xor1_init(void)
edabd38e SB	263	{
ee962723 AL	264	orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
ee962723 AL	265	IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
edabd38e SB	266	}
edabd38e SB	267
16bc90af SB	268	/*****************************************************************************
	269	* SDIO
	270	****************************************************************************/
	271	static u64 sdio_dmamask = DMA_BIT_MASK(32);
	272
	273	static struct resource dove_sdio0_resources[] = {
	274	{
	275	.start = DOVE_SDIO0_PHYS_BASE,
	276	.end = DOVE_SDIO0_PHYS_BASE + 0xff,
	277	.flags = IORESOURCE_MEM,
	278	}, {
	279	.start = IRQ_DOVE_SDIO0,
	280	.end = IRQ_DOVE_SDIO0,
	281	.flags = IORESOURCE_IRQ,
	282	},
	283	};
	284
	285	static struct platform_device dove_sdio0 = {
930e2fe7	286	.name = "sdhci-dove",
16bc90af SB	287	.id = 0,
	288	.dev = {
	289	.dma_mask = &sdio_dmamask,
	290	.coherent_dma_mask = DMA_BIT_MASK(32),
	291	},
	292	.resource = dove_sdio0_resources,
	293	.num_resources = ARRAY_SIZE(dove_sdio0_resources),
	294	};
	295
	296	void __init dove_sdio0_init(void)
	297	{
	298	platform_device_register(&dove_sdio0);
	299	}
	300
	301	static struct resource dove_sdio1_resources[] = {
	302	{
	303	.start = DOVE_SDIO1_PHYS_BASE,
	304	.end = DOVE_SDIO1_PHYS_BASE + 0xff,
	305	.flags = IORESOURCE_MEM,
	306	}, {
	307	.start = IRQ_DOVE_SDIO1,
	308	.end = IRQ_DOVE_SDIO1,
	309	.flags = IORESOURCE_IRQ,
	310	},
	311	};
	312
	313	static struct platform_device dove_sdio1 = {
930e2fe7	314	.name = "sdhci-dove",
16bc90af SB	315	.id = 1,
	316	.dev = {
	317	.dma_mask = &sdio_dmamask,
	318	.coherent_dma_mask = DMA_BIT_MASK(32),
	319	},
	320	.resource = dove_sdio1_resources,
	321	.num_resources = ARRAY_SIZE(dove_sdio1_resources),
	322	};
	323
	324	void __init dove_sdio1_init(void)
	325	{
	326	platform_device_register(&dove_sdio1);
	327	}
	328
edabd38e SB	329	void __init dove_init(void)
edabd38e SB	330	{
5817d10b SH	331	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
5817d10b SH	332	(dove_tclk + 499999) / 1000000);
edabd38e	333
573a652f	334	#ifdef CONFIG_CACHE_TAUROS2
5cc58157	335	tauros2_init(0);
573a652f	336	#endif
edabd38e SB	337	dove_setup_cpu_mbus();
edabd38e SB	338
2f129bf4	339	/* Setup root of clk tree */
5817d10b	340	dove_clk_init();
2f129bf4	341
edabd38e SB	342	/* internal devices that every board has */
	343	dove_rtc_init();
	344	dove_xor0_init();
	345	dove_xor1_init();
	346	}
6ca6ff97 RK	347
	348	void dove_restart(char mode, const char *cmd)
	349	{
	350	/*
	351	* Enable soft reset to assert RSTOUTn.
	352	*/
	353	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
	354
	355	/*
	356	* Assert soft reset.
	357	*/
	358	writel(SOFT_RESET, SYSTEM_SOFT_RESET);
	359
	360	while (1)
	361	;
	362	}
81d2ef7c SH	363
	364	#if defined(CONFIG_MACH_DOVE_DT)
	365	/*
5b03df9a SH	366	* There are still devices that doesn't even know about DT,
5b03df9a SH	367	* get clock gates here and add a clock lookup.
81d2ef7c	368	*/
5b03df9a SH	369	static void __init dove_legacy_clk_init(void)
	370	{
	371	struct device_node *np = of_find_compatible_node(NULL, NULL,
	372	"marvell,dove-gating-clock");
	373	struct of_phandle_args clkspec;
	374
	375	clkspec.np = np;
	376	clkspec.args_count = 1;
	377
	378	clkspec.args[0] = CLOCK_GATING_BIT_USB0;
	379	orion_clkdev_add(NULL, "orion-ehci.0",
	380	of_clk_get_from_provider(&clkspec));
	381
	382	clkspec.args[0] = CLOCK_GATING_BIT_USB1;
	383	orion_clkdev_add(NULL, "orion-ehci.1",
	384	of_clk_get_from_provider(&clkspec));
	385
	386	clkspec.args[0] = CLOCK_GATING_BIT_GBE;
	387	orion_clkdev_add(NULL, "mv643xx_eth_port.0",
	388	of_clk_get_from_provider(&clkspec));
	389
	390	clkspec.args[0] = CLOCK_GATING_BIT_PCIE0;
	391	orion_clkdev_add("0", "pcie",
	392	of_clk_get_from_provider(&clkspec));
	393
	394	clkspec.args[0] = CLOCK_GATING_BIT_PCIE1;
	395	orion_clkdev_add("1", "pcie",
	396	of_clk_get_from_provider(&clkspec));
5b03df9a SH	397	}
	398
	399	static void __init dove_of_clk_init(void)
	400	{
	401	mvebu_clocks_init();
	402	dove_legacy_clk_init();
	403	}
81d2ef7c SH	404
	405	static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
	406	.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
	407	};
	408
	409	static void __init dove_dt_init(void)
	410	{
	411	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
	412	(dove_tclk + 499999) / 1000000);
	413
	414	#ifdef CONFIG_CACHE_TAUROS2
fd57c65c	415	tauros2_init(0);
81d2ef7c SH	416	#endif
	417	dove_setup_cpu_mbus();
	418
	419	/* Setup root of clk tree */
5b03df9a	420	dove_of_clk_init();
81d2ef7c SH	421
	422	/* Internal devices not ported to DT yet */
	423	dove_rtc_init();
81d2ef7c SH	424
	425	dove_ge00_init(&dove_dt_ge00_data);
	426	dove_ehci0_init();
	427	dove_ehci1_init();
	428	dove_pcie_init(1, 1);
81d2ef7c	429
5b03df9a	430	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
81d2ef7c SH	431	}
	432
	433	static const char * const dove_dt_board_compat[] = {
	434	"marvell,dove",
	435	NULL
	436	};
	437
	438	DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
	439	.map_io = dove_map_io,
	440	.init_early = dove_init_early,
	441	.init_irq = orion_dt_init_irq,
6bb27d73	442	.init_time = dove_timer_init,
81d2ef7c SH	443	.init_machine = dove_dt_init,
	444	.restart = dove_restart,
	445	.dt_compat = dove_dt_board_compat,
	446	MACHINE_END
	447	#endif