Commit | Line | Data |
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edabd38e SB |
1 | /* |
2 | * arch/arm/mach-dove/common.c | |
3 | * | |
4 | * Core functions for Marvell Dove 88AP510 System On Chip | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/pci.h> | |
2f129bf4 | 16 | #include <linux/clk-provider.h> |
edabd38e | 17 | #include <linux/ata_platform.h> |
edabd38e SB |
18 | #include <linux/gpio.h> |
19 | #include <asm/page.h> | |
20 | #include <asm/setup.h> | |
21 | #include <asm/timex.h> | |
573a652f | 22 | #include <asm/hardware/cache-tauros2.h> |
edabd38e SB |
23 | #include <asm/mach/map.h> |
24 | #include <asm/mach/time.h> | |
25 | #include <asm/mach/pci.h> | |
26 | #include <mach/dove.h> | |
52167471 | 27 | #include <mach/pm.h> |
edabd38e SB |
28 | #include <mach/bridge-regs.h> |
29 | #include <asm/mach/arch.h> | |
30 | #include <linux/irq.h> | |
edabd38e | 31 | #include <plat/time.h> |
72053353 | 32 | #include <plat/ehci-orion.h> |
28a2b450 | 33 | #include <plat/common.h> |
45173d5e | 34 | #include <plat/addr-map.h> |
edabd38e SB |
35 | #include "common.h" |
36 | ||
37 | /***************************************************************************** | |
38 | * I/O Address Mapping | |
39 | ****************************************************************************/ | |
40 | static struct map_desc dove_io_desc[] __initdata = { | |
41 | { | |
42 | .virtual = DOVE_SB_REGS_VIRT_BASE, | |
43 | .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), | |
44 | .length = DOVE_SB_REGS_SIZE, | |
45 | .type = MT_DEVICE, | |
46 | }, { | |
47 | .virtual = DOVE_NB_REGS_VIRT_BASE, | |
48 | .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), | |
49 | .length = DOVE_NB_REGS_SIZE, | |
50 | .type = MT_DEVICE, | |
51 | }, { | |
52 | .virtual = DOVE_PCIE0_IO_VIRT_BASE, | |
53 | .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), | |
54 | .length = DOVE_PCIE0_IO_SIZE, | |
55 | .type = MT_DEVICE, | |
56 | }, { | |
57 | .virtual = DOVE_PCIE1_IO_VIRT_BASE, | |
58 | .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), | |
59 | .length = DOVE_PCIE1_IO_SIZE, | |
60 | .type = MT_DEVICE, | |
61 | }, | |
62 | }; | |
63 | ||
64 | void __init dove_map_io(void) | |
65 | { | |
66 | iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); | |
67 | } | |
68 | ||
2f129bf4 AL |
69 | /***************************************************************************** |
70 | * CLK tree | |
71 | ****************************************************************************/ | |
5817d10b | 72 | static int dove_tclk; |
52167471 SH |
73 | |
74 | static DEFINE_SPINLOCK(gating_lock); | |
2f129bf4 AL |
75 | static struct clk *tclk; |
76 | ||
52167471 SH |
77 | static struct clk __init *dove_register_gate(const char *name, |
78 | const char *parent, u8 bit_idx) | |
79 | { | |
80 | return clk_register_gate(NULL, name, parent, 0, | |
81 | (void __iomem *)CLOCK_GATING_CONTROL, | |
82 | bit_idx, 0, &gating_lock); | |
83 | } | |
84 | ||
5817d10b | 85 | static void __init dove_clk_init(void) |
2f129bf4 | 86 | { |
52167471 SH |
87 | struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; |
88 | struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; | |
89 | struct clk *xor0, *xor1, *ge, *gephy; | |
90 | ||
2f129bf4 | 91 | tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, |
5817d10b | 92 | dove_tclk); |
4574b886 | 93 | |
52167471 SH |
94 | usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); |
95 | usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); | |
96 | sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA); | |
97 | pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0); | |
98 | pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1); | |
99 | sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0); | |
100 | sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1); | |
101 | nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND); | |
102 | camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA); | |
103 | i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0); | |
104 | i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1); | |
105 | crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO); | |
106 | ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97); | |
107 | pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA); | |
108 | xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0); | |
109 | xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1); | |
110 | gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY); | |
111 | ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE); | |
112 | ||
113 | orion_clkdev_add(NULL, "orion_spi.0", tclk); | |
114 | orion_clkdev_add(NULL, "orion_spi.1", tclk); | |
115 | orion_clkdev_add(NULL, "orion_wdt", tclk); | |
116 | orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk); | |
117 | ||
118 | orion_clkdev_add(NULL, "orion-ehci.0", usb0); | |
119 | orion_clkdev_add(NULL, "orion-ehci.1", usb1); | |
120 | orion_clkdev_add(NULL, "mv643xx_eth.0", ge); | |
121 | orion_clkdev_add("0", "sata_mv.0", sata); | |
122 | orion_clkdev_add("0", "pcie", pex0); | |
123 | orion_clkdev_add("1", "pcie", pex1); | |
124 | orion_clkdev_add(NULL, "sdhci-dove.0", sdio0); | |
125 | orion_clkdev_add(NULL, "sdhci-dove.1", sdio1); | |
126 | orion_clkdev_add(NULL, "orion_nand", nand); | |
127 | orion_clkdev_add(NULL, "cafe1000-ccic.0", camera); | |
128 | orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0); | |
129 | orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1); | |
130 | orion_clkdev_add(NULL, "mv_crypto", crypto); | |
131 | orion_clkdev_add(NULL, "dove-ac97", ac97); | |
132 | orion_clkdev_add(NULL, "dove-pdma", pdma); | |
133 | orion_clkdev_add(NULL, "mv_xor_shared.0", xor0); | |
134 | orion_clkdev_add(NULL, "mv_xor_shared.1", xor1); | |
2f129bf4 AL |
135 | } |
136 | ||
edabd38e SB |
137 | /***************************************************************************** |
138 | * EHCI0 | |
139 | ****************************************************************************/ | |
edabd38e SB |
140 | void __init dove_ehci0_init(void) |
141 | { | |
72053353 | 142 | orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); |
edabd38e SB |
143 | } |
144 | ||
145 | /***************************************************************************** | |
146 | * EHCI1 | |
147 | ****************************************************************************/ | |
edabd38e SB |
148 | void __init dove_ehci1_init(void) |
149 | { | |
db33f4de | 150 | orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); |
edabd38e SB |
151 | } |
152 | ||
153 | /***************************************************************************** | |
154 | * GE00 | |
155 | ****************************************************************************/ | |
edabd38e SB |
156 | void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) |
157 | { | |
30e0f580 | 158 | orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, |
58569aee AP |
159 | IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, |
160 | 1600); | |
edabd38e SB |
161 | } |
162 | ||
163 | /***************************************************************************** | |
164 | * SoC RTC | |
165 | ****************************************************************************/ | |
edabd38e SB |
166 | void __init dove_rtc_init(void) |
167 | { | |
f6eaccb3 | 168 | orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); |
edabd38e SB |
169 | } |
170 | ||
171 | /***************************************************************************** | |
172 | * SATA | |
173 | ****************************************************************************/ | |
edabd38e SB |
174 | void __init dove_sata_init(struct mv_sata_platform_data *sata_data) |
175 | { | |
db33f4de | 176 | orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); |
9e613f8a | 177 | |
edabd38e SB |
178 | } |
179 | ||
180 | /***************************************************************************** | |
181 | * UART0 | |
182 | ****************************************************************************/ | |
edabd38e SB |
183 | void __init dove_uart0_init(void) |
184 | { | |
28a2b450 | 185 | orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, |
74c33576 | 186 | IRQ_DOVE_UART_0, tclk); |
edabd38e SB |
187 | } |
188 | ||
189 | /***************************************************************************** | |
190 | * UART1 | |
191 | ****************************************************************************/ | |
edabd38e SB |
192 | void __init dove_uart1_init(void) |
193 | { | |
28a2b450 | 194 | orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, |
74c33576 | 195 | IRQ_DOVE_UART_1, tclk); |
edabd38e SB |
196 | } |
197 | ||
198 | /***************************************************************************** | |
199 | * UART2 | |
200 | ****************************************************************************/ | |
edabd38e SB |
201 | void __init dove_uart2_init(void) |
202 | { | |
28a2b450 | 203 | orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, |
74c33576 | 204 | IRQ_DOVE_UART_2, tclk); |
edabd38e SB |
205 | } |
206 | ||
207 | /***************************************************************************** | |
208 | * UART3 | |
209 | ****************************************************************************/ | |
edabd38e SB |
210 | void __init dove_uart3_init(void) |
211 | { | |
28a2b450 | 212 | orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, |
74c33576 | 213 | IRQ_DOVE_UART_3, tclk); |
edabd38e SB |
214 | } |
215 | ||
216 | /***************************************************************************** | |
980f9f60 | 217 | * SPI |
edabd38e | 218 | ****************************************************************************/ |
edabd38e SB |
219 | void __init dove_spi0_init(void) |
220 | { | |
4574b886 | 221 | orion_spi_init(DOVE_SPI0_PHYS_BASE); |
edabd38e SB |
222 | } |
223 | ||
edabd38e SB |
224 | void __init dove_spi1_init(void) |
225 | { | |
4574b886 | 226 | orion_spi_1_init(DOVE_SPI1_PHYS_BASE); |
edabd38e SB |
227 | } |
228 | ||
229 | /***************************************************************************** | |
230 | * I2C | |
231 | ****************************************************************************/ | |
edabd38e SB |
232 | void __init dove_i2c_init(void) |
233 | { | |
aac7ffa3 | 234 | orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); |
edabd38e SB |
235 | } |
236 | ||
237 | /***************************************************************************** | |
238 | * Time handling | |
239 | ****************************************************************************/ | |
4ee1f6b5 LB |
240 | void __init dove_init_early(void) |
241 | { | |
242 | orion_time_set_base(TIMER_VIRT_BASE); | |
243 | } | |
244 | ||
5817d10b | 245 | static int __init dove_find_tclk(void) |
edabd38e | 246 | { |
edabd38e SB |
247 | return 166666667; |
248 | } | |
249 | ||
ca2ac5cc | 250 | static void __init dove_timer_init(void) |
edabd38e | 251 | { |
5817d10b | 252 | dove_tclk = dove_find_tclk(); |
4ee1f6b5 | 253 | orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, |
5817d10b | 254 | IRQ_DOVE_BRIDGE, dove_tclk); |
edabd38e SB |
255 | } |
256 | ||
257 | struct sys_timer dove_timer = { | |
258 | .init = dove_timer_init, | |
259 | }; | |
260 | ||
edabd38e SB |
261 | /***************************************************************************** |
262 | * XOR 0 | |
263 | ****************************************************************************/ | |
edabd38e SB |
264 | void __init dove_xor0_init(void) |
265 | { | |
db33f4de | 266 | orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, |
ee962723 | 267 | IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); |
edabd38e SB |
268 | } |
269 | ||
270 | /***************************************************************************** | |
271 | * XOR 1 | |
272 | ****************************************************************************/ | |
edabd38e SB |
273 | void __init dove_xor1_init(void) |
274 | { | |
ee962723 AL |
275 | orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, |
276 | IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); | |
edabd38e SB |
277 | } |
278 | ||
16bc90af SB |
279 | /***************************************************************************** |
280 | * SDIO | |
281 | ****************************************************************************/ | |
282 | static u64 sdio_dmamask = DMA_BIT_MASK(32); | |
283 | ||
284 | static struct resource dove_sdio0_resources[] = { | |
285 | { | |
286 | .start = DOVE_SDIO0_PHYS_BASE, | |
287 | .end = DOVE_SDIO0_PHYS_BASE + 0xff, | |
288 | .flags = IORESOURCE_MEM, | |
289 | }, { | |
290 | .start = IRQ_DOVE_SDIO0, | |
291 | .end = IRQ_DOVE_SDIO0, | |
292 | .flags = IORESOURCE_IRQ, | |
293 | }, | |
294 | }; | |
295 | ||
296 | static struct platform_device dove_sdio0 = { | |
930e2fe7 | 297 | .name = "sdhci-dove", |
16bc90af SB |
298 | .id = 0, |
299 | .dev = { | |
300 | .dma_mask = &sdio_dmamask, | |
301 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
302 | }, | |
303 | .resource = dove_sdio0_resources, | |
304 | .num_resources = ARRAY_SIZE(dove_sdio0_resources), | |
305 | }; | |
306 | ||
307 | void __init dove_sdio0_init(void) | |
308 | { | |
309 | platform_device_register(&dove_sdio0); | |
310 | } | |
311 | ||
312 | static struct resource dove_sdio1_resources[] = { | |
313 | { | |
314 | .start = DOVE_SDIO1_PHYS_BASE, | |
315 | .end = DOVE_SDIO1_PHYS_BASE + 0xff, | |
316 | .flags = IORESOURCE_MEM, | |
317 | }, { | |
318 | .start = IRQ_DOVE_SDIO1, | |
319 | .end = IRQ_DOVE_SDIO1, | |
320 | .flags = IORESOURCE_IRQ, | |
321 | }, | |
322 | }; | |
323 | ||
324 | static struct platform_device dove_sdio1 = { | |
930e2fe7 | 325 | .name = "sdhci-dove", |
16bc90af SB |
326 | .id = 1, |
327 | .dev = { | |
328 | .dma_mask = &sdio_dmamask, | |
329 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
330 | }, | |
331 | .resource = dove_sdio1_resources, | |
332 | .num_resources = ARRAY_SIZE(dove_sdio1_resources), | |
333 | }; | |
334 | ||
335 | void __init dove_sdio1_init(void) | |
336 | { | |
337 | platform_device_register(&dove_sdio1); | |
338 | } | |
339 | ||
edabd38e SB |
340 | void __init dove_init(void) |
341 | { | |
5817d10b SH |
342 | pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", |
343 | (dove_tclk + 499999) / 1000000); | |
edabd38e | 344 | |
573a652f LB |
345 | #ifdef CONFIG_CACHE_TAUROS2 |
346 | tauros2_init(); | |
347 | #endif | |
edabd38e SB |
348 | dove_setup_cpu_mbus(); |
349 | ||
2f129bf4 | 350 | /* Setup root of clk tree */ |
5817d10b | 351 | dove_clk_init(); |
2f129bf4 | 352 | |
edabd38e SB |
353 | /* internal devices that every board has */ |
354 | dove_rtc_init(); | |
355 | dove_xor0_init(); | |
356 | dove_xor1_init(); | |
357 | } | |
6ca6ff97 RK |
358 | |
359 | void dove_restart(char mode, const char *cmd) | |
360 | { | |
361 | /* | |
362 | * Enable soft reset to assert RSTOUTn. | |
363 | */ | |
364 | writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); | |
365 | ||
366 | /* | |
367 | * Assert soft reset. | |
368 | */ | |
369 | writel(SOFT_RESET, SYSTEM_SOFT_RESET); | |
370 | ||
371 | while (1) | |
372 | ; | |
373 | } |