[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-davinci / devices-da8xx.c

/*
 * DA8XX/OMAP L1XX platform device data
 *
 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
 * Derived from code that was:
 *	Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>

#include <mach/cputype.h>
#include <mach/common.h>
#include <mach/time.h>
#include <mach/da8xx.h>
#include <mach/cpuidle.h>

#include "clock.h"

#define DA8XX_TPCC_BASE			0x01c00000
#define DA850_MMCSD1_BASE		0x01e1b000
#define DA850_TPCC1_BASE		0x01e30000
#define DA8XX_TPTC0_BASE		0x01c08000
#define DA8XX_TPTC1_BASE		0x01c08400
#define DA850_TPTC2_BASE		0x01e38000
#define DA8XX_WDOG_BASE			0x01c21000 /* DA8XX_TIMER64P1_BASE */
#define DA8XX_I2C0_BASE			0x01c22000
#define DA8XX_RTC_BASE			0x01C23000
#define DA8XX_EMAC_CPPI_PORT_BASE	0x01e20000
#define DA8XX_EMAC_CPGMACSS_BASE	0x01e22000
#define DA8XX_EMAC_CPGMAC_BASE		0x01e23000
#define DA8XX_EMAC_MDIO_BASE		0x01e24000
#define DA8XX_GPIO_BASE			0x01e26000
#define DA8XX_I2C1_BASE			0x01e28000

#define DA8XX_EMAC_CTRL_REG_OFFSET	0x3000
#define DA8XX_EMAC_MOD_REG_OFFSET	0x2000
#define DA8XX_EMAC_RAM_OFFSET		0x0000
#define DA8XX_EMAC_CTRL_RAM_SIZE	SZ_8K

void __iomem *da8xx_syscfg0_base;
void __iomem *da8xx_syscfg1_base;

static struct plat_serial8250_port da8xx_serial_pdata[] = {
	{
		.mapbase	= DA8XX_UART0_BASE,
		.irq		= IRQ_DA8XX_UARTINT0,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
					UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.mapbase	= DA8XX_UART1_BASE,
		.irq		= IRQ_DA8XX_UARTINT1,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
					UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.mapbase	= DA8XX_UART2_BASE,
		.irq		= IRQ_DA8XX_UARTINT2,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
					UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.flags	= 0,
	},
};

struct platform_device da8xx_serial_device = {
	.name	= "serial8250",
	.id	= PLAT8250_DEV_PLATFORM,
	.dev	= {
		.platform_data	= da8xx_serial_pdata,
	},
};

static const s8 da8xx_queue_tc_mapping[][2] = {
	/* {event queue no, TC no} */
	{0, 0},
	{1, 1},
	{-1, -1}
};

static const s8 da8xx_queue_priority_mapping[][2] = {
	/* {event queue no, Priority} */
	{0, 3},
	{1, 7},
	{-1, -1}
};

static const s8 da850_queue_tc_mapping[][2] = {
	/* {event queue no, TC no} */
	{0, 0},
	{-1, -1}
};

static const s8 da850_queue_priority_mapping[][2] = {
	/* {event queue no, Priority} */
	{0, 3},
	{-1, -1}
};

static struct edma_soc_info da830_edma_cc0_info = {
	.n_channel		= 32,
	.n_region		= 4,
	.n_slot			= 128,
	.n_tc			= 2,
	.n_cc			= 1,
	.queue_tc_mapping	= da8xx_queue_tc_mapping,
	.queue_priority_mapping	= da8xx_queue_priority_mapping,
};

static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
	&da830_edma_cc0_info,
};

static struct edma_soc_info da850_edma_cc_info[] = {
	{
		.n_channel		= 32,
		.n_region		= 4,
		.n_slot			= 128,
		.n_tc			= 2,
		.n_cc			= 1,
		.queue_tc_mapping	= da8xx_queue_tc_mapping,
		.queue_priority_mapping	= da8xx_queue_priority_mapping,
	},
	{
		.n_channel		= 32,
		.n_region		= 4,
		.n_slot			= 128,
		.n_tc			= 1,
		.n_cc			= 1,
		.queue_tc_mapping	= da850_queue_tc_mapping,
		.queue_priority_mapping	= da850_queue_priority_mapping,
	},
};

static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
	&da850_edma_cc_info[0],
	&da850_edma_cc_info[1],
};

static struct resource da830_edma_resources[] = {
	{
		.name	= "edma_cc0",
		.start	= DA8XX_TPCC_BASE,
		.end	= DA8XX_TPCC_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc0",
		.start	= DA8XX_TPTC0_BASE,
		.end	= DA8XX_TPTC0_BASE + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc1",
		.start	= DA8XX_TPTC1_BASE,
		.end	= DA8XX_TPTC1_BASE + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma0",
		.start	= IRQ_DA8XX_CCINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.name	= "edma0_err",
		.start	= IRQ_DA8XX_CCERRINT,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct resource da850_edma_resources[] = {
	{
		.name	= "edma_cc0",
		.start	= DA8XX_TPCC_BASE,
		.end	= DA8XX_TPCC_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc0",
		.start	= DA8XX_TPTC0_BASE,
		.end	= DA8XX_TPTC0_BASE + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc1",
		.start	= DA8XX_TPTC1_BASE,
		.end	= DA8XX_TPTC1_BASE + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_cc1",
		.start	= DA850_TPCC1_BASE,
		.end	= DA850_TPCC1_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc2",
		.start	= DA850_TPTC2_BASE,
		.end	= DA850_TPTC2_BASE + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma0",
		.start	= IRQ_DA8XX_CCINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.name	= "edma0_err",
		.start	= IRQ_DA8XX_CCERRINT,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.name	= "edma1",
		.start	= IRQ_DA850_CCINT1,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.name	= "edma1_err",
		.start	= IRQ_DA850_CCERRINT1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device da830_edma_device = {
	.name		= "edma",
	.id		= -1,
	.dev = {
		.platform_data = da830_edma_info,
	},
	.num_resources	= ARRAY_SIZE(da830_edma_resources),
	.resource	= da830_edma_resources,
};

static struct platform_device da850_edma_device = {
	.name		= "edma",
	.id		= -1,
	.dev = {
		.platform_data = da850_edma_info,
	},
	.num_resources	= ARRAY_SIZE(da850_edma_resources),
	.resource	= da850_edma_resources,
};

int __init da830_register_edma(struct edma_rsv_info *rsv)
{
	da830_edma_cc0_info.rsv = rsv;

	return platform_device_register(&da830_edma_device);
}

int __init da850_register_edma(struct edma_rsv_info *rsv[2])
{
	if (rsv) {
		da850_edma_cc_info[0].rsv = rsv[0];
		da850_edma_cc_info[1].rsv = rsv[1];
	}

	return platform_device_register(&da850_edma_device);
}

static struct resource da8xx_i2c_resources0[] = {
	{
		.start	= DA8XX_I2C0_BASE,
		.end	= DA8XX_I2C0_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_DA8XX_I2CINT0,
		.end	= IRQ_DA8XX_I2CINT0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device da8xx_i2c_device0 = {
	.name		= "i2c_davinci",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources0),
	.resource	= da8xx_i2c_resources0,
};

static struct resource da8xx_i2c_resources1[] = {
	{
		.start	= DA8XX_I2C1_BASE,
		.end	= DA8XX_I2C1_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_DA8XX_I2CINT1,
		.end	= IRQ_DA8XX_I2CINT1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device da8xx_i2c_device1 = {
	.name		= "i2c_davinci",
	.id		= 2,
	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources1),
	.resource	= da8xx_i2c_resources1,
};

int __init da8xx_register_i2c(int instance,
		struct davinci_i2c_platform_data *pdata)
{
	struct platform_device *pdev;

	if (instance == 0)
		pdev = &da8xx_i2c_device0;
	else if (instance == 1)
		pdev = &da8xx_i2c_device1;
	else
		return -EINVAL;

	pdev->dev.platform_data = pdata;
	return platform_device_register(pdev);
}

static struct resource da8xx_watchdog_resources[] = {
	{
		.start	= DA8XX_WDOG_BASE,
		.end	= DA8XX_WDOG_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device da8xx_wdt_device = {
	.name		= "watchdog",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(da8xx_watchdog_resources),
	.resource	= da8xx_watchdog_resources,
};

int __init da8xx_register_watchdog(void)
{
	return platform_device_register(&da8xx_wdt_device);
}

static struct resource da8xx_emac_resources[] = {
	{
		.start	= DA8XX_EMAC_CPPI_PORT_BASE,
		.end	= DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_DA8XX_C0_RX_THRESH_PULSE,
		.end	= IRQ_DA8XX_C0_RX_THRESH_PULSE,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_DA8XX_C0_RX_PULSE,
		.end	= IRQ_DA8XX_C0_RX_PULSE,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_DA8XX_C0_TX_PULSE,
		.end	= IRQ_DA8XX_C0_TX_PULSE,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_DA8XX_C0_MISC_PULSE,
		.end	= IRQ_DA8XX_C0_MISC_PULSE,
		.flags	= IORESOURCE_IRQ,
	},
};

struct emac_platform_data da8xx_emac_pdata = {
	.ctrl_reg_offset	= DA8XX_EMAC_CTRL_REG_OFFSET,
	.ctrl_mod_reg_offset	= DA8XX_EMAC_MOD_REG_OFFSET,
	.ctrl_ram_offset	= DA8XX_EMAC_RAM_OFFSET,
	.ctrl_ram_size		= DA8XX_EMAC_CTRL_RAM_SIZE,
	.version		= EMAC_VERSION_2,
};

static struct platform_device da8xx_emac_device = {
	.name		= "davinci_emac",
	.id		= 1,
	.dev = {
		.platform_data	= &da8xx_emac_pdata,
	},
	.num_resources	= ARRAY_SIZE(da8xx_emac_resources),
	.resource	= da8xx_emac_resources,
};

static struct resource da8xx_mdio_resources[] = {
	{
		.start	= DA8XX_EMAC_MDIO_BASE,
		.end	= DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device da8xx_mdio_device = {
	.name		= "davinci_mdio",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(da8xx_mdio_resources),
	.resource	= da8xx_mdio_resources,
};

int __init da8xx_register_emac(void)
{
	int ret;

	ret = platform_device_register(&da8xx_mdio_device);
	if (ret < 0)
		return ret;
	ret = platform_device_register(&da8xx_emac_device);
	if (ret < 0)
		return ret;
	ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
			    NULL, &da8xx_emac_device.dev);
	return ret;
}

static struct resource da830_mcasp1_resources[] = {
	{
		.name	= "mcasp1",
		.start	= DAVINCI_DA830_MCASP1_REG_BASE,
		.end	= DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
		.flags	= IORESOURCE_MEM,
	},
	/* TX event */
	{
		.start	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
		.end	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
		.flags	= IORESOURCE_DMA,
	},
	/* RX event */
	{
		.start	= DAVINCI_DA830_DMA_MCASP1_AREVT,
		.end	= DAVINCI_DA830_DMA_MCASP1_AREVT,
		.flags	= IORESOURCE_DMA,
	},
};

static struct platform_device da830_mcasp1_device = {
	.name		= "davinci-mcasp",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(da830_mcasp1_resources),
	.resource	= da830_mcasp1_resources,
};

static struct resource da850_mcasp_resources[] = {
	{
		.name	= "mcasp",
		.start	= DAVINCI_DA8XX_MCASP0_REG_BASE,
		.end	= DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
		.flags	= IORESOURCE_MEM,
	},
	/* TX event */
	{
		.start	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
		.end	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
		.flags	= IORESOURCE_DMA,
	},
	/* RX event */
	{
		.start	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
		.end	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
		.flags	= IORESOURCE_DMA,
	},
};

static struct platform_device da850_mcasp_device = {
	.name		= "davinci-mcasp",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(da850_mcasp_resources),
	.resource	= da850_mcasp_resources,
};

void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
{
	/* DA830/OMAP-L137 has 3 instances of McASP */
	if (cpu_is_davinci_da830() && id == 1) {
		da830_mcasp1_device.dev.platform_data = pdata;
		platform_device_register(&da830_mcasp1_device);
	} else if (cpu_is_davinci_da850()) {
		da850_mcasp_device.dev.platform_data = pdata;
		platform_device_register(&da850_mcasp_device);
	}
}

static const struct display_panel disp_panel = {
	QVGA,
	16,
	16,
	COLOR_ACTIVE,
};

static struct lcd_ctrl_config lcd_cfg = {
	&disp_panel,
	.ac_bias		= 255,
	.ac_bias_intrpt		= 0,
	.dma_burst_sz		= 16,
	.bpp			= 16,
	.fdd			= 255,
	.tft_alt_mode		= 0,
	.stn_565_mode		= 0,
	.mono_8bit_mode		= 0,
	.invert_line_clock	= 1,
	.invert_frm_clock	= 1,
	.sync_edge		= 0,
	.sync_ctrl		= 1,
	.raster_order		= 0,
};

struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
	.manu_name		= "sharp",
	.controller_data	= &lcd_cfg,
	.type			= "Sharp_LCD035Q3DG01",
};

struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
	.manu_name		= "sharp",
	.controller_data	= &lcd_cfg,
	.type			= "Sharp_LK043T1DG01",
};

static struct resource da8xx_lcdc_resources[] = {
	[0] = { /* registers */
		.start  = DA8XX_LCD_CNTRL_BASE,
		.end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
		.flags  = IORESOURCE_MEM,
	},
	[1] = { /* interrupt */
		.start  = IRQ_DA8XX_LCDINT,
		.end    = IRQ_DA8XX_LCDINT,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device da8xx_lcdc_device = {
	.name		= "da8xx_lcdc",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(da8xx_lcdc_resources),
	.resource	= da8xx_lcdc_resources,
};

int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
{
	da8xx_lcdc_device.dev.platform_data = pdata;
	return platform_device_register(&da8xx_lcdc_device);
}

static struct resource da8xx_mmcsd0_resources[] = {
	{		/* registers */
		.start	= DA8XX_MMCSD0_BASE,
		.end	= DA8XX_MMCSD0_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{		/* interrupt */
		.start	= IRQ_DA8XX_MMCSDINT0,
		.end	= IRQ_DA8XX_MMCSDINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{		/* DMA RX */
		.start	= EDMA_CTLR_CHAN(0, 16),
		.end	= EDMA_CTLR_CHAN(0, 16),
		.flags	= IORESOURCE_DMA,
	},
	{		/* DMA TX */
		.start	= EDMA_CTLR_CHAN(0, 17),
		.end	= EDMA_CTLR_CHAN(0, 17),
		.flags	= IORESOURCE_DMA,
	},
};

static struct platform_device da8xx_mmcsd0_device = {
	.name		= "davinci_mmc",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(da8xx_mmcsd0_resources),
	.resource	= da8xx_mmcsd0_resources,
};

int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
{
	da8xx_mmcsd0_device.dev.platform_data = config;
	return platform_device_register(&da8xx_mmcsd0_device);
}

#ifdef CONFIG_ARCH_DAVINCI_DA850
static struct resource da850_mmcsd1_resources[] = {
	{		/* registers */
		.start	= DA850_MMCSD1_BASE,
		.end	= DA850_MMCSD1_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{		/* interrupt */
		.start	= IRQ_DA850_MMCSDINT0_1,
		.end	= IRQ_DA850_MMCSDINT0_1,
		.flags	= IORESOURCE_IRQ,
	},
	{		/* DMA RX */
		.start	= EDMA_CTLR_CHAN(1, 28),
		.end	= EDMA_CTLR_CHAN(1, 28),
		.flags	= IORESOURCE_DMA,
	},
	{		/* DMA TX */
		.start	= EDMA_CTLR_CHAN(1, 29),
		.end	= EDMA_CTLR_CHAN(1, 29),
		.flags	= IORESOURCE_DMA,
	},
};

static struct platform_device da850_mmcsd1_device = {
	.name		= "davinci_mmc",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(da850_mmcsd1_resources),
	.resource	= da850_mmcsd1_resources,
};

int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
{
	da850_mmcsd1_device.dev.platform_data = config;
	return platform_device_register(&da850_mmcsd1_device);
}
#endif

static struct resource da8xx_rtc_resources[] = {
	{
		.start		= DA8XX_RTC_BASE,
		.end		= DA8XX_RTC_BASE + SZ_4K - 1,
		.flags		= IORESOURCE_MEM,
	},
	{ /* timer irq */
		.start		= IRQ_DA8XX_RTC,
		.end		= IRQ_DA8XX_RTC,
		.flags		= IORESOURCE_IRQ,
	},
	{ /* alarm irq */
		.start		= IRQ_DA8XX_RTC,
		.end		= IRQ_DA8XX_RTC,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device da8xx_rtc_device = {
	.name           = "omap_rtc",
	.id             = -1,
	.num_resources	= ARRAY_SIZE(da8xx_rtc_resources),
	.resource	= da8xx_rtc_resources,
};

int da8xx_register_rtc(void)
{
	int ret;
	void __iomem *base;

	base = ioremap(DA8XX_RTC_BASE, SZ_4K);
	if (WARN_ON(!base))
		return -ENOMEM;

	/* Unlock the rtc's registers */
	__raw_writel(0x83e70b13, base + 0x6c);
	__raw_writel(0x95a4f1e0, base + 0x70);

	iounmap(base);

	ret = platform_device_register(&da8xx_rtc_device);
	if (!ret)
		/* Atleast on DA850, RTC is a wakeup source */
		device_init_wakeup(&da8xx_rtc_device.dev, true);

	return ret;
}

static void __iomem *da8xx_ddr2_ctlr_base;
void __iomem * __init da8xx_get_mem_ctlr(void)
{
	if (da8xx_ddr2_ctlr_base)
		return da8xx_ddr2_ctlr_base;

	da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
	if (!da8xx_ddr2_ctlr_base)
		pr_warning("%s: Unable to map DDR2 controller",	__func__);

	return da8xx_ddr2_ctlr_base;
}

static struct resource da8xx_cpuidle_resources[] = {
	{
		.start		= DA8XX_DDR2_CTL_BASE,
		.end		= DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
		.flags		= IORESOURCE_MEM,
	},
};

/* DA8XX devices support DDR2 power down */
static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
	.ddr2_pdown	= 1,
};


static struct platform_device da8xx_cpuidle_device = {
	.name			= "cpuidle-davinci",
	.num_resources		= ARRAY_SIZE(da8xx_cpuidle_resources),
	.resource		= da8xx_cpuidle_resources,
	.dev = {
		.platform_data	= &da8xx_cpuidle_pdata,
	},
};

int __init da8xx_register_cpuidle(void)
{
	da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();

	return platform_device_register(&da8xx_cpuidle_device);
}
Commit	Line	Data
55c79a40 MG	1	/*
	2	* DA8XX/OMAP L1XX platform device data
	3	*
	4	* Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
	5	* Derived from code that was:
	6	* Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
55c79a40 MG	13	#include <linux/init.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/dma-mapping.h>
	16	#include <linux/serial_8250.h>
	17
	18	#include <mach/cputype.h>
	19	#include <mach/common.h>
	20	#include <mach/time.h>
	21	#include <mach/da8xx.h>
1960e693	22	#include <mach/cpuidle.h>
55c79a40 MG	23
	24	#include "clock.h"
	25
	26	#define DA8XX_TPCC_BASE 0x01c00000
b8241aef	27	#define DA850_MMCSD1_BASE 0x01e1b000
3f995f2f	28	#define DA850_TPCC1_BASE 0x01e30000
55c79a40 MG	29	#define DA8XX_TPTC0_BASE 0x01c08000
55c79a40 MG	30	#define DA8XX_TPTC1_BASE 0x01c08400
3f995f2f	31	#define DA850_TPTC2_BASE 0x01e38000
55c79a40 MG	32	#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
55c79a40 MG	33	#define DA8XX_I2C0_BASE 0x01c22000
c51df70b	34	#define DA8XX_RTC_BASE 0x01C23000
55c79a40 MG	35	#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
	36	#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
	37	#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
	38	#define DA8XX_EMAC_MDIO_BASE 0x01e24000
	39	#define DA8XX_GPIO_BASE 0x01e26000
	40	#define DA8XX_I2C1_BASE 0x01e28000
	41
	42	#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
	43	#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
	44	#define DA8XX_EMAC_RAM_OFFSET 0x0000
55c79a40 MG	45	#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
55c79a40 MG	46
d2de0582 SN	47	void __iomem *da8xx_syscfg0_base;
d2de0582 SN	48	void __iomem *da8xx_syscfg1_base;
6a28adef	49
55c79a40 MG	50	static struct plat_serial8250_port da8xx_serial_pdata[] = {
	51	{
	52	.mapbase = DA8XX_UART0_BASE,
	53	.irq = IRQ_DA8XX_UARTINT0,
	54	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	55	UPF_IOREMAP,
	56	.iotype = UPIO_MEM,
	57	.regshift = 2,
	58	},
	59	{
	60	.mapbase = DA8XX_UART1_BASE,
	61	.irq = IRQ_DA8XX_UARTINT1,
	62	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	63	UPF_IOREMAP,
	64	.iotype = UPIO_MEM,
	65	.regshift = 2,
	66	},
	67	{
	68	.mapbase = DA8XX_UART2_BASE,
	69	.irq = IRQ_DA8XX_UARTINT2,
	70	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	71	UPF_IOREMAP,
	72	.iotype = UPIO_MEM,
	73	.regshift = 2,
	74	},
	75	{
	76	.flags = 0,
	77	},
	78	};
	79
	80	struct platform_device da8xx_serial_device = {
	81	.name = "serial8250",
	82	.id = PLAT8250_DEV_PLATFORM,
	83	.dev = {
	84	.platform_data = da8xx_serial_pdata,
	85	},
	86	};
	87
55c79a40 MG	88	static const s8 da8xx_queue_tc_mapping[][2] = {
	89	/* {event queue no, TC no} */
	90	{0, 0},
	91	{1, 1},
	92	{-1, -1}
	93	};
	94
	95	static const s8 da8xx_queue_priority_mapping[][2] = {
	96	/* {event queue no, Priority} */
	97	{0, 3},
	98	{1, 7},
	99	{-1, -1}
	100	};
	101
3f995f2f SR	102	static const s8 da850_queue_tc_mapping[][2] = {
	103	/* {event queue no, TC no} */
	104	{0, 0},
	105	{-1, -1}
	106	};
	107
	108	static const s8 da850_queue_priority_mapping[][2] = {
	109	/* {event queue no, Priority} */
	110	{0, 3},
	111	{-1, -1}
	112	};
	113
bc3ac9f3 SN	114	static struct edma_soc_info da830_edma_cc0_info = {
	115	.n_channel = 32,
	116	.n_region = 4,
	117	.n_slot = 128,
	118	.n_tc = 2,
	119	.n_cc = 1,
	120	.queue_tc_mapping = da8xx_queue_tc_mapping,
	121	.queue_priority_mapping = da8xx_queue_priority_mapping,
	122	};
	123
	124	static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
	125	&da830_edma_cc0_info,
55c79a40 MG	126	};
55c79a40 MG	127
bc3ac9f3	128	static struct edma_soc_info da850_edma_cc_info[] = {
3f995f2f SR	129	{
	130	.n_channel = 32,
	131	.n_region = 4,
	132	.n_slot = 128,
	133	.n_tc = 2,
	134	.n_cc = 1,
	135	.queue_tc_mapping = da8xx_queue_tc_mapping,
	136	.queue_priority_mapping = da8xx_queue_priority_mapping,
	137	},
	138	{
	139	.n_channel = 32,
	140	.n_region = 4,
	141	.n_slot = 128,
	142	.n_tc = 1,
	143	.n_cc = 1,
	144	.queue_tc_mapping = da850_queue_tc_mapping,
	145	.queue_priority_mapping = da850_queue_priority_mapping,
	146	},
	147	};
	148
bc3ac9f3 SN	149	static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
	150	&da850_edma_cc_info[0],
	151	&da850_edma_cc_info[1],
	152	};
	153
3f995f2f	154	static struct resource da830_edma_resources[] = {
55c79a40 MG	155	{
	156	.name = "edma_cc0",
	157	.start = DA8XX_TPCC_BASE,
	158	.end = DA8XX_TPCC_BASE + SZ_32K - 1,
	159	.flags = IORESOURCE_MEM,
	160	},
	161	{
	162	.name = "edma_tc0",
	163	.start = DA8XX_TPTC0_BASE,
	164	.end = DA8XX_TPTC0_BASE + SZ_1K - 1,
	165	.flags = IORESOURCE_MEM,
	166	},
	167	{
	168	.name = "edma_tc1",
	169	.start = DA8XX_TPTC1_BASE,
	170	.end = DA8XX_TPTC1_BASE + SZ_1K - 1,
	171	.flags = IORESOURCE_MEM,
	172	},
	173	{
	174	.name = "edma0",
2259bbd4	175	.start = IRQ_DA8XX_CCINT0,
55c79a40 MG	176	.flags = IORESOURCE_IRQ,
	177	},
	178	{
	179	.name = "edma0_err",
	180	.start = IRQ_DA8XX_CCERRINT,
	181	.flags = IORESOURCE_IRQ,
	182	},
	183	};
	184
3f995f2f SR	185	static struct resource da850_edma_resources[] = {
	186	{
	187	.name = "edma_cc0",
	188	.start = DA8XX_TPCC_BASE,
	189	.end = DA8XX_TPCC_BASE + SZ_32K - 1,
	190	.flags = IORESOURCE_MEM,
	191	},
	192	{
	193	.name = "edma_tc0",
	194	.start = DA8XX_TPTC0_BASE,
	195	.end = DA8XX_TPTC0_BASE + SZ_1K - 1,
	196	.flags = IORESOURCE_MEM,
	197	},
	198	{
	199	.name = "edma_tc1",
	200	.start = DA8XX_TPTC1_BASE,
	201	.end = DA8XX_TPTC1_BASE + SZ_1K - 1,
	202	.flags = IORESOURCE_MEM,
	203	},
	204	{
	205	.name = "edma_cc1",
	206	.start = DA850_TPCC1_BASE,
	207	.end = DA850_TPCC1_BASE + SZ_32K - 1,
	208	.flags = IORESOURCE_MEM,
	209	},
	210	{
	211	.name = "edma_tc2",
	212	.start = DA850_TPTC2_BASE,
	213	.end = DA850_TPTC2_BASE + SZ_1K - 1,
	214	.flags = IORESOURCE_MEM,
	215	},
	216	{
	217	.name = "edma0",
	218	.start = IRQ_DA8XX_CCINT0,
	219	.flags = IORESOURCE_IRQ,
	220	},
	221	{
	222	.name = "edma0_err",
	223	.start = IRQ_DA8XX_CCERRINT,
	224	.flags = IORESOURCE_IRQ,
	225	},
	226	{
	227	.name = "edma1",
	228	.start = IRQ_DA850_CCINT1,
	229	.flags = IORESOURCE_IRQ,
	230	},
	231	{
	232	.name = "edma1_err",
	233	.start = IRQ_DA850_CCERRINT1,
	234	.flags = IORESOURCE_IRQ,
	235	},
	236	};
	237
	238	static struct platform_device da830_edma_device = {
55c79a40 MG	239	.name = "edma",
	240	.id = -1,
	241	.dev = {
3f995f2f	242	.platform_data = da830_edma_info,
55c79a40	243	},
3f995f2f SR	244	.num_resources = ARRAY_SIZE(da830_edma_resources),
	245	.resource = da830_edma_resources,
	246	};
	247
	248	static struct platform_device da850_edma_device = {
	249	.name = "edma",
	250	.id = -1,
	251	.dev = {
	252	.platform_data = da850_edma_info,
	253	},
	254	.num_resources = ARRAY_SIZE(da850_edma_resources),
	255	.resource = da850_edma_resources,
55c79a40 MG	256	};
55c79a40 MG	257
a941c503	258	int __init da830_register_edma(struct edma_rsv_info *rsv)
55c79a40	259	{
a941c503	260	da830_edma_cc0_info.rsv = rsv;
3f995f2f	261
a941c503 RS	262	return platform_device_register(&da830_edma_device);
	263	}
	264
	265	int __init da850_register_edma(struct edma_rsv_info *rsv[2])
	266	{
	267	if (rsv) {
	268	da850_edma_cc_info[0].rsv = rsv[0];
	269	da850_edma_cc_info[1].rsv = rsv[1];
	270	}
3f995f2f	271
a941c503	272	return platform_device_register(&da850_edma_device);
55c79a40 MG	273	}
	274
	275	static struct resource da8xx_i2c_resources0[] = {
	276	{
	277	.start = DA8XX_I2C0_BASE,
	278	.end = DA8XX_I2C0_BASE + SZ_4K - 1,
	279	.flags = IORESOURCE_MEM,
	280	},
	281	{
	282	.start = IRQ_DA8XX_I2CINT0,
	283	.end = IRQ_DA8XX_I2CINT0,
	284	.flags = IORESOURCE_IRQ,
	285	},
	286	};
	287
	288	static struct platform_device da8xx_i2c_device0 = {
	289	.name = "i2c_davinci",
	290	.id = 1,
	291	.num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
	292	.resource = da8xx_i2c_resources0,
	293	};
	294
	295	static struct resource da8xx_i2c_resources1[] = {
	296	{
	297	.start = DA8XX_I2C1_BASE,
	298	.end = DA8XX_I2C1_BASE + SZ_4K - 1,
	299	.flags = IORESOURCE_MEM,
	300	},
	301	{
	302	.start = IRQ_DA8XX_I2CINT1,
	303	.end = IRQ_DA8XX_I2CINT1,
	304	.flags = IORESOURCE_IRQ,
	305	},
	306	};
	307
	308	static struct platform_device da8xx_i2c_device1 = {
	309	.name = "i2c_davinci",
	310	.id = 2,
	311	.num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
	312	.resource = da8xx_i2c_resources1,
	313	};
	314
	315	int __init da8xx_register_i2c(int instance,
	316	struct davinci_i2c_platform_data *pdata)
	317	{
	318	struct platform_device *pdev;
	319
	320	if (instance == 0)
	321	pdev = &da8xx_i2c_device0;
	322	else if (instance == 1)
	323	pdev = &da8xx_i2c_device1;
	324	else
	325	return -EINVAL;
	326
	327	pdev->dev.platform_data = pdata;
	328	return platform_device_register(pdev);
	329	}
	330
	331	static struct resource da8xx_watchdog_resources[] = {
	332	{
	333	.start = DA8XX_WDOG_BASE,
	334	.end = DA8XX_WDOG_BASE + SZ_4K - 1,
	335	.flags = IORESOURCE_MEM,
	336	},
337	};
338
c78a5bc2	339	struct platform_device da8xx_wdt_device = {
55c79a40 MG	340	.name = "watchdog",
	341	.id = -1,
	342	.num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
	343	.resource = da8xx_watchdog_resources,
	344	};
	345
	346	int __init da8xx_register_watchdog(void)
	347	{
c78a5bc2	348	return platform_device_register(&da8xx_wdt_device);
55c79a40 MG	349	}
	350
	351	static struct resource da8xx_emac_resources[] = {
	352	{
	353	.start = DA8XX_EMAC_CPPI_PORT_BASE,
d22960c8	354	.end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
55c79a40 MG	355	.flags = IORESOURCE_MEM,
	356	},
	357	{
	358	.start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
	359	.end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
	360	.flags = IORESOURCE_IRQ,
	361	},
	362	{
	363	.start = IRQ_DA8XX_C0_RX_PULSE,
	364	.end = IRQ_DA8XX_C0_RX_PULSE,
	365	.flags = IORESOURCE_IRQ,
	366	},
	367	{
	368	.start = IRQ_DA8XX_C0_TX_PULSE,
	369	.end = IRQ_DA8XX_C0_TX_PULSE,
	370	.flags = IORESOURCE_IRQ,
	371	},
	372	{
	373	.start = IRQ_DA8XX_C0_MISC_PULSE,
	374	.end = IRQ_DA8XX_C0_MISC_PULSE,
	375	.flags = IORESOURCE_IRQ,
	376	},
	377	};
	378
	379	struct emac_platform_data da8xx_emac_pdata = {
	380	.ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
	381	.ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
	382	.ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
55c79a40 MG	383	.ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
	384	.version = EMAC_VERSION_2,
	385	};
	386
	387	static struct platform_device da8xx_emac_device = {
	388	.name = "davinci_emac",
	389	.id = 1,
	390	.dev = {
	391	.platform_data = &da8xx_emac_pdata,
	392	},
	393	.num_resources = ARRAY_SIZE(da8xx_emac_resources),
	394	.resource = da8xx_emac_resources,
	395	};
	396
d22960c8 CC	397	static struct resource da8xx_mdio_resources[] = {
	398	{
	399	.start = DA8XX_EMAC_MDIO_BASE,
	400	.end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
	401	.flags = IORESOURCE_MEM,
	402	},
	403	};
	404
	405	static struct platform_device da8xx_mdio_device = {
	406	.name = "davinci_mdio",
	407	.id = 0,
	408	.num_resources = ARRAY_SIZE(da8xx_mdio_resources),
	409	.resource = da8xx_mdio_resources,
	410	};
	411
31f53cf3 MG	412	int __init da8xx_register_emac(void)
31f53cf3 MG	413	{
d22960c8 CC	414	int ret;
	415
	416	ret = platform_device_register(&da8xx_mdio_device);
	417	if (ret < 0)
	418	return ret;
	419	ret = platform_device_register(&da8xx_emac_device);
	420	if (ret < 0)
	421	return ret;
	422	ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
	423	NULL, &da8xx_emac_device.dev);
	424	return ret;
31f53cf3 MG	425	}
31f53cf3 MG	426
e33ef5e3 C	427	static struct resource da830_mcasp1_resources[] = {
	428	{
	429	.name = "mcasp1",
	430	.start = DAVINCI_DA830_MCASP1_REG_BASE,
	431	.end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
	432	.flags = IORESOURCE_MEM,
	433	},
	434	/* TX event */
	435	{
	436	.start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
	437	.end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
	438	.flags = IORESOURCE_DMA,
	439	},
	440	/* RX event */
	441	{
	442	.start = DAVINCI_DA830_DMA_MCASP1_AREVT,
	443	.end = DAVINCI_DA830_DMA_MCASP1_AREVT,
	444	.flags = IORESOURCE_DMA,
	445	},
	446	};
	447
	448	static struct platform_device da830_mcasp1_device = {
	449	.name = "davinci-mcasp",
	450	.id = 1,
	451	.num_resources = ARRAY_SIZE(da830_mcasp1_resources),
	452	.resource = da830_mcasp1_resources,
	453	};
	454
491214e1 C	455	static struct resource da850_mcasp_resources[] = {
	456	{
	457	.name = "mcasp",
	458	.start = DAVINCI_DA8XX_MCASP0_REG_BASE,
	459	.end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
	460	.flags = IORESOURCE_MEM,
	461	},
	462	/* TX event */
	463	{
	464	.start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
	465	.end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
	466	.flags = IORESOURCE_DMA,
	467	},
	468	/* RX event */
	469	{
	470	.start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
	471	.end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
	472	.flags = IORESOURCE_DMA,
	473	},
	474	};
	475
	476	static struct platform_device da850_mcasp_device = {
	477	.name = "davinci-mcasp",
	478	.id = 0,
	479	.num_resources = ARRAY_SIZE(da850_mcasp_resources),
	480	.resource = da850_mcasp_resources,
	481	};
	482
b8864aa4	483	void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
e33ef5e3	484	{
491214e1 C	485	/* DA830/OMAP-L137 has 3 instances of McASP */
491214e1 C	486	if (cpu_is_davinci_da830() && id == 1) {
e33ef5e3 C	487	da830_mcasp1_device.dev.platform_data = pdata;
e33ef5e3 C	488	platform_device_register(&da830_mcasp1_device);
491214e1 C	489	} else if (cpu_is_davinci_da850()) {
	490	da850_mcasp_device.dev.platform_data = pdata;
	491	platform_device_register(&da850_mcasp_device);
e33ef5e3 C	492	}
e33ef5e3 C	493	}
5cbdf276 SR	494
	495	static const struct display_panel disp_panel = {
	496	QVGA,
	497	16,
	498	16,
	499	COLOR_ACTIVE,
	500	};
	501
	502	static struct lcd_ctrl_config lcd_cfg = {
	503	&disp_panel,
	504	.ac_bias = 255,
	505	.ac_bias_intrpt = 0,
	506	.dma_burst_sz = 16,
	507	.bpp = 16,
	508	.fdd = 255,
	509	.tft_alt_mode = 0,
	510	.stn_565_mode = 0,
	511	.mono_8bit_mode = 0,
	512	.invert_line_clock = 1,
	513	.invert_frm_clock = 1,
	514	.sync_edge = 0,
	515	.sync_ctrl = 1,
	516	.raster_order = 0,
	517	};
	518
b9e6342b MG	519	struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
	520	.manu_name = "sharp",
	521	.controller_data = &lcd_cfg,
	522	.type = "Sharp_LCD035Q3DG01",
	523	};
	524
	525	struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
	526	.manu_name = "sharp",
	527	.controller_data = &lcd_cfg,
	528	.type = "Sharp_LK043T1DG01",
5cbdf276 SR	529	};
	530
	531	static struct resource da8xx_lcdc_resources[] = {
	532	[0] = { /* registers */
	533	.start = DA8XX_LCD_CNTRL_BASE,
	534	.end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
	535	.flags = IORESOURCE_MEM,
	536	},
	537	[1] = { /* interrupt */
	538	.start = IRQ_DA8XX_LCDINT,
	539	.end = IRQ_DA8XX_LCDINT,
	540	.flags = IORESOURCE_IRQ,
	541	},
	542	};
	543
b9e6342b	544	static struct platform_device da8xx_lcdc_device = {
5cbdf276 SR	545	.name = "da8xx_lcdc",
	546	.id = 0,
	547	.num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
	548	.resource = da8xx_lcdc_resources,
5cbdf276 SR	549	};
5cbdf276 SR	550
b9e6342b	551	int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
5cbdf276	552	{
b9e6342b MG	553	da8xx_lcdc_device.dev.platform_data = pdata;
b9e6342b MG	554	return platform_device_register(&da8xx_lcdc_device);
5cbdf276	555	}
700691f2 SR	556
	557	static struct resource da8xx_mmcsd0_resources[] = {
	558	{ /* registers */
	559	.start = DA8XX_MMCSD0_BASE,
	560	.end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
	561	.flags = IORESOURCE_MEM,
	562	},
	563	{ /* interrupt */
	564	.start = IRQ_DA8XX_MMCSDINT0,
	565	.end = IRQ_DA8XX_MMCSDINT0,
	566	.flags = IORESOURCE_IRQ,
	567	},
	568	{ /* DMA RX */
	569	.start = EDMA_CTLR_CHAN(0, 16),
	570	.end = EDMA_CTLR_CHAN(0, 16),
	571	.flags = IORESOURCE_DMA,
	572	},
	573	{ /* DMA TX */
	574	.start = EDMA_CTLR_CHAN(0, 17),
	575	.end = EDMA_CTLR_CHAN(0, 17),
	576	.flags = IORESOURCE_DMA,
	577	},
	578	};
	579
	580	static struct platform_device da8xx_mmcsd0_device = {
	581	.name = "davinci_mmc",
	582	.id = 0,
	583	.num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
	584	.resource = da8xx_mmcsd0_resources,
	585	};
	586
	587	int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
	588	{
	589	da8xx_mmcsd0_device.dev.platform_data = config;
	590	return platform_device_register(&da8xx_mmcsd0_device);
	591	}
c51df70b	592
b8241aef JK	593	#ifdef CONFIG_ARCH_DAVINCI_DA850
	594	static struct resource da850_mmcsd1_resources[] = {
	595	{ /* registers */
	596	.start = DA850_MMCSD1_BASE,
	597	.end = DA850_MMCSD1_BASE + SZ_4K - 1,
	598	.flags = IORESOURCE_MEM,
	599	},
	600	{ /* interrupt */
	601	.start = IRQ_DA850_MMCSDINT0_1,
	602	.end = IRQ_DA850_MMCSDINT0_1,
	603	.flags = IORESOURCE_IRQ,
	604	},
	605	{ /* DMA RX */
	606	.start = EDMA_CTLR_CHAN(1, 28),
	607	.end = EDMA_CTLR_CHAN(1, 28),
	608	.flags = IORESOURCE_DMA,
	609	},
	610	{ /* DMA TX */
	611	.start = EDMA_CTLR_CHAN(1, 29),
	612	.end = EDMA_CTLR_CHAN(1, 29),
	613	.flags = IORESOURCE_DMA,
	614	},
	615	};
	616
	617	static struct platform_device da850_mmcsd1_device = {
	618	.name = "davinci_mmc",
	619	.id = 1,
	620	.num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
	621	.resource = da850_mmcsd1_resources,
	622	};
	623
	624	int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
	625	{
	626	da850_mmcsd1_device.dev.platform_data = config;
	627	return platform_device_register(&da850_mmcsd1_device);
	628	}
	629	#endif
	630
c51df70b MG	631	static struct resource da8xx_rtc_resources[] = {
	632	{
	633	.start = DA8XX_RTC_BASE,
	634	.end = DA8XX_RTC_BASE + SZ_4K - 1,
	635	.flags = IORESOURCE_MEM,
	636	},
	637	{ /* timer irq */
	638	.start = IRQ_DA8XX_RTC,
	639	.end = IRQ_DA8XX_RTC,
	640	.flags = IORESOURCE_IRQ,
	641	},
	642	{ /* alarm irq */
	643	.start = IRQ_DA8XX_RTC,
	644	.end = IRQ_DA8XX_RTC,
	645	.flags = IORESOURCE_IRQ,
	646	},
	647	};
	648
	649	static struct platform_device da8xx_rtc_device = {
	650	.name = "omap_rtc",
	651	.id = -1,
	652	.num_resources = ARRAY_SIZE(da8xx_rtc_resources),
	653	.resource = da8xx_rtc_resources,
	654	};
	655
	656	int da8xx_register_rtc(void)
	657	{
75c99bb0	658	int ret;
db6db5d8 CC	659	void __iomem *base;
	660
	661	base = ioremap(DA8XX_RTC_BASE, SZ_4K);
	662	if (WARN_ON(!base))
	663	return -ENOMEM;
75c99bb0	664
c51df70b	665	/* Unlock the rtc's registers */
db6db5d8 CC	666	__raw_writel(0x83e70b13, base + 0x6c);
	667	__raw_writel(0x95a4f1e0, base + 0x70);
	668
	669	iounmap(base);
c51df70b	670
75c99bb0 SN	671	ret = platform_device_register(&da8xx_rtc_device);
	672	if (!ret)
	673	/* Atleast on DA850, RTC is a wakeup source */
	674	device_init_wakeup(&da8xx_rtc_device.dev, true);
	675
	676	return ret;
c51df70b	677	}
1960e693	678
948c66df SN	679	static void __iomem *da8xx_ddr2_ctlr_base;
	680	void __iomem * __init da8xx_get_mem_ctlr(void)
	681	{
	682	if (da8xx_ddr2_ctlr_base)
	683	return da8xx_ddr2_ctlr_base;
	684
	685	da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
	686	if (!da8xx_ddr2_ctlr_base)
	687	pr_warning("%s: Unable to map DDR2 controller", __func__);
	688
	689	return da8xx_ddr2_ctlr_base;
	690	}
	691
1960e693 SN	692	static struct resource da8xx_cpuidle_resources[] = {
	693	{
	694	.start = DA8XX_DDR2_CTL_BASE,
	695	.end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
	696	.flags = IORESOURCE_MEM,
	697	},
	698	};
	699
	700	/* DA8XX devices support DDR2 power down */
	701	static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
	702	.ddr2_pdown = 1,
	703	};
	704
	705
	706	static struct platform_device da8xx_cpuidle_device = {
	707	.name = "cpuidle-davinci",
	708	.num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
	709	.resource = da8xx_cpuidle_resources,
	710	.dev = {
	711	.platform_data = &da8xx_cpuidle_pdata,
	712	},
	713	};
	714
	715	int __init da8xx_register_cpuidle(void)
	716	{
948c66df SN	717	da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
948c66df SN	718
1960e693 SN	719	return platform_device_register(&da8xx_cpuidle_device);
1960e693 SN	720	}