[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-bcmring / core.c

/*
 *  derived from linux/arch/arm/mach-versatile/core.c
 *  linux/arch/arm/mach-bcmring/core.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
/* Portions copyright Broadcom 2008 */

#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>

#include <linux/amba/bus.h>
#include <mach/csp/mm_addr.h>
#include <mach/hardware.h>
#include <asm/clkdev.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/hardware/arm_timer.h>
#include <asm/mach-types.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <asm/mach/mmc.h>

#include <cfg_global.h>

#include "clock.h"

#include <csp/secHw.h>
#include <mach/csp/secHw_def.h>
#include <mach/csp/chipcHw_inline.h>
#include <mach/csp/tmrHw_reg.h>

#define AMBA_DEVICE(name, initname, base, plat, size)       \
static struct amba_device name##_device = {     \
   .dev = {                                     \
      .coherent_dma_mask = ~0,                  \
      .init_name = initname,                    \
      .platform_data = plat                     \
   },                                           \
   .res = {                                     \
      .start = MM_ADDR_IO_##base,               \
		.end = MM_ADDR_IO_##base + (size) - 1,    \
      .flags = IORESOURCE_MEM                   \
   },                                           \
   .dma_mask = ~0,                              \
   .irq = {                                     \
      IRQ_##base                                \
   }                                            \
}


AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);

static struct clk pll1_clk = {
	.name = "PLL1",
	.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
	.rate_hz = 2000000000,
	.use_cnt = 7,
};

static struct clk uart_clk = {
	.name = "UART",
	.type = CLK_TYPE_PROGRAMMABLE,
	.csp_id = chipcHw_CLOCK_UART,
	.rate_hz = HW_CFG_UART_CLK_HZ,
	.parent = &pll1_clk,
};

static struct clk_lookup lookups[] = {
	{			/* UART0 */
	 .dev_id = "uarta",
	 .clk = &uart_clk,
	 }, {			/* UART1 */
	     .dev_id = "uartb",
	     .clk = &uart_clk,
	     }
};

static struct amba_device *amba_devs[] __initdata = {
	&uartA_device,
	&uartB_device,
};

void __init bcmring_amba_init(void)
{
	int i;
	u32 bus_clock;

/* Linux is run initially in non-secure mode. Secure peripherals */
/* generate FIQ, and must be handled in secure mode. Until we have */
/* a linux security monitor implementation, keep everything in */
/* non-secure mode. */
	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
	secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
			  secHw_BLK_MASK_KEY_SCAN |
			  secHw_BLK_MASK_TOUCH_SCREEN |
			  secHw_BLK_MASK_UART0 |
			  secHw_BLK_MASK_UART1 |
			  secHw_BLK_MASK_WATCHDOG |
			  secHw_BLK_MASK_SPUM |
			  secHw_BLK_MASK_DDR2 |
			  secHw_BLK_MASK_SPU |
			  secHw_BLK_MASK_PKA |
			  secHw_BLK_MASK_RNG |
			  secHw_BLK_MASK_RTC |
			  secHw_BLK_MASK_OTP |
			  secHw_BLK_MASK_BOOT |
			  secHw_BLK_MASK_MPU |
			  secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);

	/* Only the devices attached to the AMBA bus are enabled just before the bus is */
	/* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
	/* driver to access these blocks. The bus is probed, and the drivers are loaded. */
	/* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
	bus_clock = chipcHw_REG_BUS_CLOCK_GE
	    | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;

	chipcHw_busInterfaceClockEnable(bus_clock);

	for (i = 0; i < ARRAY_SIZE(lookups); i++)
		clkdev_add(&lookups[i]);

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}
}

/*
 * Where is the timer (VA)?
 */
#define TIMER0_VA_BASE		 MM_IO_BASE_TMR
#define TIMER1_VA_BASE		(MM_IO_BASE_TMR + 0x20)
#define TIMER2_VA_BASE		(MM_IO_BASE_TMR + 0x40)
#define TIMER3_VA_BASE          (MM_IO_BASE_TMR + 0x60)

/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
#if defined(CONFIG_ARCH_FPGA11107)
/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
/* slow down Linux's sense of time */
#define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
#define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
#define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
#define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
#else
#define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
#define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
#define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
#define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
#endif

#define TICKS_PER_uSEC     TIMER0_FREQUENCY_MHZ

/*
 *  These are useconds NOT ticks.
 *
 */
#define mSEC_1                          1000
#define mSEC_5                          (mSEC_1 * 5)
#define mSEC_10                         (mSEC_1 * 10)
#define mSEC_25                         (mSEC_1 * 25)
#define SEC_1                           (mSEC_1 * 1000)

/*
 * How long is the timer interval?
 */
#define TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_10)
#if TIMER_INTERVAL >= 0x100000
#define TIMER_RELOAD	(TIMER_INTERVAL >> 8)
#define TIMER_DIVISOR	(TIMER_CTRL_DIV256)
#define TICKS2USECS(x)	(256 * (x) / TICKS_PER_uSEC)
#elif TIMER_INTERVAL >= 0x10000
#define TIMER_RELOAD	(TIMER_INTERVAL >> 4)	/* Divide by 16 */
#define TIMER_DIVISOR	(TIMER_CTRL_DIV16)
#define TICKS2USECS(x)	(16 * (x) / TICKS_PER_uSEC)
#else
#define TIMER_RELOAD	(TIMER_INTERVAL)
#define TIMER_DIVISOR	(TIMER_CTRL_DIV1)
#define TICKS2USECS(x)	((x) / TICKS_PER_uSEC)
#endif

static void timer_set_mode(enum clock_event_mode mode,
			   struct clock_event_device *clk)
{
	unsigned long ctrl;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);

		ctrl = TIMER_CTRL_PERIODIC;
		ctrl |=
		    TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
		    TIMER_CTRL_ENABLE;
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* period set, and timer enabled in 'next_event' hook */
		ctrl = TIMER_CTRL_ONESHOT;
		ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		ctrl = 0;
	}

	writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
}

static int timer_set_next_event(unsigned long evt,
				struct clock_event_device *unused)
{
	unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);

	writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);

	return 0;
}

static struct clock_event_device timer0_clockevent = {
	.name = "timer0",
	.shift = 32,
	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode = timer_set_mode,
	.set_next_event = timer_set_next_event,
};

/*
 * IRQ handler for the timer
 */
static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &timer0_clockevent;

	writel(1, TIMER0_VA_BASE + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction bcmring_timer_irq = {
	.name = "bcmring Timer Tick",
	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler = bcmring_timer_interrupt,
};

static cycle_t bcmring_get_cycles_timer1(void)
{
	return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
}

static cycle_t bcmring_get_cycles_timer3(void)
{
	return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
}

static struct clocksource clocksource_bcmring_timer1 = {
	.name = "timer1",
	.rating = 200,
	.read = bcmring_get_cycles_timer1,
	.mask = CLOCKSOURCE_MASK(32),
	.shift = 20,
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};

static struct clocksource clocksource_bcmring_timer3 = {
	.name = "timer3",
	.rating = 100,
	.read = bcmring_get_cycles_timer3,
	.mask = CLOCKSOURCE_MASK(32),
	.shift = 20,
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};

static int __init bcmring_clocksource_init(void)
{
	/* setup timer1 as free-running clocksource */
	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
	writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
	       TIMER1_VA_BASE + TIMER_CTRL);

	clocksource_bcmring_timer1.mult =
	    clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000,
				 clocksource_bcmring_timer1.shift);
	clocksource_register(&clocksource_bcmring_timer1);

	/* setup timer3 as free-running clocksource */
	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
	writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
	writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
	       TIMER3_VA_BASE + TIMER_CTRL);

	clocksource_bcmring_timer3.mult =
	    clocksource_khz2mult(TIMER3_FREQUENCY_KHZ,
				 clocksource_bcmring_timer3.shift);
	clocksource_register(&clocksource_bcmring_timer3);

	return 0;
}

/*
 * Set up timer interrupt, and return the current time in seconds.
 */
void __init bcmring_init_timer(void)
{
	printk(KERN_INFO "bcmring_init_timer\n");
	/*
	 * Initialise to a known state (all timers off)
	 */
	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
	writel(0, TIMER3_VA_BASE + TIMER_CTRL);

	/*
	 * Make irqs happen for the system timer
	 */
	setup_irq(IRQ_TIMER0, &bcmring_timer_irq);

	bcmring_clocksource_init();

	timer0_clockevent.mult =
	    div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
	timer0_clockevent.max_delta_ns =
	    clockevent_delta2ns(0xffffffff, &timer0_clockevent);
	timer0_clockevent.min_delta_ns =
	    clockevent_delta2ns(0xf, &timer0_clockevent);

	timer0_clockevent.cpumask = cpumask_of(0);
	clockevents_register_device(&timer0_clockevent);
}

struct sys_timer bcmring_timer = {
	.init = bcmring_init_timer,
};
Commit	Line	Data
278a6752 LC	1	/*
	2	* derived from linux/arch/arm/mach-versatile/core.c
	3	* linux/arch/arm/mach-bcmring/core.c
	4	*
	5	* Copyright (C) 1999 - 2003 ARM Limited
	6	* Copyright (C) 2000 Deep Blue Solutions Ltd
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
	22	/* Portions copyright Broadcom 2008 */
	23
	24	#include <linux/init.h>
	25	#include <linux/device.h>
	26	#include <linux/dma-mapping.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/sysdev.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/amba/bus.h>
	31	#include <linux/clocksource.h>
	32	#include <linux/clockchips.h>
	33
	34	#include <linux/amba/bus.h>
	35	#include <mach/csp/mm_addr.h>
	36	#include <mach/hardware.h>
	37	#include <asm/clkdev.h>
	38	#include <linux/io.h>
	39	#include <asm/irq.h>
	40	#include <asm/hardware/arm_timer.h>
	41	#include <asm/mach-types.h>
	42
	43	#include <asm/mach/arch.h>
	44	#include <asm/mach/flash.h>
	45	#include <asm/mach/irq.h>
	46	#include <asm/mach/time.h>
	47	#include <asm/mach/map.h>
	48	#include <asm/mach/mmc.h>
	49
	50	#include <cfg_global.h>
	51
	52	#include "clock.h"
	53
	54	#include <csp/secHw.h>
	55	#include <mach/csp/secHw_def.h>
	56	#include <mach/csp/chipcHw_inline.h>
	57	#include <mach/csp/tmrHw_reg.h>
	58
	59	#define AMBA_DEVICE(name, initname, base, plat, size) \
	60	static struct amba_device name##_device = { \
	61	.dev = { \
	62	.coherent_dma_mask = ~0, \
	63	.init_name = initname, \
	64	.platform_data = plat \
65	}, \
66	.res = { \
67	.start = MM_ADDR_IO_##base, \
68	.end = MM_ADDR_IO_##base + (size) - 1, \
69	.flags = IORESOURCE_MEM \
70	}, \
71	.dma_mask = ~0, \
72	.irq = { \
73	IRQ_##base \
74	} \
75	}
76
77
78	AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
79	AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
80
81	static struct clk pll1_clk = {
82	.name = "PLL1",
83	.type = CLK_TYPE_PRIMARY \| CLK_TYPE_PLL1,
84	.rate_hz = 2000000000,
85	.use_cnt = 7,
86	};
87
88	static struct clk uart_clk = {
89	.name = "UART",
90	.type = CLK_TYPE_PROGRAMMABLE,
91	.csp_id = chipcHw_CLOCK_UART,
92	.rate_hz = HW_CFG_UART_CLK_HZ,
93	.parent = &pll1_clk,
94	};
95
96	static struct clk_lookup lookups[] = {
97	{ /* UART0 */
98	.dev_id = "uarta",
99	.clk = &uart_clk,
100	}, { /* UART1 */
101	.dev_id = "uartb",
102	.clk = &uart_clk,
103	}
104	};
105
106	static struct amba_device *amba_devs[] __initdata = {
107	&uartA_device,
108	&uartB_device,
109	};
110
111	void __init bcmring_amba_init(void)
112	{
113	int i;
114	u32 bus_clock;
115
116	/* Linux is run initially in non-secure mode. Secure peripherals */
117	/* generate FIQ, and must be handled in secure mode. Until we have */
118	/* a linux security monitor implementation, keep everything in */
119	/* non-secure mode. */
120	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
121	secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL \|
122	secHw_BLK_MASK_KEY_SCAN \|
123	secHw_BLK_MASK_TOUCH_SCREEN \|
124	secHw_BLK_MASK_UART0 \|
125	secHw_BLK_MASK_UART1 \|
126	secHw_BLK_MASK_WATCHDOG \|
127	secHw_BLK_MASK_SPUM \|
128	secHw_BLK_MASK_DDR2 \|
129	secHw_BLK_MASK_SPU \|
130	secHw_BLK_MASK_PKA \|
131	secHw_BLK_MASK_RNG \|
132	secHw_BLK_MASK_RTC \|
133	secHw_BLK_MASK_OTP \|
134	secHw_BLK_MASK_BOOT \|
135	secHw_BLK_MASK_MPU \|
136	secHw_BLK_MASK_TZCTRL \| secHw_BLK_MASK_INTR);
137
138	/* Only the devices attached to the AMBA bus are enabled just before the bus is */
139	/* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
140	/* driver to access these blocks. The bus is probed, and the drivers are loaded. */
141	/* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
142	bus_clock = chipcHw_REG_BUS_CLOCK_GE
143	\| chipcHw_REG_BUS_CLOCK_SDIO0 \| chipcHw_REG_BUS_CLOCK_SDIO1;
144
145	chipcHw_busInterfaceClockEnable(bus_clock);
146
147	for (i = 0; i < ARRAY_SIZE(lookups); i++)
148	clkdev_add(&lookups[i]);
149
150	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
151	struct amba_device *d = amba_devs[i];
152	amba_device_register(d, &iomem_resource);
153	}
154	}
155
156	/*
157	* Where is the timer (VA)?
158	*/
159	#define TIMER0_VA_BASE MM_IO_BASE_TMR
160	#define TIMER1_VA_BASE (MM_IO_BASE_TMR + 0x20)
161	#define TIMER2_VA_BASE (MM_IO_BASE_TMR + 0x40)
162	#define TIMER3_VA_BASE (MM_IO_BASE_TMR + 0x60)
163
164	/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
165	#if defined(CONFIG_ARCH_FPGA11107)
166	/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
167	/* slow down Linux's sense of time */
168	#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
169	#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
170	#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
171	#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
172	#else
173	#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
174	#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
175	#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
176	#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
177	#endif
178
179	#define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ
180
181	/*
182	* These are useconds NOT ticks.
183	*
184	*/
185	#define mSEC_1 1000
186	#define mSEC_5 (mSEC_1 * 5)
187	#define mSEC_10 (mSEC_1 * 10)
188	#define mSEC_25 (mSEC_1 * 25)
189	#define SEC_1 (mSEC_1 * 1000)
190
191	/*
192	* How long is the timer interval?
193	*/
194	#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
195	#if TIMER_INTERVAL >= 0x100000
196	#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
197	#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
198	#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
199	#elif TIMER_INTERVAL >= 0x10000
200	#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
201	#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
202	#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
203	#else
204	#define TIMER_RELOAD (TIMER_INTERVAL)
205	#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
206	#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
207	#endif
208
209	static void timer_set_mode(enum clock_event_mode mode,
210	struct clock_event_device *clk)
211	{
212	unsigned long ctrl;
213
214	switch (mode) {
215	case CLOCK_EVT_MODE_PERIODIC:
216	writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
217
218	ctrl = TIMER_CTRL_PERIODIC;
219	ctrl \|=
220	TIMER_DIVISOR \| TIMER_CTRL_32BIT \| TIMER_CTRL_IE \|
221	TIMER_CTRL_ENABLE;
222	break;
223	case CLOCK_EVT_MODE_ONESHOT:
224	/* period set, and timer enabled in 'next_event' hook */
225	ctrl = TIMER_CTRL_ONESHOT;
226	ctrl \|= TIMER_DIVISOR \| TIMER_CTRL_32BIT \| TIMER_CTRL_IE;
227	break;
228	case CLOCK_EVT_MODE_UNUSED:
229	case CLOCK_EVT_MODE_SHUTDOWN:
230	default:
231	ctrl = 0;
232	}
233
234	writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
235	}
236
237	static int timer_set_next_event(unsigned long evt,
238	struct clock_event_device *unused)
239	{
240	unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
241
242	writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
243	writel(ctrl \| TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
244
245	return 0;
246	}
247
248	static struct clock_event_device timer0_clockevent = {
249	.name = "timer0",
250	.shift = 32,
251	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
252	.set_mode = timer_set_mode,
253	.set_next_event = timer_set_next_event,
254	};
255
256	/*
257	* IRQ handler for the timer
258	*/
259	static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
260	{
261	struct clock_event_device *evt = &timer0_clockevent;
262
263	writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
264
265	evt->event_handler(evt);
266
267	return IRQ_HANDLED;
268	}
269
270	static struct irqaction bcmring_timer_irq = {
271	.name = "bcmring Timer Tick",
272	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
273	.handler = bcmring_timer_interrupt,
274	};
275
276	static cycle_t bcmring_get_cycles_timer1(void)
277	{
278	return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
279	}
280
281	static cycle_t bcmring_get_cycles_timer3(void)
282	{
283	return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
284	}
285
286	static struct clocksource clocksource_bcmring_timer1 = {
287	.name = "timer1",
288	.rating = 200,
289	.read = bcmring_get_cycles_timer1,
290	.mask = CLOCKSOURCE_MASK(32),
291	.shift = 20,
292	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
293	};
294
295	static struct clocksource clocksource_bcmring_timer3 = {
296	.name = "timer3",
297	.rating = 100,
298	.read = bcmring_get_cycles_timer3,
299	.mask = CLOCKSOURCE_MASK(32),
300	.shift = 20,
301	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
302	};
303
304	static int __init bcmring_clocksource_init(void)
305	{
306	/* setup timer1 as free-running clocksource */
307	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
308	writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
309	writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
310	writel(TIMER_CTRL_32BIT \| TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC,
311	TIMER1_VA_BASE + TIMER_CTRL);
312
313	clocksource_bcmring_timer1.mult =
314	clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000,
315	clocksource_bcmring_timer1.shift);
316	clocksource_register(&clocksource_bcmring_timer1);
317
318	/* setup timer3 as free-running clocksource */
319	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
320	writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
321	writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
322	writel(TIMER_CTRL_32BIT \| TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC,
323	TIMER3_VA_BASE + TIMER_CTRL);
324
325	clocksource_bcmring_timer3.mult =
326	clocksource_khz2mult(TIMER3_FREQUENCY_KHZ,
327	clocksource_bcmring_timer3.shift);
328	clocksource_register(&clocksource_bcmring_timer3);
329
330	return 0;
331	}
332
333	/*
334	* Set up timer interrupt, and return the current time in seconds.
335	*/
336	void __init bcmring_init_timer(void)
337	{
338	printk(KERN_INFO "bcmring_init_timer\n");
339	/*
340	* Initialise to a known state (all timers off)
341	*/
342	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
343	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
344	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
345	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
346
347	/*
348	* Make irqs happen for the system timer
349	*/
350	setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
351
352	bcmring_clocksource_init();
353
354	timer0_clockevent.mult =
355	div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
356	timer0_clockevent.max_delta_ns =
357	clockevent_delta2ns(0xffffffff, &timer0_clockevent);
358	timer0_clockevent.min_delta_ns =
359	clockevent_delta2ns(0xf, &timer0_clockevent);
360
361	timer0_clockevent.cpumask = cpumask_of(0);
362	clockevents_register_device(&timer0_clockevent);
363	}
364
365	struct sys_timer bcmring_timer = {
366	.init = bcmring_init_timer,
367	};