[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-at91 / gpio.c

/*
 * linux/arch/arm/mach-at91/gpio.c
 *
 * Copyright (C) 2005 HP Labs
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/at91_pio.h>
#include <mach/gpio.h>

#include <asm/gpio.h>

#include "generic.h"

struct at91_gpio_chip {
	struct gpio_chip	chip;
	struct at91_gpio_chip	*next;		/* Bank sharing same clock */
	struct at91_gpio_bank	*bank;		/* Bank definition */
	void __iomem		*regbase;	/* Base of register bank */
};

#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)

static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
static int at91_gpiolib_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val);
static int at91_gpiolib_direction_input(struct gpio_chip *chip,
					unsigned offset);

#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio)			\
	{								\
		.chip = {						\
			.label		  = name,			\
			.direction_input  = at91_gpiolib_direction_input, \
			.direction_output = at91_gpiolib_direction_output, \
			.get		  = at91_gpiolib_get,		\
			.set		  = at91_gpiolib_set,		\
			.dbg_show	  = at91_gpiolib_dbg_show,	\
			.base		  = base_gpio,			\
			.ngpio		  = nr_gpio,			\
		},							\
	}

static struct at91_gpio_chip gpio_chip[] = {
	AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32),
	AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32),
	AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32),
	AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32),
	AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32),
};

static int gpio_banks;

static inline void __iomem *pin_to_controller(unsigned pin)
{
	pin -= PIN_BASE;
	pin /= 32;
	if (likely(pin < gpio_banks))
		return gpio_chip[pin].regbase;

	return NULL;
}

static inline unsigned pin_to_mask(unsigned pin)
{
	pin -= PIN_BASE;
	return 1 << (pin % 32);
}


/*--------------------------------------------------------------------------*/

/* Not all hardware capabilities are exposed through these calls; they
 * only encapsulate the most common features and modes.  (So if you
 * want to change signals in groups, do it directly.)
 *
 * Bootloaders will usually handle some of the pin multiplexing setup.
 * The intent is certainly that by the time Linux is fully booted, all
 * pins should have been fully initialized.  These setup calls should
 * only be used by board setup routines, or possibly in driver probe().
 *
 * For bootloaders doing all that setup, these calls could be inlined
 * as NOPs so Linux won't duplicate any setup code
 */


/*
 * mux the pin to the "GPIO" peripheral role.
 */
int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;
	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_PER);
	return 0;
}
EXPORT_SYMBOL(at91_set_GPIO_periph);


/*
 * mux the pin to the "A" internal peripheral role.
 */
int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_ASR);
	__raw_writel(mask, pio + PIO_PDR);
	return 0;
}
EXPORT_SYMBOL(at91_set_A_periph);


/*
 * mux the pin to the "B" internal peripheral role.
 */
int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_BSR);
	__raw_writel(mask, pio + PIO_PDR);
	return 0;
}
EXPORT_SYMBOL(at91_set_B_periph);


/*
 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
 * configure it for an input.
 */
int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_ODR);
	__raw_writel(mask, pio + PIO_PER);
	return 0;
}
EXPORT_SYMBOL(at91_set_gpio_input);


/*
 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
 * and configure it for an output.
 */
int __init_or_module at91_set_gpio_output(unsigned pin, int value)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + PIO_PUDR);
	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
	__raw_writel(mask, pio + PIO_OER);
	__raw_writel(mask, pio + PIO_PER);
	return 0;
}
EXPORT_SYMBOL(at91_set_gpio_output);


/*
 * enable/disable the glitch filter; mostly used with IRQ handling.
 */
int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;
	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
	return 0;
}
EXPORT_SYMBOL(at91_set_deglitch);

/*
 * enable/disable the multi-driver; This is only valid for output and
 * allows the output pin to run as an open collector output.
 */
int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
	return 0;
}
EXPORT_SYMBOL(at91_set_multi_drive);

/*
 * assuming the pin is muxed as a gpio output, set its value.
 */
int at91_set_gpio_value(unsigned pin, int value)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;
	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
	return 0;
}
EXPORT_SYMBOL(at91_set_gpio_value);


/*
 * read the pin's value (works even if it's not muxed as a gpio).
 */
int at91_get_gpio_value(unsigned pin)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);
	u32		pdsr;

	if (!pio)
		return -EINVAL;
	pdsr = __raw_readl(pio + PIO_PDSR);
	return (pdsr & mask) != 0;
}
EXPORT_SYMBOL(at91_get_gpio_value);

/*--------------------------------------------------------------------------*/

#ifdef CONFIG_PM

static u32 wakeups[MAX_GPIO_BANKS];
static u32 backups[MAX_GPIO_BANKS];

static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
{
	unsigned	mask = pin_to_mask(d->irq);
	unsigned	bank = (d->irq - PIN_BASE) / 32;

	if (unlikely(bank >= MAX_GPIO_BANKS))
		return -EINVAL;

	if (state)
		wakeups[bank] |= mask;
	else
		wakeups[bank] &= ~mask;

	set_irq_wake(gpio_chip[bank].bank->id, state);

	return 0;
}

void at91_gpio_suspend(void)
{
	int i;

	for (i = 0; i < gpio_banks; i++) {
		void __iomem	*pio = gpio_chip[i].regbase;

		backups[i] = __raw_readl(pio + PIO_IMR);
		__raw_writel(backups[i], pio + PIO_IDR);
		__raw_writel(wakeups[i], pio + PIO_IER);

		if (!wakeups[i])
			clk_disable(gpio_chip[i].bank->clock);
		else {
#ifdef CONFIG_PM_DEBUG
			printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
#endif
		}
	}
}

void at91_gpio_resume(void)
{
	int i;

	for (i = 0; i < gpio_banks; i++) {
		void __iomem	*pio = gpio_chip[i].regbase;

		if (!wakeups[i])
			clk_enable(gpio_chip[i].bank->clock);

		__raw_writel(wakeups[i], pio + PIO_IDR);
		__raw_writel(backups[i], pio + PIO_IER);
	}
}

#else
#define gpio_irq_set_wake	NULL
#endif


/* Several AIC controller irqs are dispatched through this GPIO handler.
 * To use any AT91_PIN_* as an externally triggered IRQ, first call
 * at91_set_gpio_input() then maybe enable its glitch filter.
 * Then just request_irq() with the pin ID; it works like any ARM IRQ
 * handler, though it always triggers on rising and falling edges.
 *
 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
 * configuring them with at91_set_a_periph() or at91_set_b_periph().
 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
 */

static void gpio_irq_mask(struct irq_data *d)
{
	void __iomem	*pio = pin_to_controller(d->irq);
	unsigned	mask = pin_to_mask(d->irq);

	if (pio)
		__raw_writel(mask, pio + PIO_IDR);
}

static void gpio_irq_unmask(struct irq_data *d)
{
	void __iomem	*pio = pin_to_controller(d->irq);
	unsigned	mask = pin_to_mask(d->irq);

	if (pio)
		__raw_writel(mask, pio + PIO_IER);
}

static int gpio_irq_type(struct irq_data *d, unsigned type)
{
	switch (type) {
	case IRQ_TYPE_NONE:
	case IRQ_TYPE_EDGE_BOTH:
		return 0;
	default:
		return -EINVAL;
	}
}

static struct irq_chip gpio_irqchip = {
	.name		= "GPIO",
	.irq_mask	= gpio_irq_mask,
	.irq_unmask	= gpio_irq_unmask,
	.irq_set_type	= gpio_irq_type,
	.irq_set_wake	= gpio_irq_set_wake,
};

static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
	unsigned	pin;
	struct irq_desc	*gpio;
	struct at91_gpio_chip *at91_gpio;
	void __iomem	*pio;
	u32		isr;

	at91_gpio = get_irq_chip_data(irq);
	pio = at91_gpio->regbase;

	/* temporarily mask (level sensitive) parent IRQ */
	desc->irq_data.chip->irq_ack(&desc->irq_data);
	for (;;) {
		/* Reading ISR acks pending (edge triggered) GPIO interrupts.
		 * When there none are pending, we're finished unless we need
		 * to process multiple banks (like ID_PIOCDE on sam9263).
		 */
		isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
		if (!isr) {
			if (!at91_gpio->next)
				break;
			at91_gpio = at91_gpio->next;
			pio = at91_gpio->regbase;
			continue;
		}

		pin = at91_gpio->chip.base;
		gpio = &irq_desc[pin];

		while (isr) {
			if (isr & 1) {
				if (unlikely(gpio->depth)) {
					/*
					 * The core ARM interrupt handler lazily disables IRQs so
					 * another IRQ must be generated before it actually gets
					 * here to be disabled on the GPIO controller.
					 */
					gpio_irq_mask(irq_get_irq_data(pin));
				}
				else
					generic_handle_irq(pin);
			}
			pin++;
			gpio++;
			isr >>= 1;
		}
	}
	desc->irq_data.chip->irq_unmask(&desc->irq_data);
	/* now it may re-trigger */
}

/*--------------------------------------------------------------------------*/

#ifdef CONFIG_DEBUG_FS

static int at91_gpio_show(struct seq_file *s, void *unused)
{
	int bank, j;

	/* print heading */
	seq_printf(s, "Pin\t");
	for (bank = 0; bank < gpio_banks; bank++) {
		seq_printf(s, "PIO%c\t", 'A' + bank);
	};
	seq_printf(s, "\n\n");

	/* print pin status */
	for (j = 0; j < 32; j++) {
		seq_printf(s, "%i:\t", j);

		for (bank = 0; bank < gpio_banks; bank++) {
			unsigned	pin  = PIN_BASE + (32 * bank) + j;
			void __iomem	*pio = pin_to_controller(pin);
			unsigned	mask = pin_to_mask(pin);

			if (__raw_readl(pio + PIO_PSR) & mask)
				seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
			else
				seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");

			seq_printf(s, "\t");
		}

		seq_printf(s, "\n");
	}

	return 0;
}

static int at91_gpio_open(struct inode *inode, struct file *file)
{
	return single_open(file, at91_gpio_show, NULL);
}

static const struct file_operations at91_gpio_operations = {
	.open		= at91_gpio_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init at91_gpio_debugfs_init(void)
{
	/* /sys/kernel/debug/at91_gpio */
	(void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
	return 0;
}
postcore_initcall(at91_gpio_debugfs_init);

#endif

/*--------------------------------------------------------------------------*/

/*
 * This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

/*
 * Called from the processor-specific init to enable GPIO interrupt support.
 */
void __init at91_gpio_irq_setup(void)
{
	unsigned		pioc, pin;
	struct at91_gpio_chip	*this, *prev;

	for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL;
			pioc++ < gpio_banks;
			prev = this, this++) {
		unsigned	id = this->bank->id;
		unsigned	i;

		__raw_writel(~0, this->regbase + PIO_IDR);

		for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
			lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class);

			/*
			 * Can use the "simple" and not "edge" handler since it's
			 * shorter, and the AIC handles interrupts sanely.
			 */
			set_irq_chip(pin, &gpio_irqchip);
			set_irq_handler(pin, handle_simple_irq);
			set_irq_flags(pin, IRQF_VALID);
		}

		/* The toplevel handler handles one bank of GPIOs, except
		 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
		 * the list, so we only set up that handler.
		 */
		if (prev && prev->next == this)
			continue;

		set_irq_chip_data(id, this);
		set_irq_chained_handler(id, gpio_irq_handler);
	}
	pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
}

/* gpiolib support */
static int at91_gpiolib_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
	void __iomem *pio = at91_gpio->regbase;
	unsigned mask = 1 << offset;

	__raw_writel(mask, pio + PIO_ODR);
	return 0;
}

static int at91_gpiolib_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
	void __iomem *pio = at91_gpio->regbase;
	unsigned mask = 1 << offset;

	__raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
	__raw_writel(mask, pio + PIO_OER);
	return 0;
}

static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
{
	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
	void __iomem *pio = at91_gpio->regbase;
	unsigned mask = 1 << offset;
	u32 pdsr;

	pdsr = __raw_readl(pio + PIO_PDSR);
	return (pdsr & mask) != 0;
}

static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
	void __iomem *pio = at91_gpio->regbase;
	unsigned mask = 1 << offset;

	__raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
}

static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	int i;

	for (i = 0; i < chip->ngpio; i++) {
		unsigned pin = chip->base + i;
		void __iomem *pio = pin_to_controller(pin);
		unsigned mask = pin_to_mask(pin);
		const char *gpio_label;

		gpio_label = gpiochip_is_requested(chip, i);
		if (gpio_label) {
			seq_printf(s, "[%s] GPIO%s%d: ",
				   gpio_label, chip->label, i);
			if (__raw_readl(pio + PIO_PSR) & mask)
				seq_printf(s, "[gpio] %s\n",
					   at91_get_gpio_value(pin) ?
					   "set" : "clear");
			else
				seq_printf(s, "[periph %s]\n",
					   __raw_readl(pio + PIO_ABSR) &
					   mask ? "B" : "A");
		}
	}
}

/*
 * Called from the processor-specific init to enable GPIO pin support.
 */
void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
{
	unsigned		i;
	struct at91_gpio_chip *at91_gpio, *last = NULL;

	BUG_ON(nr_banks > MAX_GPIO_BANKS);

	gpio_banks = nr_banks;

	for (i = 0; i < nr_banks; i++) {
		at91_gpio = &gpio_chip[i];

		at91_gpio->bank = &data[i];
		at91_gpio->chip.base = PIN_BASE + i * 32;
		at91_gpio->regbase = at91_gpio->bank->offset +
			(void __iomem *)AT91_VA_BASE_SYS;

		/* enable PIO controller's clock */
		clk_enable(at91_gpio->bank->clock);

		/* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
		if (last && last->bank->id == at91_gpio->bank->id)
			last->next = at91_gpio;
		last = at91_gpio;

		gpiochip_add(&at91_gpio->chip);
	}
}
Commit	Line	Data
73a59c1c	1	/*
9d041268	2	* linux/arch/arm/mach-at91/gpio.c
73a59c1c SP	3	*
	4	* Copyright (C) 2005 HP Labs
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
f2173834	12	#include <linux/clk.h>
73a59c1c	13	#include <linux/errno.h>
07d265dd TG	14	#include <linux/interrupt.h>
07d265dd TG	15	#include <linux/irq.h>
b66545e7 AV	16	#include <linux/debugfs.h>
b66545e7 AV	17	#include <linux/seq_file.h>
73a59c1c SP	18	#include <linux/kernel.h>
	19	#include <linux/list.h>
	20	#include <linux/module.h>
fced80c7	21	#include <linux/io.h>
73a59c1c	22
a09e64fb RK	23	#include <mach/hardware.h>
	24	#include <mach/at91_pio.h>
	25	#include <mach/gpio.h>
73a59c1c	26
f373e8c0 RM	27	#include <asm/gpio.h>
f373e8c0 RM	28
f2173834 AV	29	#include "generic.h"
f2173834 AV	30
f373e8c0 RM	31	struct at91_gpio_chip {
	32	struct gpio_chip chip;
	33	struct at91_gpio_chip next; / Bank sharing same clock */
	34	struct at91_gpio_bank bank; / Bank definition */
	35	void __iomem regbase; / Base of register bank */
	36	};
f2173834	37
f373e8c0 RM	38	#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
	39
	40	static void at91_gpiolib_dbg_show(struct seq_file s, struct gpio_chip chip);
	41	static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
	42	static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
	43	static int at91_gpiolib_direction_output(struct gpio_chip *chip,
	44	unsigned offset, int val);
	45	static int at91_gpiolib_direction_input(struct gpio_chip *chip,
	46	unsigned offset);
f373e8c0 RM	47
	48	#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \
	49	{ \
	50	.chip = { \
	51	.label = name, \
f373e8c0 RM	52	.direction_input = at91_gpiolib_direction_input, \
	53	.direction_output = at91_gpiolib_direction_output, \
	54	.get = at91_gpiolib_get, \
	55	.set = at91_gpiolib_set, \
	56	.dbg_show = at91_gpiolib_dbg_show, \
	57	.base = base_gpio, \
	58	.ngpio = nr_gpio, \
	59	}, \
	60	}
f2173834	61
f373e8c0 RM	62	static struct at91_gpio_chip gpio_chip[] = {
	63	AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32),
	64	AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32),
	65	AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32),
	66	AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32),
	67	AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32),
	68	};
	69
	70	static int gpio_banks;
73a59c1c SP	71
	72	static inline void __iomem *pin_to_controller(unsigned pin)
	73	{
73a59c1c SP	74	pin -= PIN_BASE;
73a59c1c SP	75	pin /= 32;
f2173834	76	if (likely(pin < gpio_banks))
f373e8c0	77	return gpio_chip[pin].regbase;
73a59c1c SP	78
	79	return NULL;
	80	}
	81
	82	static inline unsigned pin_to_mask(unsigned pin)
	83	{
	84	pin -= PIN_BASE;
	85	return 1 << (pin % 32);
	86	}
	87
	88
	89	/--------------------------------------------------------------------------/
	90
	91	/* Not all hardware capabilities are exposed through these calls; they
	92	* only encapsulate the most common features and modes. (So if you
	93	* want to change signals in groups, do it directly.)
	94	*
	95	* Bootloaders will usually handle some of the pin multiplexing setup.
	96	* The intent is certainly that by the time Linux is fully booted, all
	97	* pins should have been fully initialized. These setup calls should
	98	* only be used by board setup routines, or possibly in driver probe().
	99	*
	100	* For bootloaders doing all that setup, these calls could be inlined
	101	* as NOPs so Linux won't duplicate any setup code
	102	*/
	103
	104
a31c4eea DB	105	/*
	106	* mux the pin to the "GPIO" peripheral role.
	107	*/
	108	int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
	109	{
	110	void __iomem *pio = pin_to_controller(pin);
	111	unsigned mask = pin_to_mask(pin);
	112
	113	if (!pio)
	114	return -EINVAL;
	115	__raw_writel(mask, pio + PIO_IDR);
	116	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	117	__raw_writel(mask, pio + PIO_PER);
	118	return 0;
	119	}
	120	EXPORT_SYMBOL(at91_set_GPIO_periph);
	121
	122
73a59c1c SP	123	/*
	124	* mux the pin to the "A" internal peripheral role.
	125	*/
	126	int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
	127	{
	128	void __iomem *pio = pin_to_controller(pin);
	129	unsigned mask = pin_to_mask(pin);
	130
	131	if (!pio)
	132	return -EINVAL;
	133
	134	__raw_writel(mask, pio + PIO_IDR);
	135	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	136	__raw_writel(mask, pio + PIO_ASR);
	137	__raw_writel(mask, pio + PIO_PDR);
	138	return 0;
	139	}
	140	EXPORT_SYMBOL(at91_set_A_periph);
	141
	142
	143	/*
	144	* mux the pin to the "B" internal peripheral role.
	145	*/
	146	int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
	147	{
	148	void __iomem *pio = pin_to_controller(pin);
	149	unsigned mask = pin_to_mask(pin);
	150
	151	if (!pio)
	152	return -EINVAL;
	153
	154	__raw_writel(mask, pio + PIO_IDR);
	155	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	156	__raw_writel(mask, pio + PIO_BSR);
	157	__raw_writel(mask, pio + PIO_PDR);
	158	return 0;
	159	}
	160	EXPORT_SYMBOL(at91_set_B_periph);
	161
	162
	163	/*
	164	* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
	165	* configure it for an input.
	166	*/
	167	int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
	168	{
	169	void __iomem *pio = pin_to_controller(pin);
	170	unsigned mask = pin_to_mask(pin);
	171
	172	if (!pio)
	173	return -EINVAL;
	174
	175	__raw_writel(mask, pio + PIO_IDR);
	176	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	177	__raw_writel(mask, pio + PIO_ODR);
	178	__raw_writel(mask, pio + PIO_PER);
	179	return 0;
	180	}
	181	EXPORT_SYMBOL(at91_set_gpio_input);
	182
	183
	184	/*
	185	* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
	186	* and configure it for an output.
187	*/
188	int __init_or_module at91_set_gpio_output(unsigned pin, int value)
189	{
190	void __iomem *pio = pin_to_controller(pin);
191	unsigned mask = pin_to_mask(pin);
192
193	if (!pio)
194	return -EINVAL;
195
196	__raw_writel(mask, pio + PIO_IDR);
197	__raw_writel(mask, pio + PIO_PUDR);
198	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
199	__raw_writel(mask, pio + PIO_OER);
200	__raw_writel(mask, pio + PIO_PER);
201	return 0;
202	}
203	EXPORT_SYMBOL(at91_set_gpio_output);
204
205
206	/*
207	* enable/disable the glitch filter; mostly used with IRQ handling.
208	*/
209	int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
210	{
211	void __iomem *pio = pin_to_controller(pin);
212	unsigned mask = pin_to_mask(pin);
213
214	if (!pio)
215	return -EINVAL;
216	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
217	return 0;
218	}
219	EXPORT_SYMBOL(at91_set_deglitch);
220
df666b9c AV	221	/*
	222	* enable/disable the multi-driver; This is only valid for output and
	223	* allows the output pin to run as an open collector output.
	224	*/
	225	int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
	226	{
	227	void __iomem *pio = pin_to_controller(pin);
	228	unsigned mask = pin_to_mask(pin);
	229
	230	if (!pio)
	231	return -EINVAL;
	232
	233	__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
	234	return 0;
	235	}
	236	EXPORT_SYMBOL(at91_set_multi_drive);
	237
73a59c1c SP	238	/*
	239	* assuming the pin is muxed as a gpio output, set its value.
	240	*/
	241	int at91_set_gpio_value(unsigned pin, int value)
	242	{
	243	void __iomem *pio = pin_to_controller(pin);
	244	unsigned mask = pin_to_mask(pin);
	245
	246	if (!pio)
	247	return -EINVAL;
	248	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
	249	return 0;
	250	}
	251	EXPORT_SYMBOL(at91_set_gpio_value);
	252
	253
	254	/*
	255	* read the pin's value (works even if it's not muxed as a gpio).
	256	*/
	257	int at91_get_gpio_value(unsigned pin)
	258	{
	259	void __iomem *pio = pin_to_controller(pin);
	260	unsigned mask = pin_to_mask(pin);
	261	u32 pdsr;
	262
	263	if (!pio)
	264	return -EINVAL;
	265	pdsr = __raw_readl(pio + PIO_PDSR);
	266	return (pdsr & mask) != 0;
	267	}
	268	EXPORT_SYMBOL(at91_get_gpio_value);
	269
	270	/--------------------------------------------------------------------------/
	271
814138ff AV	272	#ifdef CONFIG_PM
814138ff AV	273
f2173834 AV	274	static u32 wakeups[MAX_GPIO_BANKS];
f2173834 AV	275	static u32 backups[MAX_GPIO_BANKS];
814138ff	276
da0f9403	277	static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
814138ff	278	{
da0f9403 LB	279	unsigned mask = pin_to_mask(d->irq);
da0f9403 LB	280	unsigned bank = (d->irq - PIN_BASE) / 32;
814138ff	281
3ea163e4	282	if (unlikely(bank >= MAX_GPIO_BANKS))
814138ff AV	283	return -EINVAL;
	284
	285	if (state)
3ea163e4	286	wakeups[bank] \|= mask;
814138ff	287	else
3ea163e4 AV	288	wakeups[bank] &= ~mask;
3ea163e4 AV	289
f373e8c0	290	set_irq_wake(gpio_chip[bank].bank->id, state);
814138ff AV	291
	292	return 0;
	293	}
	294
	295	void at91_gpio_suspend(void)
	296	{
	297	int i;
	298
f2173834	299	for (i = 0; i < gpio_banks; i++) {
f373e8c0	300	void __iomem *pio = gpio_chip[i].regbase;
814138ff	301
e83aff58 DB	302	backups[i] = __raw_readl(pio + PIO_IMR);
	303	__raw_writel(backups[i], pio + PIO_IDR);
	304	__raw_writel(wakeups[i], pio + PIO_IER);
814138ff	305
3ea163e4	306	if (!wakeups[i])
f373e8c0	307	clk_disable(gpio_chip[i].bank->clock);
3ea163e4	308	else {
814138ff	309	#ifdef CONFIG_PM_DEBUG
3ea163e4	310	printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
814138ff AV	311	#endif
	312	}
	313	}
	314	}
	315
	316	void at91_gpio_resume(void)
	317	{
	318	int i;
	319
f2173834	320	for (i = 0; i < gpio_banks; i++) {
f373e8c0	321	void __iomem *pio = gpio_chip[i].regbase;
814138ff	322
3ea163e4	323	if (!wakeups[i])
f373e8c0	324	clk_enable(gpio_chip[i].bank->clock);
3ea163e4	325
e83aff58 DB	326	__raw_writel(wakeups[i], pio + PIO_IDR);
e83aff58 DB	327	__raw_writel(backups[i], pio + PIO_IER);
f2173834	328	}
814138ff AV	329	}
	330
	331	#else
	332	#define gpio_irq_set_wake NULL
	333	#endif
	334
73a59c1c SP	335
	336	/* Several AIC controller irqs are dispatched through this GPIO handler.
	337	* To use any AT91_PIN_* as an externally triggered IRQ, first call
	338	* at91_set_gpio_input() then maybe enable its glitch filter.
	339	* Then just request_irq() with the pin ID; it works like any ARM IRQ
	340	* handler, though it always triggers on rising and falling edges.
	341	*
	342	* Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
	343	* configuring them with at91_set_a_periph() or at91_set_b_periph().
	344	* IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
	345	*/
	346
da0f9403	347	static void gpio_irq_mask(struct irq_data *d)
73a59c1c	348	{
da0f9403 LB	349	void __iomem *pio = pin_to_controller(d->irq);
da0f9403 LB	350	unsigned mask = pin_to_mask(d->irq);
73a59c1c SP	351
	352	if (pio)
	353	__raw_writel(mask, pio + PIO_IDR);
	354	}
	355
da0f9403	356	static void gpio_irq_unmask(struct irq_data *d)
73a59c1c	357	{
da0f9403 LB	358	void __iomem *pio = pin_to_controller(d->irq);
da0f9403 LB	359	unsigned mask = pin_to_mask(d->irq);
73a59c1c SP	360
	361	if (pio)
	362	__raw_writel(mask, pio + PIO_IER);
	363	}
	364
da0f9403	365	static int gpio_irq_type(struct irq_data *d, unsigned type)
73a59c1c	366	{
e83aff58 DB	367	switch (type) {
	368	case IRQ_TYPE_NONE:
	369	case IRQ_TYPE_EDGE_BOTH:
	370	return 0;
	371	default:
	372	return -EINVAL;
	373	}
73a59c1c SP	374	}
73a59c1c SP	375
38c677cb DB	376	static struct irq_chip gpio_irqchip = {
38c677cb DB	377	.name = "GPIO",
da0f9403 LB	378	.irq_mask = gpio_irq_mask,
	379	.irq_unmask = gpio_irq_unmask,
	380	.irq_set_type = gpio_irq_type,
	381	.irq_set_wake = gpio_irq_set_wake,
73a59c1c SP	382	};
73a59c1c SP	383
10dd5ce2	384	static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
73a59c1c SP	385	{
73a59c1c SP	386	unsigned pin;
10dd5ce2	387	struct irq_desc *gpio;
f373e8c0	388	struct at91_gpio_chip *at91_gpio;
73a59c1c SP	389	void __iomem *pio;
	390	u32 isr;
	391
f373e8c0 RM	392	at91_gpio = get_irq_chip_data(irq);
f373e8c0 RM	393	pio = at91_gpio->regbase;
73a59c1c SP	394
73a59c1c SP	395	/* temporarily mask (level sensitive) parent IRQ */
da0f9403	396	desc->irq_data.chip->irq_ack(&desc->irq_data);
73a59c1c	397	for (;;) {
e83aff58 DB	398	/* Reading ISR acks pending (edge triggered) GPIO interrupts.
	399	* When there none are pending, we're finished unless we need
	400	* to process multiple banks (like ID_PIOCDE on sam9263).
	401	*/
73a59c1c	402	isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
e83aff58	403	if (!isr) {
f373e8c0	404	if (!at91_gpio->next)
e83aff58	405	break;
f373e8c0 RM	406	at91_gpio = at91_gpio->next;
f373e8c0 RM	407	pio = at91_gpio->regbase;
e83aff58 DB	408	continue;
e83aff58 DB	409	}
73a59c1c	410
f373e8c0	411	pin = at91_gpio->chip.base;
085eefb5	412	gpio = &irq_desc[pin];
73a59c1c SP	413
73a59c1c SP	414	while (isr) {
abbea718	415	if (isr & 1) {
07d265dd	416	if (unlikely(gpio->depth)) {
abbea718 AV	417	/*
	418	* The core ARM interrupt handler lazily disables IRQs so
	419	* another IRQ must be generated before it actually gets
	420	* here to be disabled on the GPIO controller.
	421	*/
da0f9403	422	gpio_irq_mask(irq_get_irq_data(pin));
abbea718 AV	423	}
abbea718 AV	424	else
d8aa0251	425	generic_handle_irq(pin);
abbea718	426	}
73a59c1c SP	427	pin++;
	428	gpio++;
	429	isr >>= 1;
	430	}
	431	}
da0f9403	432	desc->irq_data.chip->irq_unmask(&desc->irq_data);
73a59c1c SP	433	/* now it may re-trigger */
	434	}
	435
f2173834 AV	436	/--------------------------------------------------------------------------/
f2173834 AV	437
b66545e7 AV	438	#ifdef CONFIG_DEBUG_FS
	439
	440	static int at91_gpio_show(struct seq_file s, void unused)
	441	{
	442	int bank, j;
	443
	444	/* print heading */
	445	seq_printf(s, "Pin\t");
	446	for (bank = 0; bank < gpio_banks; bank++) {
	447	seq_printf(s, "PIO%c\t", 'A' + bank);
	448	};
	449	seq_printf(s, "\n\n");
	450
	451	/* print pin status */
	452	for (j = 0; j < 32; j++) {
	453	seq_printf(s, "%i:\t", j);
	454
	455	for (bank = 0; bank < gpio_banks; bank++) {
	456	unsigned pin = PIN_BASE + (32 * bank) + j;
	457	void __iomem *pio = pin_to_controller(pin);
	458	unsigned mask = pin_to_mask(pin);
	459
	460	if (__raw_readl(pio + PIO_PSR) & mask)
	461	seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
	462	else
	463	seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
	464
	465	seq_printf(s, "\t");
	466	}
	467
	468	seq_printf(s, "\n");
	469	}
	470
	471	return 0;
	472	}
	473
	474	static int at91_gpio_open(struct inode inode, struct file file)
	475	{
	476	return single_open(file, at91_gpio_show, NULL);
	477	}
	478
	479	static const struct file_operations at91_gpio_operations = {
	480	.open = at91_gpio_open,
	481	.read = seq_read,
	482	.llseek = seq_lseek,
	483	.release = single_release,
	484	};
	485
	486	static int __init at91_gpio_debugfs_init(void)
	487	{
	488	/* /sys/kernel/debug/at91_gpio */
	489	(void) debugfs_create_file("at91_gpio", S_IFREG \| S_IRUGO, NULL, NULL, &at91_gpio_operations);
	490	return 0;
	491	}
	492	postcore_initcall(at91_gpio_debugfs_init);
	493
	494	#endif
	495
	496	/--------------------------------------------------------------------------/
	497
2b768b6c AV	498	/*
2b768b6c AV	499	* This lock class tells lockdep that GPIO irqs are in a different
37aca70c DB	500	* category than their parents, so it won't report false recursion.
	501	*/
	502	static struct lock_class_key gpio_lock_class;
	503
f2173834 AV	504	/*
	505	* Called from the processor-specific init to enable GPIO interrupt support.
	506	*/
	507	void __init at91_gpio_irq_setup(void)
73a59c1c	508	{
e83aff58	509	unsigned pioc, pin;
f373e8c0	510	struct at91_gpio_chip this, prev;
73a59c1c	511
f373e8c0	512	for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL;
e83aff58 DB	513	pioc++ < gpio_banks;
e83aff58 DB	514	prev = this, this++) {
f373e8c0	515	unsigned id = this->bank->id;
73a59c1c SP	516	unsigned i;
73a59c1c SP	517
e83aff58	518	__raw_writel(~0, this->regbase + PIO_IDR);
73a59c1c	519
f373e8c0	520	for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
37aca70c DB	521	lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class);
37aca70c DB	522
814138ff AV	523	/*
814138ff AV	524	* Can use the "simple" and not "edge" handler since it's
3a4fa0a2	525	* shorter, and the AIC handles interrupts sanely.
814138ff	526	*/
73a59c1c	527	set_irq_chip(pin, &gpio_irqchip);
10dd5ce2	528	set_irq_handler(pin, handle_simple_irq);
73a59c1c SP	529	set_irq_flags(pin, IRQF_VALID);
	530	}
	531
e83aff58 DB	532	/* The toplevel handler handles one bank of GPIOs, except
	533	* AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
	534	* the list, so we only set up that handler.
	535	*/
	536	if (prev && prev->next == this)
	537	continue;
	538
	539	set_irq_chip_data(id, this);
73a59c1c	540	set_irq_chained_handler(id, gpio_irq_handler);
73a59c1c	541	}
f2173834 AV	542	pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
	543	}
	544
f373e8c0 RM	545	/* gpiolib support */
	546	static int at91_gpiolib_direction_input(struct gpio_chip *chip,
	547	unsigned offset)
	548	{
	549	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
	550	void __iomem *pio = at91_gpio->regbase;
	551	unsigned mask = 1 << offset;
	552
	553	__raw_writel(mask, pio + PIO_ODR);
	554	return 0;
	555	}
	556
	557	static int at91_gpiolib_direction_output(struct gpio_chip *chip,
	558	unsigned offset, int val)
	559	{
	560	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
	561	void __iomem *pio = at91_gpio->regbase;
	562	unsigned mask = 1 << offset;
	563
	564	__raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
	565	__raw_writel(mask, pio + PIO_OER);
	566	return 0;
	567	}
	568
	569	static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
	570	{
	571	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
	572	void __iomem *pio = at91_gpio->regbase;
	573	unsigned mask = 1 << offset;
	574	u32 pdsr;
	575
	576	pdsr = __raw_readl(pio + PIO_PDSR);
	577	return (pdsr & mask) != 0;
	578	}
	579
	580	static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
	581	{
	582	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
	583	void __iomem *pio = at91_gpio->regbase;
	584	unsigned mask = 1 << offset;
	585
	586	__raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
	587	}
	588
f373e8c0 RM	589	static void at91_gpiolib_dbg_show(struct seq_file s, struct gpio_chip chip)
	590	{
	591	int i;
	592
	593	for (i = 0; i < chip->ngpio; i++) {
	594	unsigned pin = chip->base + i;
	595	void __iomem *pio = pin_to_controller(pin);
	596	unsigned mask = pin_to_mask(pin);
	597	const char *gpio_label;
	598
	599	gpio_label = gpiochip_is_requested(chip, i);
	600	if (gpio_label) {
	601	seq_printf(s, "[%s] GPIO%s%d: ",
	602	gpio_label, chip->label, i);
	603	if (__raw_readl(pio + PIO_PSR) & mask)
	604	seq_printf(s, "[gpio] %s\n",
	605	at91_get_gpio_value(pin) ?
	606	"set" : "clear");
	607	else
	608	seq_printf(s, "[periph %s]\n",
	609	__raw_readl(pio + PIO_ABSR) &
	610	mask ? "B" : "A");
	611	}
	612	}
	613	}
	614
f2173834 AV	615	/*
	616	* Called from the processor-specific init to enable GPIO pin support.
	617	*/
	618	void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
	619	{
e83aff58	620	unsigned i;
f373e8c0	621	struct at91_gpio_chip at91_gpio, last = NULL;
e83aff58	622
f2173834 AV	623	BUG_ON(nr_banks > MAX_GPIO_BANKS);
f2173834 AV	624
f2173834	625	gpio_banks = nr_banks;
e83aff58	626
f373e8c0 RM	627	for (i = 0; i < nr_banks; i++) {
	628	at91_gpio = &gpio_chip[i];
	629
	630	at91_gpio->bank = &data[i];
	631	at91_gpio->chip.base = PIN_BASE + i * 32;
	632	at91_gpio->regbase = at91_gpio->bank->offset +
	633	(void __iomem *)AT91_VA_BASE_SYS;
e83aff58	634
2b768b6c	635	/* enable PIO controller's clock */
97fb44eb	636	clk_enable(at91_gpio->bank->clock);
2b768b6c	637
e83aff58	638	/* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
f373e8c0 RM	639	if (last && last->bank->id == at91_gpio->bank->id)
	640	last->next = at91_gpio;
	641	last = at91_gpio;
	642
	643	gpiochip_add(&at91_gpio->chip);
e83aff58	644	}
73a59c1c	645	}