Commit | Line | Data |
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eb1d65aa GU |
1 | /* |
2 | * arch/arm/mach-at91/at91x40.c | |
3 | * | |
4 | * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com> | |
5 | * Copyright (C) 2005 SAN People | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/irq.h> | |
14070ade | 16 | #include <linux/io.h> |
c9dfafba | 17 | #include <asm/proc-fns.h> |
86dfe446 | 18 | #include <asm/system_misc.h> |
eb1d65aa | 19 | #include <asm/mach/arch.h> |
a09e64fb RK |
20 | #include <mach/at91x40.h> |
21 | #include <mach/at91_st.h> | |
22 | #include <mach/timex.h> | |
a510b9ba JCPV |
23 | |
24 | #include "at91_aic.h" | |
eb1d65aa GU |
25 | #include "generic.h" |
26 | ||
27 | /* | |
66aaeff1 GU |
28 | * Export the clock functions for the AT91X40. Some external code common |
29 | * to all AT91 family parts relys on this, like the gpio and serial support. | |
eb1d65aa GU |
30 | */ |
31 | int clk_enable(struct clk *clk) | |
32 | { | |
33 | return 0; | |
34 | } | |
35 | ||
66aaeff1 GU |
36 | void clk_disable(struct clk *clk) |
37 | { | |
38 | } | |
39 | ||
40 | unsigned long clk_get_rate(struct clk *clk) | |
41 | { | |
42 | return AT91X40_MASTER_CLOCK; | |
43 | } | |
44 | ||
c9dfafba NP |
45 | static void at91x40_idle(void) |
46 | { | |
47 | /* | |
48 | * Disable the processor clock. The processor will be automatically | |
49 | * re-enabled by an interrupt or by a reset. | |
50 | */ | |
dca4ba41 | 51 | __raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR)); |
c9dfafba NP |
52 | cpu_do_idle(); |
53 | } | |
54 | ||
eb1d65aa GU |
55 | void __init at91x40_initialize(unsigned long main_clock) |
56 | { | |
c9dfafba | 57 | arm_pm_idle = at91x40_idle; |
eb1d65aa GU |
58 | at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1) |
59 | | (1 << AT91X40_ID_IRQ2); | |
60 | } | |
61 | ||
62 | /* | |
63 | * The default interrupt priority levels (0 = lowest, 7 = highest). | |
64 | */ | |
65 | static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = { | |
66 | 7, /* Advanced Interrupt Controller (FIQ) */ | |
67 | 0, /* System Peripherals */ | |
68 | 0, /* USART 0 */ | |
69 | 0, /* USART 1 */ | |
70 | 2, /* Timer Counter 0 */ | |
71 | 2, /* Timer Counter 1 */ | |
72 | 2, /* Timer Counter 2 */ | |
73 | 0, /* Watchdog timer */ | |
74 | 0, /* Parallel IO Controller A */ | |
75 | 0, /* Reserved */ | |
76 | 0, /* Reserved */ | |
77 | 0, /* Reserved */ | |
78 | 0, /* Reserved */ | |
79 | 0, /* Reserved */ | |
80 | 0, /* Reserved */ | |
81 | 0, /* Reserved */ | |
82 | 0, /* External IRQ0 */ | |
83 | 0, /* External IRQ1 */ | |
84 | 0, /* External IRQ2 */ | |
85 | }; | |
86 | ||
87 | void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS]) | |
88 | { | |
89 | if (!priority) | |
90 | priority = at91x40_default_irq_priority; | |
91 | ||
0654f4ab | 92 | at91_aic_init(priority, at91_extern_irq); |
eb1d65aa GU |
93 | } |
94 |