Commit | Line | Data |
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1a0ed732 | 1 | /* |
ad48ce74 | 2 | * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x |
1a0ed732 AV |
3 | * |
4 | * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France | |
5 | * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France | |
ad48ce74 | 6 | * Converted to ClockSource/ClockEvents by David Brownell. |
1a0ed732 AV |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
1a0ed732 AV |
12 | #include <linux/interrupt.h> |
13 | #include <linux/irq.h> | |
14 | #include <linux/kernel.h> | |
ad48ce74 AV |
15 | #include <linux/clk.h> |
16 | #include <linux/clockchips.h> | |
1a0ed732 | 17 | |
1a0ed732 AV |
18 | #include <asm/mach/time.h> |
19 | ||
a09e64fb | 20 | #include <mach/at91_pit.h> |
1a0ed732 AV |
21 | |
22 | ||
23 | #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) | |
24 | #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) | |
25 | ||
ad48ce74 AV |
26 | static u32 pit_cycle; /* write-once */ |
27 | static u32 pit_cnt; /* access only w/system irq blocked */ | |
28 | ||
29 | ||
1a0ed732 | 30 | /* |
ad48ce74 AV |
31 | * Clocksource: just a monotonic counter of MCK/16 cycles. |
32 | * We don't care whether or not PIT irqs are enabled. | |
1a0ed732 | 33 | */ |
8e19608e | 34 | static cycle_t read_pit_clk(struct clocksource *cs) |
1a0ed732 | 35 | { |
ad48ce74 AV |
36 | unsigned long flags; |
37 | u32 elapsed; | |
38 | u32 t; | |
39 | ||
40 | raw_local_irq_save(flags); | |
41 | elapsed = pit_cnt; | |
42 | t = at91_sys_read(AT91_PIT_PIIR); | |
43 | raw_local_irq_restore(flags); | |
44 | ||
45 | elapsed += PIT_PICNT(t) * pit_cycle; | |
46 | elapsed += PIT_CPIV(t); | |
47 | return elapsed; | |
48 | } | |
49 | ||
50 | static struct clocksource pit_clk = { | |
51 | .name = "pit", | |
52 | .rating = 175, | |
53 | .read = read_pit_clk, | |
ad48ce74 AV |
54 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
55 | }; | |
1a0ed732 | 56 | |
1a0ed732 | 57 | |
ad48ce74 AV |
58 | /* |
59 | * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16) | |
60 | */ | |
61 | static void | |
62 | pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) | |
63 | { | |
ad48ce74 AV |
64 | switch (mode) { |
65 | case CLOCK_EVT_MODE_PERIODIC: | |
501d7038 | 66 | /* update clocksource counter */ |
ad48ce74 AV |
67 | pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); |
68 | at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN | |
69 | | AT91_PIT_PITIEN); | |
ad48ce74 AV |
70 | break; |
71 | case CLOCK_EVT_MODE_ONESHOT: | |
72 | BUG(); | |
73 | /* FALLTHROUGH */ | |
74 | case CLOCK_EVT_MODE_SHUTDOWN: | |
75 | case CLOCK_EVT_MODE_UNUSED: | |
76 | /* disable irq, leaving the clocksource active */ | |
77 | at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); | |
78 | break; | |
79 | case CLOCK_EVT_MODE_RESUME: | |
80 | break; | |
81 | } | |
1a0ed732 AV |
82 | } |
83 | ||
ad48ce74 AV |
84 | static struct clock_event_device pit_clkevt = { |
85 | .name = "pit", | |
86 | .features = CLOCK_EVT_FEAT_PERIODIC, | |
87 | .shift = 32, | |
88 | .rating = 100, | |
ad48ce74 AV |
89 | .set_mode = pit_clkevt_mode, |
90 | }; | |
91 | ||
92 | ||
1a0ed732 AV |
93 | /* |
94 | * IRQ handler for the timer. | |
95 | */ | |
ad48ce74 | 96 | static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id) |
1a0ed732 | 97 | { |
501d7038 UKK |
98 | /* |
99 | * irqs should be disabled here, but as the irq is shared they are only | |
100 | * guaranteed to be off if the timer irq is registered first. | |
101 | */ | |
102 | WARN_ON_ONCE(!irqs_disabled()); | |
1a0ed732 | 103 | |
ad48ce74 AV |
104 | /* The PIT interrupt may be disabled, and is shared */ |
105 | if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC) | |
106 | && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) { | |
107 | unsigned nr_ticks; | |
108 | ||
109 | /* Get number of ticks performed before irq, and ack it */ | |
1a0ed732 AV |
110 | nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); |
111 | do { | |
ad48ce74 AV |
112 | pit_cnt += pit_cycle; |
113 | pit_clkevt.event_handler(&pit_clkevt); | |
1a0ed732 AV |
114 | nr_ticks--; |
115 | } while (nr_ticks); | |
116 | ||
1a0ed732 | 117 | return IRQ_HANDLED; |
ad48ce74 AV |
118 | } |
119 | ||
120 | return IRQ_NONE; | |
1a0ed732 AV |
121 | } |
122 | ||
ad48ce74 | 123 | static struct irqaction at91sam926x_pit_irq = { |
1a0ed732 | 124 | .name = "at91_tick", |
b30fabad | 125 | .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
ad48ce74 | 126 | .handler = at91sam926x_pit_interrupt |
1a0ed732 AV |
127 | }; |
128 | ||
ad48ce74 | 129 | static void at91sam926x_pit_reset(void) |
1a0ed732 | 130 | { |
ad48ce74 | 131 | /* Disable timer and irqs */ |
1a0ed732 AV |
132 | at91_sys_write(AT91_PIT_MR, 0); |
133 | ||
ad48ce74 AV |
134 | /* Clear any pending interrupts, wait for PIT to stop counting */ |
135 | while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) | |
136 | cpu_relax(); | |
1a0ed732 | 137 | |
ad48ce74 AV |
138 | /* Start PIT but don't enable IRQ */ |
139 | at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); | |
1a0ed732 AV |
140 | } |
141 | ||
142 | /* | |
ad48ce74 | 143 | * Set up both clocksource and clockevent support. |
1a0ed732 | 144 | */ |
ad48ce74 | 145 | static void __init at91sam926x_pit_init(void) |
1a0ed732 | 146 | { |
ad48ce74 AV |
147 | unsigned long pit_rate; |
148 | unsigned bits; | |
149 | ||
150 | /* | |
151 | * Use our actual MCK to figure out how many MCK/16 ticks per | |
152 | * 1/HZ period (instead of a compile-time constant LATCH). | |
153 | */ | |
154 | pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16; | |
155 | pit_cycle = (pit_rate + HZ/2) / HZ; | |
156 | WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0); | |
1a0ed732 | 157 | |
ad48ce74 AV |
158 | /* Initialize and enable the timer */ |
159 | at91sam926x_pit_reset(); | |
160 | ||
161 | /* | |
162 | * Register clocksource. The high order bits of PIV are unused, | |
163 | * so this isn't a 32-bit counter unless we get clockevent irqs. | |
164 | */ | |
ad48ce74 AV |
165 | bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */; |
166 | pit_clk.mask = CLOCKSOURCE_MASK(bits); | |
132b1632 | 167 | clocksource_register_hz(&pit_clk, pit_rate); |
ad48ce74 AV |
168 | |
169 | /* Set up irq handler */ | |
170 | setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq); | |
171 | ||
172 | /* Set up and register clockevents */ | |
173 | pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift); | |
320ab2b0 | 174 | pit_clkevt.cpumask = cpumask_of(0); |
ad48ce74 | 175 | clockevents_register_device(&pit_clkevt); |
1a0ed732 AV |
176 | } |
177 | ||
ad48ce74 | 178 | static void at91sam926x_pit_suspend(void) |
1a0ed732 AV |
179 | { |
180 | /* Disable timer */ | |
181 | at91_sys_write(AT91_PIT_MR, 0); | |
182 | } | |
1a0ed732 AV |
183 | |
184 | struct sys_timer at91sam926x_timer = { | |
ad48ce74 AV |
185 | .init = at91sam926x_pit_init, |
186 | .suspend = at91sam926x_pit_suspend, | |
187 | .resume = at91sam926x_pit_reset, | |
1a0ed732 | 188 | }; |