[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-at91 / at91sam9263.c

/*
 * arch/arm/mach-at91/at91sam9263.c
 *
 *  Copyright (C) 2007 Atmel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>
#include <linux/pm.h>

#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9263.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>

#include "generic.h"
#include "clock.h"

static struct map_desc at91sam9263_io_desc[] __initdata = {
	{
		.virtual	= AT91_VA_BASE_SYS,
		.pfn		= __phys_to_pfn(AT91_BASE_SYS),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE,
		.pfn		= __phys_to_pfn(AT91SAM9263_SRAM0_BASE),
		.length		= AT91SAM9263_SRAM0_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE,
		.pfn		= __phys_to_pfn(AT91SAM9263_SRAM1_BASE),
		.length		= AT91SAM9263_SRAM1_SIZE,
		.type		= MT_DEVICE,
	},
};

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioCDE_clk = {
	.name		= "pioCDE_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PIOCDE,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
	.name		= "mci0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_MCI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
	.name		= "mci1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_MCI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk can_clk = {
	.name		= "can_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_CAN,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
	.name		= "twi_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_TWI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tcb_clk = {
	.name		= "tcb_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_TCB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
	.name		= "macb_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_EMAC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twodge_clk = {
	.name		= "2dge_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_2DGE,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
	.name		= "udc_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_UDP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
	.name		= "isi_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_ISI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
	.name		= "ohci_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_UHP,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioCDE_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&mmc0_clk,
	&mmc1_clk,
	&can_clk,
	&twi_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc0_clk,
	&ssc1_clk,
	&ac97_clk,
	&tcb_clk,
	&pwm_clk,
	&macb_clk,
	&twodge_clk,
	&udc_clk,
	&isi_clk,
	&lcdc_clk,
	&dma_clk,
	&ohci_clk,
	// irq0 .. irq1
};

/*
 * The four programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};
static struct clk pck2 = {
	.name		= "pck2",
	.pmc_mask	= AT91_PMC_PCK2,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 2,
};
static struct clk pck3 = {
	.name		= "pck3",
	.pmc_mask	= AT91_PMC_PCK3,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 3,
};

static void __init at91sam9263_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clk_register(&pck0);
	clk_register(&pck1);
	clk_register(&pck2);
	clk_register(&pck3);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9263_gpio[] = {
	{
		.id		= AT91SAM9263_ID_PIOA,
		.offset		= AT91_PIOA,
		.clock		= &pioA_clk,
	}, {
		.id		= AT91SAM9263_ID_PIOB,
		.offset		= AT91_PIOB,
		.clock		= &pioB_clk,
	}, {
		.id		= AT91SAM9263_ID_PIOCDE,
		.offset		= AT91_PIOC,
		.clock		= &pioCDE_clk,
	}, {
		.id		= AT91SAM9263_ID_PIOCDE,
		.offset		= AT91_PIOD,
		.clock		= &pioCDE_clk,
	}, {
		.id		= AT91SAM9263_ID_PIOCDE,
		.offset		= AT91_PIOE,
		.clock		= &pioCDE_clk,
	}
};

static void at91sam9263_poweroff(void)
{
	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}


/* --------------------------------------------------------------------
 *  AT91SAM9263 processor initialization
 * -------------------------------------------------------------------- */

void __init at91sam9263_initialize(unsigned long main_clock)
{
	/* Map peripherals */
	iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));

	at91_arch_reset = at91sam9_alt_reset;
	pm_power_off = at91sam9263_poweroff;
	at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);

	/* Init clock subsystem */
	at91_clock_init(main_clock);

	/* Register the processor-specific clocks */
	at91sam9263_register_clocks();

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9263_gpio, 5);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller (FIQ) */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C, D and E */
	0,
	0,
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	0,	/* Multimedia Card Interface 0 */
	0,	/* Multimedia Card Interface 1 */
	3,	/* CAN */
	6,	/* Two-Wire Interface */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	5,	/* AC97 Controller */
	0,	/* Timer Counter 0, 1 and 2 */
	0,	/* Pulse Width Modulation Controller */
	3,	/* Ethernet */
	0,
	0,	/* 2D Graphic Engine */
	2,	/* USB Device Port */
	0,	/* Image Sensor Interface */
	3,	/* LDC Controller */
	0,	/* DMA Controller */
	0,
	2,	/* USB Host port */
	0,	/* Advanced Interrupt Controller (IRQ0) */
	0,	/* Advanced Interrupt Controller (IRQ1) */
};

void __init at91sam9263_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
	if (!priority)
		priority = at91sam9263_default_irq_priority;

	/* Initialize the AIC interrupt controller */
	at91_aic_init(priority);

	/* Enable GPIO interrupts */
	at91_gpio_irq_setup();
}
Commit	Line	Data
b2c65616 AV	1	/*
	2	* arch/arm/mach-at91/at91sam9263.c
	3	*
	4	* Copyright (C) 2007 Atmel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
3ef2fb42	14	#include <linux/pm.h>
b2c65616	15
80b02c17	16	#include <asm/irq.h>
b2c65616 AV	17	#include <asm/mach/arch.h>
b2c65616 AV	18	#include <asm/mach/map.h>
a09e64fb RK	19	#include <mach/at91sam9263.h>
	20	#include <mach/at91_pmc.h>
	21	#include <mach/at91_rstc.h>
	22	#include <mach/at91_shdwc.h>
b2c65616 AV	23
	24	#include "generic.h"
	25	#include "clock.h"
	26
	27	static struct map_desc at91sam9263_io_desc[] __initdata = {
	28	{
	29	.virtual = AT91_VA_BASE_SYS,
	30	.pfn = __phys_to_pfn(AT91_BASE_SYS),
	31	.length = SZ_16K,
	32	.type = MT_DEVICE,
	33	}, {
	34	.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE,
	35	.pfn = __phys_to_pfn(AT91SAM9263_SRAM0_BASE),
	36	.length = AT91SAM9263_SRAM0_SIZE,
	37	.type = MT_DEVICE,
	38	}, {
	39	.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE,
	40	.pfn = __phys_to_pfn(AT91SAM9263_SRAM1_BASE),
	41	.length = AT91SAM9263_SRAM1_SIZE,
	42	.type = MT_DEVICE,
	43	},
	44	};
	45
	46	/* --------------------------------------------------------------------
	47	* Clocks
	48	* -------------------------------------------------------------------- */
	49
	50	/*
	51	* The peripheral clocks.
	52	*/
	53	static struct clk pioA_clk = {
	54	.name = "pioA_clk",
	55	.pmc_mask = 1 << AT91SAM9263_ID_PIOA,
	56	.type = CLK_TYPE_PERIPHERAL,
	57	};
	58	static struct clk pioB_clk = {
	59	.name = "pioB_clk",
	60	.pmc_mask = 1 << AT91SAM9263_ID_PIOB,
	61	.type = CLK_TYPE_PERIPHERAL,
	62	};
	63	static struct clk pioCDE_clk = {
	64	.name = "pioCDE_clk",
	65	.pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
	66	.type = CLK_TYPE_PERIPHERAL,
	67	};
	68	static struct clk usart0_clk = {
	69	.name = "usart0_clk",
	70	.pmc_mask = 1 << AT91SAM9263_ID_US0,
	71	.type = CLK_TYPE_PERIPHERAL,
	72	};
	73	static struct clk usart1_clk = {
	74	.name = "usart1_clk",
	75	.pmc_mask = 1 << AT91SAM9263_ID_US1,
	76	.type = CLK_TYPE_PERIPHERAL,
	77	};
	78	static struct clk usart2_clk = {
	79	.name = "usart2_clk",
	80	.pmc_mask = 1 << AT91SAM9263_ID_US2,
	81	.type = CLK_TYPE_PERIPHERAL,
	82	};
	83	static struct clk mmc0_clk = {
	84	.name = "mci0_clk",
	85	.pmc_mask = 1 << AT91SAM9263_ID_MCI0,
	86	.type = CLK_TYPE_PERIPHERAL,
87	};
88	static struct clk mmc1_clk = {
89	.name = "mci1_clk",
90	.pmc_mask = 1 << AT91SAM9263_ID_MCI1,
91	.type = CLK_TYPE_PERIPHERAL,
92	};
e8788bab AV	93	static struct clk can_clk = {
	94	.name = "can_clk",
	95	.pmc_mask = 1 << AT91SAM9263_ID_CAN,
	96	.type = CLK_TYPE_PERIPHERAL,
	97	};
b2c65616 AV	98	static struct clk twi_clk = {
	99	.name = "twi_clk",
	100	.pmc_mask = 1 << AT91SAM9263_ID_TWI,
	101	.type = CLK_TYPE_PERIPHERAL,
	102	};
	103	static struct clk spi0_clk = {
	104	.name = "spi0_clk",
	105	.pmc_mask = 1 << AT91SAM9263_ID_SPI0,
	106	.type = CLK_TYPE_PERIPHERAL,
	107	};
	108	static struct clk spi1_clk = {
	109	.name = "spi1_clk",
	110	.pmc_mask = 1 << AT91SAM9263_ID_SPI1,
	111	.type = CLK_TYPE_PERIPHERAL,
	112	};
e8788bab AV	113	static struct clk ssc0_clk = {
	114	.name = "ssc0_clk",
	115	.pmc_mask = 1 << AT91SAM9263_ID_SSC0,
	116	.type = CLK_TYPE_PERIPHERAL,
	117	};
	118	static struct clk ssc1_clk = {
	119	.name = "ssc1_clk",
	120	.pmc_mask = 1 << AT91SAM9263_ID_SSC1,
	121	.type = CLK_TYPE_PERIPHERAL,
	122	};
	123	static struct clk ac97_clk = {
	124	.name = "ac97_clk",
	125	.pmc_mask = 1 << AT91SAM9263_ID_AC97C,
	126	.type = CLK_TYPE_PERIPHERAL,
	127	};
b2c65616 AV	128	static struct clk tcb_clk = {
	129	.name = "tcb_clk",
	130	.pmc_mask = 1 << AT91SAM9263_ID_TCB,
	131	.type = CLK_TYPE_PERIPHERAL,
	132	};
bb1ad68b AV	133	static struct clk pwm_clk = {
bb1ad68b AV	134	.name = "pwm_clk",
e8788bab AV	135	.pmc_mask = 1 << AT91SAM9263_ID_PWMC,
	136	.type = CLK_TYPE_PERIPHERAL,
	137	};
69b2e99c AV	138	static struct clk macb_clk = {
69b2e99c AV	139	.name = "macb_clk",
b2c65616 AV	140	.pmc_mask = 1 << AT91SAM9263_ID_EMAC,
	141	.type = CLK_TYPE_PERIPHERAL,
	142	};
e8788bab AV	143	static struct clk dma_clk = {
	144	.name = "dma_clk",
	145	.pmc_mask = 1 << AT91SAM9263_ID_DMA,
	146	.type = CLK_TYPE_PERIPHERAL,
	147	};
	148	static struct clk twodge_clk = {
	149	.name = "2dge_clk",
	150	.pmc_mask = 1 << AT91SAM9263_ID_2DGE,
	151	.type = CLK_TYPE_PERIPHERAL,
	152	};
b2c65616 AV	153	static struct clk udc_clk = {
	154	.name = "udc_clk",
	155	.pmc_mask = 1 << AT91SAM9263_ID_UDP,
	156	.type = CLK_TYPE_PERIPHERAL,
	157	};
	158	static struct clk isi_clk = {
	159	.name = "isi_clk",
	160	.pmc_mask = 1 << AT91SAM9263_ID_ISI,
	161	.type = CLK_TYPE_PERIPHERAL,
	162	};
	163	static struct clk lcdc_clk = {
	164	.name = "lcdc_clk",
7f6e2d99	165	.pmc_mask = 1 << AT91SAM9263_ID_LCDC,
b2c65616 AV	166	.type = CLK_TYPE_PERIPHERAL,
	167	};
	168	static struct clk ohci_clk = {
	169	.name = "ohci_clk",
	170	.pmc_mask = 1 << AT91SAM9263_ID_UHP,
	171	.type = CLK_TYPE_PERIPHERAL,
	172	};
	173
	174	static struct clk *periph_clocks[] __initdata = {
	175	&pioA_clk,
	176	&pioB_clk,
	177	&pioCDE_clk,
	178	&usart0_clk,
	179	&usart1_clk,
	180	&usart2_clk,
	181	&mmc0_clk,
	182	&mmc1_clk,
e8788bab	183	&can_clk,
b2c65616 AV	184	&twi_clk,
	185	&spi0_clk,
	186	&spi1_clk,
e8788bab AV	187	&ssc0_clk,
	188	&ssc1_clk,
	189	&ac97_clk,
b2c65616	190	&tcb_clk,
bb1ad68b	191	&pwm_clk,
69b2e99c	192	&macb_clk,
e8788bab	193	&twodge_clk,
b2c65616 AV	194	&udc_clk,
	195	&isi_clk,
	196	&lcdc_clk,
e8788bab	197	&dma_clk,
b2c65616 AV	198	&ohci_clk,
	199	// irq0 .. irq1
	200	};
	201
	202	/*
	203	* The four programmable clocks.
	204	* You must configure pin multiplexing to bring these signals out.
	205	*/
	206	static struct clk pck0 = {
	207	.name = "pck0",
	208	.pmc_mask = AT91_PMC_PCK0,
	209	.type = CLK_TYPE_PROGRAMMABLE,
	210	.id = 0,
	211	};
	212	static struct clk pck1 = {
	213	.name = "pck1",
	214	.pmc_mask = AT91_PMC_PCK1,
	215	.type = CLK_TYPE_PROGRAMMABLE,
	216	.id = 1,
	217	};
	218	static struct clk pck2 = {
	219	.name = "pck2",
	220	.pmc_mask = AT91_PMC_PCK2,
	221	.type = CLK_TYPE_PROGRAMMABLE,
	222	.id = 2,
	223	};
	224	static struct clk pck3 = {
	225	.name = "pck3",
	226	.pmc_mask = AT91_PMC_PCK3,
	227	.type = CLK_TYPE_PROGRAMMABLE,
	228	.id = 3,
	229	};
	230
	231	static void __init at91sam9263_register_clocks(void)
	232	{
	233	int i;
	234
	235	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	236	clk_register(periph_clocks[i]);
	237
	238	clk_register(&pck0);
	239	clk_register(&pck1);
	240	clk_register(&pck2);
	241	clk_register(&pck3);
	242	}
	243
	244	/* --------------------------------------------------------------------
	245	* GPIO
	246	* -------------------------------------------------------------------- */
	247
	248	static struct at91_gpio_bank at91sam9263_gpio[] = {
	249	{
	250	.id = AT91SAM9263_ID_PIOA,
	251	.offset = AT91_PIOA,
	252	.clock = &pioA_clk,
	253	}, {
	254	.id = AT91SAM9263_ID_PIOB,
	255	.offset = AT91_PIOB,
	256	.clock = &pioB_clk,
	257	}, {
	258	.id = AT91SAM9263_ID_PIOCDE,
	259	.offset = AT91_PIOC,
	260	.clock = &pioCDE_clk,
	261	}, {
262	.id = AT91SAM9263_ID_PIOCDE,
263	.offset = AT91_PIOD,
264	.clock = &pioCDE_clk,
265	}, {
266	.id = AT91SAM9263_ID_PIOCDE,
267	.offset = AT91_PIOE,
268	.clock = &pioCDE_clk,
269	}
270	};
271
3ef2fb42 AV	272	static void at91sam9263_poweroff(void)
	273	{
	274	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY \| AT91_SHDW_SHDW);
	275	}
	276
b2c65616 AV	277
	278	/* --------------------------------------------------------------------
	279	* AT91SAM9263 processor initialization
	280	* -------------------------------------------------------------------- */
	281
	282	void __init at91sam9263_initialize(unsigned long main_clock)
	283	{
	284	/* Map peripherals */
	285	iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
	286
bb413db5	287	at91_arch_reset = at91sam9_alt_reset;
3ef2fb42	288	pm_power_off = at91sam9263_poweroff;
b2c65616 AV	289	at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) \| (1 << AT91SAM9263_ID_IRQ1);
	290
	291	/* Init clock subsystem */
	292	at91_clock_init(main_clock);
	293
	294	/* Register the processor-specific clocks */
	295	at91sam9263_register_clocks();
	296
	297	/* Register GPIO subsystem */
	298	at91_gpio_init(at91sam9263_gpio, 5);
	299	}
	300
	301	/* --------------------------------------------------------------------
	302	* Interrupt initialization
	303	* -------------------------------------------------------------------- */
	304
	305	/*
	306	* The default interrupt priority levels (0 = lowest, 7 = highest).
	307	*/
	308	static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
	309	7, /* Advanced Interrupt Controller (FIQ) */
	310	7, /* System Peripherals */
7cbed2b5 AV	311	1, /* Parallel IO Controller A */
	312	1, /* Parallel IO Controller B */
	313	1, /* Parallel IO Controller C, D and E */
b2c65616 AV	314	0,
b2c65616 AV	315	0,
7cbed2b5 AV	316	5, /* USART 0 */
	317	5, /* USART 1 */
	318	5, /* USART 2 */
b2c65616 AV	319	0, /* Multimedia Card Interface 0 */
b2c65616 AV	320	0, /* Multimedia Card Interface 1 */
7cbed2b5 AV	321	3, /* CAN */
	322	6, /* Two-Wire Interface */
	323	5, /* Serial Peripheral Interface 0 */
	324	5, /* Serial Peripheral Interface 1 */
	325	4, /* Serial Synchronous Controller 0 */
	326	4, /* Serial Synchronous Controller 1 */
	327	5, /* AC97 Controller */
b2c65616 AV	328	0, /* Timer Counter 0, 1 and 2 */
	329	0, /* Pulse Width Modulation Controller */
	330	3, /* Ethernet */
	331	0,
	332	0, /* 2D Graphic Engine */
7cbed2b5	333	2, /* USB Device Port */
b2c65616 AV	334	0, /* Image Sensor Interface */
	335	3, /* LDC Controller */
	336	0, /* DMA Controller */
	337	0,
7cbed2b5	338	2, /* USB Host port */
b2c65616 AV	339	0, /* Advanced Interrupt Controller (IRQ0) */
	340	0, /* Advanced Interrupt Controller (IRQ1) */
	341	};
	342
	343	void __init at91sam9263_init_interrupts(unsigned int priority[NR_AIC_IRQS])
	344	{
	345	if (!priority)
	346	priority = at91sam9263_default_irq_priority;
	347
	348	/* Initialize the AIC interrupt controller */
	349	at91_aic_init(priority);
	350
	351	/* Enable GPIO interrupts */
	352	at91_gpio_irq_setup();
	353	}