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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-at91 / at91sam9261_devices.c
CommitLineData
86ad76bb 1/*
9d041268 2 * arch/arm/mach-at91/at91sam9261_devices.c
86ad76bb
AV		 3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15
c6686ff9 16#include <linux/dma-mapping.h>
2f8163ba 17#include <linux/gpio.h>
86ad76bb 18#include <linux/platform_device.h>
f230d3f5 19#include <linux/i2c-gpio.h>
86ad76bb 20
f230d3f5 21#include <linux/fb.h>
b8b78609
JA		 22#include <video/atmel_lcdc.h>
23
a09e64fb
RK		 24#include <mach/at91sam9261.h>
25#include <mach/at91sam9261_matrix.h>
4342d647 26#include <mach/at91_matrix.h>
a09e64fb 27#include <mach/at91sam9_smc.h>
86ad76bb 28
43d2f532 29#include "board.h"
86ad76bb
AV		 30#include "generic.h"
31
86ad76bb
AV		 32
33/* --------------------------------------------------------------------
34 * USB Host
35 * -------------------------------------------------------------------- */
36
37#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
c6686ff9 38static u64 ohci_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 39static struct at91_usbh_data usbh_data;
40
41static struct resource usbh_resources[] = {
42 [0] = {
43 .start = AT91SAM9261_UHP_BASE,
44 .end = AT91SAM9261_UHP_BASE + SZ_1M - 1,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
8fe82a55
LD		 48 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
49 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
86ad76bb
AV		 50 .flags = IORESOURCE_IRQ,
51 },
52};
53
54static struct platform_device at91sam9261_usbh_device = {
55 .name = "at91_ohci",
56 .id = -1,
57 .dev = {
58 .dma_mask = &ohci_dmamask,
c6686ff9 59 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 60 .platform_data = &usbh_data,
61 },
62 .resource = usbh_resources,
63 .num_resources = ARRAY_SIZE(usbh_resources),
64};
65
66void __init at91_add_device_usbh(struct at91_usbh_data *data)
67{
1fcaea7e
TP		 68 int i;
69
86ad76bb
AV		 70 if (!data)
71 return;
72
1fcaea7e
TP		 73 /* Enable overcurrent notification */
74 for (i = 0; i < data->ports; i++) {
641f3ce6 75 if (gpio_is_valid(data->overcurrent_pin[i]))
1fcaea7e
TP		 76 at91_set_gpio_input(data->overcurrent_pin[i], 1);
77 }
78
86ad76bb
AV		 79 usbh_data = *data;
80 platform_device_register(&at91sam9261_usbh_device);
81}
82#else
83void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84#endif
85
86
87/* --------------------------------------------------------------------
88 * USB Device (Gadget)
89 * -------------------------------------------------------------------- */
90
e8c9dc93 91#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
86ad76bb
AV		 92static struct at91_udc_data udc_data;
93
94static struct resource udc_resources[] = {
95 [0] = {
96 .start = AT91SAM9261_BASE_UDP,
97 .end = AT91SAM9261_BASE_UDP + SZ_16K - 1,
98 .flags = IORESOURCE_MEM,
99 },
100 [1] = {
8fe82a55
LD		 101 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
102 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
86ad76bb
AV		 103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device at91sam9261_udc_device = {
108 .name = "at91_udc",
109 .id = -1,
110 .dev = {
111 .platform_data = &udc_data,
112 },
113 .resource = udc_resources,
114 .num_resources = ARRAY_SIZE(udc_resources),
115};
116
117void __init at91_add_device_udc(struct at91_udc_data *data)
118{
86ad76bb
AV		 119 if (!data)
120 return;
121
cc9f9aef 122 if (gpio_is_valid(data->vbus_pin)) {
86ad76bb
AV		 123 at91_set_gpio_input(data->vbus_pin, 0);
124 at91_set_deglitch(data->vbus_pin, 1);
125 }
126
da7a42d6 127 /* Pullup pin is handled internally by USB device peripheral */
86ad76bb
AV		 128
129 udc_data = *data;
130 platform_device_register(&at91sam9261_udc_device);
131}
132#else
133void __init at91_add_device_udc(struct at91_udc_data *data) {}
134#endif
135
136/* --------------------------------------------------------------------
137 * MMC / SD
138 * -------------------------------------------------------------------- */
139
4cf3326a 140#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
c6686ff9 141static u64 mmc_dmamask = DMA_BIT_MASK(32);
4cf3326a 142static struct mci_platform_data mmc_data;
86ad76bb
AV		 143
144static struct resource mmc_resources[] = {
145 [0] = {
146 .start = AT91SAM9261_BASE_MCI,
147 .end = AT91SAM9261_BASE_MCI + SZ_16K - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
8fe82a55
LD		 151 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
152 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
86ad76bb
AV		 153 .flags = IORESOURCE_IRQ,
154 },
155};
156
157static struct platform_device at91sam9261_mmc_device = {
4cf3326a 158 .name = "atmel_mci",
86ad76bb
AV		 159 .id = -1,
160 .dev = {
161 .dma_mask = &mmc_dmamask,
c6686ff9 162 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 163 .platform_data = &mmc_data,
164 },
165 .resource = mmc_resources,
166 .num_resources = ARRAY_SIZE(mmc_resources),
167};
168
4cf3326a 169void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
86ad76bb
AV		 170{
171 if (!data)
172 return;
173
4cf3326a
LD		 174 if (data->slot[0].bus_width) {
175 /* input/irq */
176 if (gpio_is_valid(data->slot[0].detect_pin)) {
177 at91_set_gpio_input(data->slot[0].detect_pin, 1);
178 at91_set_deglitch(data->slot[0].detect_pin, 1);
179 }
180 if (gpio_is_valid(data->slot[0].wp_pin))
181 at91_set_gpio_input(data->slot[0].wp_pin, 1);
182
183 /* CLK */
184 at91_set_B_periph(AT91_PIN_PA2, 0);
185
186 /* CMD */
187 at91_set_B_periph(AT91_PIN_PA1, 1);
188
189 /* DAT0, maybe DAT1..DAT3 */
190 at91_set_B_periph(AT91_PIN_PA0, 1);
191 if (data->slot[0].bus_width == 4) {
192 at91_set_B_periph(AT91_PIN_PA4, 1);
193 at91_set_B_periph(AT91_PIN_PA5, 1);
194 at91_set_B_periph(AT91_PIN_PA6, 1);
195 }
196
197 mmc_data = *data;
198 platform_device_register(&at91sam9261_mmc_device);
86ad76bb 199 }
86ad76bb
AV		 200}
201#else
4cf3326a 202void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
86ad76bb
AV		 203#endif
204
205
206/* --------------------------------------------------------------------
207 * NAND / SmartMedia
208 * -------------------------------------------------------------------- */
209
f6ed6f78 210#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 211static struct atmel_nand_data nand_data;
86ad76bb
AV		 212
213#define NAND_BASE AT91_CHIPSELECT_3
214
215static struct resource nand_resources[] = {
216 {
217 .start = NAND_BASE,
218 .end = NAND_BASE + SZ_256M - 1,
219 .flags = IORESOURCE_MEM,
220 }
221};
222
3c3796cc
HS		 223static struct platform_device atmel_nand_device = {
224 .name = "atmel_nand",
86ad76bb
AV		 225 .id = -1,
226 .dev = {
227 .platform_data = &nand_data,
228 },
229 .resource = nand_resources,
230 .num_resources = ARRAY_SIZE(nand_resources),
231};
232
3c3796cc 233void __init at91_add_device_nand(struct atmel_nand_data *data)
86ad76bb 234{
461d3b4d 235 unsigned long csa;
86ad76bb
AV		 236
237 if (!data)
238 return;
239
4342d647
JCPV		 240 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
241 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
86ad76bb 242
86ad76bb 243 /* enable pin */
cc9f9aef 244 if (gpio_is_valid(data->enable_pin))
86ad76bb
AV		 245 at91_set_gpio_output(data->enable_pin, 1);
246
247 /* ready/busy pin */
cc9f9aef 248 if (gpio_is_valid(data->rdy_pin))
86ad76bb
AV		 249 at91_set_gpio_input(data->rdy_pin, 1);
250
251 /* card detect pin */
cc9f9aef 252 if (gpio_is_valid(data->det_pin))
86ad76bb
AV		 253 at91_set_gpio_input(data->det_pin, 1);
254
255 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
256 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
257
258 nand_data = *data;
3c3796cc 259 platform_device_register(&atmel_nand_device);
86ad76bb
AV		 260}
261
262#else
3c3796cc 263void __init at91_add_device_nand(struct atmel_nand_data *data) {}
86ad76bb
AV		 264#endif
265
266
267/* --------------------------------------------------------------------
268 * TWI (i2c)
269 * -------------------------------------------------------------------- */
270
f230d3f5
AV		 271/*
272 * Prefer the GPIO code since the TWI controller isn't robust
273 * (gets overruns and underruns under load) and can only issue
274 * repeated STARTs in one scenario (the driver doesn't yet handle them).
275 */
276#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
277
278static struct i2c_gpio_platform_data pdata = {
279 .sda_pin = AT91_PIN_PA7,
280 .sda_is_open_drain = 1,
281 .scl_pin = AT91_PIN_PA8,
282 .scl_is_open_drain = 1,
283 .udelay = 2, /* ~100 kHz */
284};
285
286static struct platform_device at91sam9261_twi_device = {
287 .name = "i2c-gpio",
7840487c 288 .id = 0,
f230d3f5
AV		 289 .dev.platform_data = &pdata,
290};
291
292void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
293{
294 at91_set_GPIO_periph(AT91_PIN_PA7, 1); /* TWD (SDA) */
295 at91_set_multi_drive(AT91_PIN_PA7, 1);
296
297 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
298 at91_set_multi_drive(AT91_PIN_PA8, 1);
299
300 i2c_register_board_info(0, devices, nr_devices);
301 platform_device_register(&at91sam9261_twi_device);
302}
303
304#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
86ad76bb
AV		 305
306static struct resource twi_resources[] = {
307 [0] = {
308 .start = AT91SAM9261_BASE_TWI,
309 .end = AT91SAM9261_BASE_TWI + SZ_16K - 1,
310 .flags = IORESOURCE_MEM,
311 },
312 [1] = {
8fe82a55
LD		 313 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
314 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
86ad76bb
AV		 315 .flags = IORESOURCE_IRQ,
316 },
317};
318
319static struct platform_device at91sam9261_twi_device = {
302090a6 320 .id = 0,
86ad76bb
AV		 321 .resource = twi_resources,
322 .num_resources = ARRAY_SIZE(twi_resources),
323};
324
f230d3f5 325void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
86ad76bb 326{
fac368a0
NV		 327 /* IP version is not the same on 9261 and g10 */
328 if (cpu_is_at91sam9g10()) {
329 at91sam9261_twi_device.name = "i2c-at91sam9g10";
94e73465 330 /* I2C PIO must not be configured as open-drain on this chip */
fac368a0
NV		 331 } else {
332 at91sam9261_twi_device.name = "i2c-at91sam9261";
94e73465
LD		 333 at91_set_multi_drive(AT91_PIN_PA7, 1);
334 at91_set_multi_drive(AT91_PIN_PA8, 1);
fac368a0
NV		 335 }
336
86ad76bb
AV		 337 /* pins used for TWI interface */
338 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */
86ad76bb 339 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */
86ad76bb 340
f230d3f5 341 i2c_register_board_info(0, devices, nr_devices);
86ad76bb
AV		 342 platform_device_register(&at91sam9261_twi_device);
343}
344#else
f230d3f5 345void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
86ad76bb
AV		 346#endif
347
348
349/* --------------------------------------------------------------------
350 * SPI
351 * -------------------------------------------------------------------- */
352
353#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 354static u64 spi_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 355
356static struct resource spi0_resources[] = {
357 [0] = {
358 .start = AT91SAM9261_BASE_SPI0,
359 .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
360 .flags = IORESOURCE_MEM,
361 },
362 [1] = {
8fe82a55
LD		 363 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
364 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
86ad76bb
AV		 365 .flags = IORESOURCE_IRQ,
366 },
367};
368
369static struct platform_device at91sam9261_spi0_device = {
370 .name = "atmel_spi",
371 .id = 0,
372 .dev = {
373 .dma_mask = &spi_dmamask,
c6686ff9 374 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 375 },
376 .resource = spi0_resources,
377 .num_resources = ARRAY_SIZE(spi0_resources),
378};
379
380static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
381
382static struct resource spi1_resources[] = {
383 [0] = {
384 .start = AT91SAM9261_BASE_SPI1,
385 .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
8fe82a55
LD		 389 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
390 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
86ad76bb
AV		 391 .flags = IORESOURCE_IRQ,
392 },
393};
394
395static struct platform_device at91sam9261_spi1_device = {
396 .name = "atmel_spi",
397 .id = 1,
398 .dev = {
399 .dma_mask = &spi_dmamask,
c6686ff9 400 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 401 },
402 .resource = spi1_resources,
403 .num_resources = ARRAY_SIZE(spi1_resources),
404};
405
406static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
407
408void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
409{
410 int i;
411 unsigned long cs_pin;
412 short enable_spi0 = 0;
413 short enable_spi1 = 0;
414
415 /* Choose SPI chip-selects */
416 for (i = 0; i < nr_devices; i++) {
417 if (devices[i].controller_data)
418 cs_pin = (unsigned long) devices[i].controller_data;
419 else if (devices[i].bus_num == 0)
420 cs_pin = spi0_standard_cs[devices[i].chip_select];
421 else
422 cs_pin = spi1_standard_cs[devices[i].chip_select];
423
0c2c1f62
NF		 424 if (!gpio_is_valid(cs_pin))
425 continue;
426
86ad76bb
AV		 427 if (devices[i].bus_num == 0)
428 enable_spi0 = 1;
429 else
430 enable_spi1 = 1;
431
432 /* enable chip-select pin */
433 at91_set_gpio_output(cs_pin, 1);
434
435 /* pass chip-select pin to driver */
436 devices[i].controller_data = (void *) cs_pin;
437 }
438
439 spi_register_board_info(devices, nr_devices);
440
441 /* Configure SPI bus(es) */
442 if (enable_spi0) {
443 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
444 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
445 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
446
86ad76bb
AV		 447 platform_device_register(&at91sam9261_spi0_device);
448 }
449 if (enable_spi1) {
450 at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
451 at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
452 at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
453
86ad76bb
AV		 454 platform_device_register(&at91sam9261_spi1_device);
455 }
456}
457#else
458void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
459#endif
460
461
462/* --------------------------------------------------------------------
463 * LCD Controller
464 * -------------------------------------------------------------------- */
465
7776a94c 466#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
c6686ff9 467static u64 lcdc_dmamask = DMA_BIT_MASK(32);
7776a94c 468static struct atmel_lcdfb_info lcdc_data;
86ad76bb
AV		 469
470static struct resource lcdc_resources[] = {
471 [0] = {
472 .start = AT91SAM9261_LCDC_BASE,
473 .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
474 .flags = IORESOURCE_MEM,
475 },
476 [1] = {
8fe82a55
LD		 477 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
478 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
86ad76bb
AV		 479 .flags = IORESOURCE_IRQ,
480 },
481#if defined(CONFIG_FB_INTSRAM)
482 [2] = {
483 .start = AT91SAM9261_SRAM_BASE,
484 .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
485 .flags = IORESOURCE_MEM,
486 },
487#endif
488};
489
490static struct platform_device at91_lcdc_device = {
86ad76bb
AV		 491 .id = 0,
492 .dev = {
493 .dma_mask = &lcdc_dmamask,
c6686ff9 494 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 495 .platform_data = &lcdc_data,
496 },
497 .resource = lcdc_resources,
498 .num_resources = ARRAY_SIZE(lcdc_resources),
499};
500
7776a94c 501void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
86ad76bb
AV		 502{
503 if (!data) {
504 return;
505 }
506
bbd44f6b
JH		 507 if (cpu_is_at91sam9g10())
508 at91_lcdc_device.name = "at91sam9g10-lcdfb";
509 else
510 at91_lcdc_device.name = "at91sam9261-lcdfb";
511
f06e656f
AV		 512#if defined(CONFIG_FB_ATMEL_STN)
513 at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
514 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
515 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
516 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
517 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
518 at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */
519 at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */
520 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
521 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
522#else
86ad76bb
AV		 523 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
524 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
525 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
526 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
527 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
528 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
529 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
530 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
531 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
532 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
533 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
534 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
535 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
536 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
537 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
538 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
539 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
540 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
541 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
542 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
543 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
544 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
f06e656f 545#endif
86ad76bb 546
01d3a5e7
HS		 547 if (ARRAY_SIZE(lcdc_resources) > 2) {
548 void __iomem *fb;
549 struct resource *fb_res = &lcdc_resources[2];
28f65c11 550 size_t fb_len = resource_size(fb_res);
01d3a5e7 551
90898709 552 fb = ioremap(fb_res->start, fb_len);
01d3a5e7
HS		 553 if (fb) {
554 memset(fb, 0, fb_len);
90898709 555 iounmap(fb);
01d3a5e7
HS		 556 }
557 }
86ad76bb
AV		 558 lcdc_data = *data;
559 platform_device_register(&at91_lcdc_device);
560}
561#else
7776a94c 562void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
86ad76bb
AV		 563#endif
564
565
e5f40bfa
AV		 566/* --------------------------------------------------------------------
567 * Timer/Counter block
568 * -------------------------------------------------------------------- */
569
570#ifdef CONFIG_ATMEL_TCLIB
571
572static struct resource tcb_resources[] = {
573 [0] = {
574 .start = AT91SAM9261_BASE_TCB0,
575 .end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
576 .flags = IORESOURCE_MEM,
577 },
578 [1] = {
8fe82a55
LD		 579 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
580 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
e5f40bfa
AV		 581 .flags = IORESOURCE_IRQ,
582 },
583 [2] = {
8fe82a55
LD		 584 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
585 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
e5f40bfa
AV		 586 .flags = IORESOURCE_IRQ,
587 },
588 [3] = {
8fe82a55
LD		 589 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
590 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
e5f40bfa
AV		 591 .flags = IORESOURCE_IRQ,
592 },
593};
594
595static struct platform_device at91sam9261_tcb_device = {
596 .name = "atmel_tcb",
597 .id = 0,
598 .resource = tcb_resources,
599 .num_resources = ARRAY_SIZE(tcb_resources),
600};
601
602static void __init at91_add_device_tc(void)
603{
e5f40bfa
AV		 604 platform_device_register(&at91sam9261_tcb_device);
605}
606#else
607static void __init at91_add_device_tc(void) { }
608#endif
609
610
884f5a6a
AV		 611/* --------------------------------------------------------------------
612 * RTT
613 * -------------------------------------------------------------------- */
614
615static struct resource rtt_resources[] = {
616 {
eab5fd67
JCPV		 617 .start = AT91SAM9261_BASE_RTT,
618 .end = AT91SAM9261_BASE_RTT + SZ_16 - 1,
884f5a6a 619 .flags = IORESOURCE_MEM,
b3af8b49
JCPV		 620 }, {
621 .flags = IORESOURCE_MEM,
e402af6c
LD		 622 }, {
623 .flags = IORESOURCE_IRQ,
884f5a6a
AV		 624 }
625};
626
627static struct platform_device at91sam9261_rtt_device = {
628 .name = "at91_rtt",
4fd9212c 629 .id = 0,
884f5a6a 630 .resource = rtt_resources,
884f5a6a
AV		 631};
632
205056a3
JCPV		 633#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
634static void __init at91_add_device_rtt_rtc(void)
635{
636 at91sam9261_rtt_device.name = "rtc-at91sam9";
b3af8b49
JCPV		 637 /*
638 * The second resource is needed:
639 * GPBR will serve as the storage for RTC time offset
640 */
e402af6c 641 at91sam9261_rtt_device.num_resources = 3;
b3af8b49
JCPV		 642 rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
643 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
644 rtt_resources[1].end = rtt_resources[1].start + 3;
e402af6c
LD		 645 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
646 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
205056a3
JCPV		 647}
648#else
b3af8b49
JCPV		 649static void __init at91_add_device_rtt_rtc(void)
650{
651 /* Only one resource is needed: RTT not used as RTC */
652 at91sam9261_rtt_device.num_resources = 1;
653}
205056a3
JCPV		 654#endif
655
884f5a6a
AV		 656static void __init at91_add_device_rtt(void)
657{
205056a3 658 at91_add_device_rtt_rtc();
884f5a6a
AV		 659 platform_device_register(&at91sam9261_rtt_device);
660}
661
662
663/* --------------------------------------------------------------------
664 * Watchdog
665 * -------------------------------------------------------------------- */
666
2af29b78 667#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
c1c30a29
JCPV		 668static struct resource wdt_resources[] = {
669 {
670 .start = AT91SAM9261_BASE_WDT,
671 .end = AT91SAM9261_BASE_WDT + SZ_16 - 1,
672 .flags = IORESOURCE_MEM,
673 }
674};
675
884f5a6a
AV		 676static struct platform_device at91sam9261_wdt_device = {
677 .name = "at91_wdt",
678 .id = -1,
c1c30a29
JCPV		 679 .resource = wdt_resources,
680 .num_resources = ARRAY_SIZE(wdt_resources),
884f5a6a
AV		 681};
682
683static void __init at91_add_device_watchdog(void)
684{
685 platform_device_register(&at91sam9261_wdt_device);
686}
687#else
688static void __init at91_add_device_watchdog(void) {}
689#endif
690
691
bfbc3266
AV		 692/* --------------------------------------------------------------------
693 * SSC -- Synchronous Serial Controller
694 * -------------------------------------------------------------------- */
695
696#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
697static u64 ssc0_dmamask = DMA_BIT_MASK(32);
698
699static struct resource ssc0_resources[] = {
700 [0] = {
701 .start = AT91SAM9261_BASE_SSC0,
702 .end = AT91SAM9261_BASE_SSC0 + SZ_16K - 1,
703 .flags = IORESOURCE_MEM,
704 },
705 [1] = {
8fe82a55
LD		 706 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
707 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
bfbc3266
AV		 708 .flags = IORESOURCE_IRQ,
709 },
710};
711
712static struct platform_device at91sam9261_ssc0_device = {
636036d2 713 .name = "at91rm9200_ssc",
bfbc3266
AV		 714 .id = 0,
715 .dev = {
716 .dma_mask = &ssc0_dmamask,
717 .coherent_dma_mask = DMA_BIT_MASK(32),
718 },
719 .resource = ssc0_resources,
720 .num_resources = ARRAY_SIZE(ssc0_resources),
721};
722
723static inline void configure_ssc0_pins(unsigned pins)
724{
725 if (pins & ATMEL_SSC_TF)
726 at91_set_A_periph(AT91_PIN_PB21, 1);
727 if (pins & ATMEL_SSC_TK)
728 at91_set_A_periph(AT91_PIN_PB22, 1);
729 if (pins & ATMEL_SSC_TD)
730 at91_set_A_periph(AT91_PIN_PB23, 1);
731 if (pins & ATMEL_SSC_RD)
732 at91_set_A_periph(AT91_PIN_PB24, 1);
733 if (pins & ATMEL_SSC_RK)
734 at91_set_A_periph(AT91_PIN_PB25, 1);
735 if (pins & ATMEL_SSC_RF)
736 at91_set_A_periph(AT91_PIN_PB26, 1);
737}
738
739static u64 ssc1_dmamask = DMA_BIT_MASK(32);
740
741static struct resource ssc1_resources[] = {
742 [0] = {
743 .start = AT91SAM9261_BASE_SSC1,
744 .end = AT91SAM9261_BASE_SSC1 + SZ_16K - 1,
745 .flags = IORESOURCE_MEM,
746 },
747 [1] = {
8fe82a55
LD		 748 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
749 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
bfbc3266
AV		 750 .flags = IORESOURCE_IRQ,
751 },
752};
753
754static struct platform_device at91sam9261_ssc1_device = {
636036d2 755 .name = "at91rm9200_ssc",
bfbc3266
AV		 756 .id = 1,
757 .dev = {
758 .dma_mask = &ssc1_dmamask,
759 .coherent_dma_mask = DMA_BIT_MASK(32),
760 },
761 .resource = ssc1_resources,
762 .num_resources = ARRAY_SIZE(ssc1_resources),
763};
764
765static inline void configure_ssc1_pins(unsigned pins)
766{
767 if (pins & ATMEL_SSC_TF)
768 at91_set_B_periph(AT91_PIN_PA17, 1);
769 if (pins & ATMEL_SSC_TK)
770 at91_set_B_periph(AT91_PIN_PA18, 1);
771 if (pins & ATMEL_SSC_TD)
772 at91_set_B_periph(AT91_PIN_PA19, 1);
773 if (pins & ATMEL_SSC_RD)
774 at91_set_B_periph(AT91_PIN_PA20, 1);
775 if (pins & ATMEL_SSC_RK)
776 at91_set_B_periph(AT91_PIN_PA21, 1);
777 if (pins & ATMEL_SSC_RF)
778 at91_set_B_periph(AT91_PIN_PA22, 1);
779}
780
781static u64 ssc2_dmamask = DMA_BIT_MASK(32);
782
783static struct resource ssc2_resources[] = {
784 [0] = {
785 .start = AT91SAM9261_BASE_SSC2,
786 .end = AT91SAM9261_BASE_SSC2 + SZ_16K - 1,
787 .flags = IORESOURCE_MEM,
788 },
789 [1] = {
8fe82a55
LD		 790 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
791 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
bfbc3266
AV		 792 .flags = IORESOURCE_IRQ,
793 },
794};
795
796static struct platform_device at91sam9261_ssc2_device = {
636036d2 797 .name = "at91rm9200_ssc",
bfbc3266
AV		 798 .id = 2,
799 .dev = {
800 .dma_mask = &ssc2_dmamask,
801 .coherent_dma_mask = DMA_BIT_MASK(32),
802 },
803 .resource = ssc2_resources,
804 .num_resources = ARRAY_SIZE(ssc2_resources),
805};
806
807static inline void configure_ssc2_pins(unsigned pins)
808{
809 if (pins & ATMEL_SSC_TF)
810 at91_set_B_periph(AT91_PIN_PC25, 1);
811 if (pins & ATMEL_SSC_TK)
812 at91_set_B_periph(AT91_PIN_PC26, 1);
813 if (pins & ATMEL_SSC_TD)
814 at91_set_B_periph(AT91_PIN_PC27, 1);
815 if (pins & ATMEL_SSC_RD)
816 at91_set_B_periph(AT91_PIN_PC28, 1);
817 if (pins & ATMEL_SSC_RK)
818 at91_set_B_periph(AT91_PIN_PC29, 1);
819 if (pins & ATMEL_SSC_RF)
820 at91_set_B_periph(AT91_PIN_PC30, 1);
821}
822
823/*
824 * SSC controllers are accessed through library code, instead of any
825 * kind of all-singing/all-dancing driver. For example one could be
826 * used by a particular I2S audio codec's driver, while another one
827 * on the same system might be used by a custom data capture driver.
828 */
829void __init at91_add_device_ssc(unsigned id, unsigned pins)
830{
831 struct platform_device *pdev;
832
833 /*
834 * NOTE: caller is responsible for passing information matching
835 * "pins" to whatever will be using each particular controller.
836 */
837 switch (id) {
838 case AT91SAM9261_ID_SSC0:
839 pdev = &at91sam9261_ssc0_device;
840 configure_ssc0_pins(pins);
bfbc3266
AV		 841 break;
842 case AT91SAM9261_ID_SSC1:
843 pdev = &at91sam9261_ssc1_device;
844 configure_ssc1_pins(pins);
bfbc3266
AV		 845 break;
846 case AT91SAM9261_ID_SSC2:
847 pdev = &at91sam9261_ssc2_device;
848 configure_ssc2_pins(pins);
bfbc3266
AV		 849 break;
850 default:
851 return;
852 }
853
854 platform_device_register(pdev);
855}
856
857#else
858void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
859#endif
860
861
86ad76bb
AV		 862/* --------------------------------------------------------------------
863 * UART
864 * -------------------------------------------------------------------- */
865
866#if defined(CONFIG_SERIAL_ATMEL)
867static struct resource dbgu_resources[] = {
868 [0] = {
13079a73
JCPV		 869 .start = AT91SAM9261_BASE_DBGU,
870 .end = AT91SAM9261_BASE_DBGU + SZ_512 - 1,
86ad76bb
AV		 871 .flags = IORESOURCE_MEM,
872 },
873 [1] = {
8fe82a55
LD		 874 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
875 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
86ad76bb
AV		 876 .flags = IORESOURCE_IRQ,
877 },
878};
879
880static struct atmel_uart_data dbgu_data = {
881 .use_dma_tx = 0,
882 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
86ad76bb
AV		 883};
884
c6686ff9
AV		 885static u64 dbgu_dmamask = DMA_BIT_MASK(32);
886
86ad76bb
AV		 887static struct platform_device at91sam9261_dbgu_device = {
888 .name = "atmel_usart",
889 .id = 0,
890 .dev = {
c6686ff9
AV		 891 .dma_mask = &dbgu_dmamask,
892 .coherent_dma_mask = DMA_BIT_MASK(32),
893 .platform_data = &dbgu_data,
86ad76bb
AV		 894 },
895 .resource = dbgu_resources,
896 .num_resources = ARRAY_SIZE(dbgu_resources),
897};
898
899static inline void configure_dbgu_pins(void)
900{
901 at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
902 at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
903}
904
905static struct resource uart0_resources[] = {
906 [0] = {
907 .start = AT91SAM9261_BASE_US0,
908 .end = AT91SAM9261_BASE_US0 + SZ_16K - 1,
909 .flags = IORESOURCE_MEM,
910 },
911 [1] = {
8fe82a55
LD		 912 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
913 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
86ad76bb
AV		 914 .flags = IORESOURCE_IRQ,
915 },
916};
917
918static struct atmel_uart_data uart0_data = {
919 .use_dma_tx = 1,
920 .use_dma_rx = 1,
921};
922
c6686ff9
AV		 923static u64 uart0_dmamask = DMA_BIT_MASK(32);
924
86ad76bb
AV		 925static struct platform_device at91sam9261_uart0_device = {
926 .name = "atmel_usart",
927 .id = 1,
928 .dev = {
c6686ff9
AV		 929 .dma_mask = &uart0_dmamask,
930 .coherent_dma_mask = DMA_BIT_MASK(32),
931 .platform_data = &uart0_data,
86ad76bb
AV		 932 },
933 .resource = uart0_resources,
934 .num_resources = ARRAY_SIZE(uart0_resources),
935};
936
c8f385a6 937static inline void configure_usart0_pins(unsigned pins)
86ad76bb
AV		 938{
939 at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
940 at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
c8f385a6
AV		 941
942 if (pins & ATMEL_UART_RTS)
943 at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
944 if (pins & ATMEL_UART_CTS)
945 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
86ad76bb
AV		 946}
947
948static struct resource uart1_resources[] = {
949 [0] = {
950 .start = AT91SAM9261_BASE_US1,
951 .end = AT91SAM9261_BASE_US1 + SZ_16K - 1,
952 .flags = IORESOURCE_MEM,
953 },
954 [1] = {
8fe82a55
LD		 955 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
956 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
86ad76bb
AV		 957 .flags = IORESOURCE_IRQ,
958 },
959};
960
961static struct atmel_uart_data uart1_data = {
962 .use_dma_tx = 1,
963 .use_dma_rx = 1,
964};
965
c6686ff9
AV		 966static u64 uart1_dmamask = DMA_BIT_MASK(32);
967
86ad76bb
AV		 968static struct platform_device at91sam9261_uart1_device = {
969 .name = "atmel_usart",
970 .id = 2,
971 .dev = {
c6686ff9
AV		 972 .dma_mask = &uart1_dmamask,
973 .coherent_dma_mask = DMA_BIT_MASK(32),
974 .platform_data = &uart1_data,
86ad76bb
AV		 975 },
976 .resource = uart1_resources,
977 .num_resources = ARRAY_SIZE(uart1_resources),
978};
979
c8f385a6 980static inline void configure_usart1_pins(unsigned pins)
86ad76bb
AV		 981{
982 at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
983 at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
c8f385a6
AV		 984
985 if (pins & ATMEL_UART_RTS)
986 at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */
987 if (pins & ATMEL_UART_CTS)
988 at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
86ad76bb
AV		 989}
990
991static struct resource uart2_resources[] = {
992 [0] = {
993 .start = AT91SAM9261_BASE_US2,
994 .end = AT91SAM9261_BASE_US2 + SZ_16K - 1,
995 .flags = IORESOURCE_MEM,
996 },
997 [1] = {
8fe82a55
LD		 998 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
999 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
86ad76bb
AV		 1000 .flags = IORESOURCE_IRQ,
1001 },
1002};
1003
1004static struct atmel_uart_data uart2_data = {
1005 .use_dma_tx = 1,
1006 .use_dma_rx = 1,
1007};
1008
c6686ff9
AV		 1009static u64 uart2_dmamask = DMA_BIT_MASK(32);
1010
86ad76bb
AV		 1011static struct platform_device at91sam9261_uart2_device = {
1012 .name = "atmel_usart",
1013 .id = 3,
1014 .dev = {
c6686ff9
AV		 1015 .dma_mask = &uart2_dmamask,
1016 .coherent_dma_mask = DMA_BIT_MASK(32),
1017 .platform_data = &uart2_data,
86ad76bb
AV		 1018 },
1019 .resource = uart2_resources,
1020 .num_resources = ARRAY_SIZE(uart2_resources),
1021};
1022
c8f385a6 1023static inline void configure_usart2_pins(unsigned pins)
86ad76bb
AV		 1024{
1025 at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
1026 at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
c8f385a6
AV		 1027
1028 if (pins & ATMEL_UART_RTS)
1029 at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/
1030 if (pins & ATMEL_UART_CTS)
1031 at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
86ad76bb
AV		 1032}
1033
11aadac4 1034static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
86ad76bb 1035
c8f385a6
AV		 1036void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1037{
1038 struct platform_device *pdev;
2b348e2f 1039 struct atmel_uart_data *pdata;
c8f385a6
AV		 1040
1041 switch (id) {
1042 case 0: /* DBGU */
1043 pdev = &at91sam9261_dbgu_device;
1044 configure_dbgu_pins();
c8f385a6
AV		 1045 break;
1046 case AT91SAM9261_ID_US0:
1047 pdev = &at91sam9261_uart0_device;
1048 configure_usart0_pins(pins);
c8f385a6
AV		 1049 break;
1050 case AT91SAM9261_ID_US1:
1051 pdev = &at91sam9261_uart1_device;
1052 configure_usart1_pins(pins);
c8f385a6
AV		 1053 break;
1054 case AT91SAM9261_ID_US2:
1055 pdev = &at91sam9261_uart2_device;
1056 configure_usart2_pins(pins);
c8f385a6
AV		 1057 break;
1058 default:
1059 return;
1060 }
2b348e2f
JCPV		 1061 pdata = pdev->dev.platform_data;
1062 pdata->num = portnr; /* update to mapped ID */
c8f385a6
AV		 1063
1064 if (portnr < ATMEL_MAX_UART)
1065 at91_uarts[portnr] = pdev;
1066}
1067
86ad76bb
AV		 1068void __init at91_add_device_serial(void)
1069{
1070 int i;
1071
1072 for (i = 0; i < ATMEL_MAX_UART; i++) {
1073 if (at91_uarts[i])
1074 platform_device_register(at91_uarts[i]);
1075 }
1076}
1077#else
c8f385a6 1078void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
86ad76bb
AV		 1079void __init at91_add_device_serial(void) {}
1080#endif
1081
1082
1083/* -------------------------------------------------------------------- */
1084
1085/*
1086 * These devices are always present and don't need any board-specific
1087 * setup.
1088 */
1089static int __init at91_add_standard_devices(void)
1090{
884f5a6a
AV		 1091 at91_add_device_rtt();
1092 at91_add_device_watchdog();
e5f40bfa 1093 at91_add_device_tc();
86ad76bb
AV		 1094 return 0;
1095}
1096
1097arch_initcall(at91_add_standard_devices);
kernel source for telekom puls (alcatel/mediatek)