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treewide: Convert uses of struct resource to resource_size(ptr)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-at91 / at91sam9261_devices.c
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86ad76bb 1/*
9d041268 2 * arch/arm/mach-at91/at91sam9261_devices.c
86ad76bb
AV		 3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15
c6686ff9 16#include <linux/dma-mapping.h>
86ad76bb 17#include <linux/platform_device.h>
f230d3f5 18#include <linux/i2c-gpio.h>
86ad76bb 19
f230d3f5 20#include <linux/fb.h>
b8b78609
JA		 21#include <video/atmel_lcdc.h>
22
a09e64fb
RK		 23#include <mach/board.h>
24#include <mach/gpio.h>
25#include <mach/at91sam9261.h>
26#include <mach/at91sam9261_matrix.h>
27#include <mach/at91sam9_smc.h>
86ad76bb
AV		 28
29#include "generic.h"
30
86ad76bb
AV		 31
32/* --------------------------------------------------------------------
33 * USB Host
34 * -------------------------------------------------------------------- */
35
36#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
c6686ff9 37static u64 ohci_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 38static struct at91_usbh_data usbh_data;
39
40static struct resource usbh_resources[] = {
41 [0] = {
42 .start = AT91SAM9261_UHP_BASE,
43 .end = AT91SAM9261_UHP_BASE + SZ_1M - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = AT91SAM9261_ID_UHP,
48 .end = AT91SAM9261_ID_UHP,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53static struct platform_device at91sam9261_usbh_device = {
54 .name = "at91_ohci",
55 .id = -1,
56 .dev = {
57 .dma_mask = &ohci_dmamask,
c6686ff9 58 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 59 .platform_data = &usbh_data,
60 },
61 .resource = usbh_resources,
62 .num_resources = ARRAY_SIZE(usbh_resources),
63};
64
65void __init at91_add_device_usbh(struct at91_usbh_data *data)
66{
67 if (!data)
68 return;
69
70 usbh_data = *data;
71 platform_device_register(&at91sam9261_usbh_device);
72}
73#else
74void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
75#endif
76
77
78/* --------------------------------------------------------------------
79 * USB Device (Gadget)
80 * -------------------------------------------------------------------- */
81
82#ifdef CONFIG_USB_GADGET_AT91
83static struct at91_udc_data udc_data;
84
85static struct resource udc_resources[] = {
86 [0] = {
87 .start = AT91SAM9261_BASE_UDP,
88 .end = AT91SAM9261_BASE_UDP + SZ_16K - 1,
89 .flags = IORESOURCE_MEM,
90 },
91 [1] = {
92 .start = AT91SAM9261_ID_UDP,
93 .end = AT91SAM9261_ID_UDP,
94 .flags = IORESOURCE_IRQ,
95 },
96};
97
98static struct platform_device at91sam9261_udc_device = {
99 .name = "at91_udc",
100 .id = -1,
101 .dev = {
102 .platform_data = &udc_data,
103 },
104 .resource = udc_resources,
105 .num_resources = ARRAY_SIZE(udc_resources),
106};
107
108void __init at91_add_device_udc(struct at91_udc_data *data)
109{
86ad76bb
AV		 110 if (!data)
111 return;
112
113 if (data->vbus_pin) {
114 at91_set_gpio_input(data->vbus_pin, 0);
115 at91_set_deglitch(data->vbus_pin, 1);
116 }
117
da7a42d6 118 /* Pullup pin is handled internally by USB device peripheral */
86ad76bb
AV		 119
120 udc_data = *data;
121 platform_device_register(&at91sam9261_udc_device);
122}
123#else
124void __init at91_add_device_udc(struct at91_udc_data *data) {}
125#endif
126
127/* --------------------------------------------------------------------
128 * MMC / SD
129 * -------------------------------------------------------------------- */
130
131#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
c6686ff9 132static u64 mmc_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 133static struct at91_mmc_data mmc_data;
134
135static struct resource mmc_resources[] = {
136 [0] = {
137 .start = AT91SAM9261_BASE_MCI,
138 .end = AT91SAM9261_BASE_MCI + SZ_16K - 1,
139 .flags = IORESOURCE_MEM,
140 },
141 [1] = {
142 .start = AT91SAM9261_ID_MCI,
143 .end = AT91SAM9261_ID_MCI,
144 .flags = IORESOURCE_IRQ,
145 },
146};
147
148static struct platform_device at91sam9261_mmc_device = {
149 .name = "at91_mci",
150 .id = -1,
151 .dev = {
152 .dma_mask = &mmc_dmamask,
c6686ff9 153 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 154 .platform_data = &mmc_data,
155 },
156 .resource = mmc_resources,
157 .num_resources = ARRAY_SIZE(mmc_resources),
158};
159
d0760b3b 160void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
86ad76bb
AV		 161{
162 if (!data)
163 return;
164
165 /* input/irq */
166 if (data->det_pin) {
167 at91_set_gpio_input(data->det_pin, 1);
168 at91_set_deglitch(data->det_pin, 1);
169 }
170 if (data->wp_pin)
171 at91_set_gpio_input(data->wp_pin, 1);
172 if (data->vcc_pin)
173 at91_set_gpio_output(data->vcc_pin, 0);
174
175 /* CLK */
176 at91_set_B_periph(AT91_PIN_PA2, 0);
177
178 /* CMD */
179 at91_set_B_periph(AT91_PIN_PA1, 1);
180
181 /* DAT0, maybe DAT1..DAT3 */
182 at91_set_B_periph(AT91_PIN_PA0, 1);
183 if (data->wire4) {
184 at91_set_B_periph(AT91_PIN_PA4, 1);
185 at91_set_B_periph(AT91_PIN_PA5, 1);
186 at91_set_B_periph(AT91_PIN_PA6, 1);
187 }
188
189 mmc_data = *data;
190 platform_device_register(&at91sam9261_mmc_device);
191}
192#else
d0760b3b 193void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
86ad76bb
AV		 194#endif
195
196
197/* --------------------------------------------------------------------
198 * NAND / SmartMedia
199 * -------------------------------------------------------------------- */
200
f6ed6f78 201#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 202static struct atmel_nand_data nand_data;
86ad76bb
AV		 203
204#define NAND_BASE AT91_CHIPSELECT_3
205
206static struct resource nand_resources[] = {
207 {
208 .start = NAND_BASE,
209 .end = NAND_BASE + SZ_256M - 1,
210 .flags = IORESOURCE_MEM,
211 }
212};
213
3c3796cc
HS		 214static struct platform_device atmel_nand_device = {
215 .name = "atmel_nand",
86ad76bb
AV		 216 .id = -1,
217 .dev = {
218 .platform_data = &nand_data,
219 },
220 .resource = nand_resources,
221 .num_resources = ARRAY_SIZE(nand_resources),
222};
223
3c3796cc 224void __init at91_add_device_nand(struct atmel_nand_data *data)
86ad76bb 225{
461d3b4d 226 unsigned long csa;
86ad76bb
AV		 227
228 if (!data)
229 return;
230
231 csa = at91_sys_read(AT91_MATRIX_EBICSA);
22823558 232 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
86ad76bb 233
86ad76bb
AV		 234 /* enable pin */
235 if (data->enable_pin)
236 at91_set_gpio_output(data->enable_pin, 1);
237
238 /* ready/busy pin */
239 if (data->rdy_pin)
240 at91_set_gpio_input(data->rdy_pin, 1);
241
242 /* card detect pin */
243 if (data->det_pin)
244 at91_set_gpio_input(data->det_pin, 1);
245
246 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
247 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
248
249 nand_data = *data;
3c3796cc 250 platform_device_register(&atmel_nand_device);
86ad76bb
AV		 251}
252
253#else
3c3796cc 254void __init at91_add_device_nand(struct atmel_nand_data *data) {}
86ad76bb
AV		 255#endif
256
257
258/* --------------------------------------------------------------------
259 * TWI (i2c)
260 * -------------------------------------------------------------------- */
261
f230d3f5
AV		 262/*
263 * Prefer the GPIO code since the TWI controller isn't robust
264 * (gets overruns and underruns under load) and can only issue
265 * repeated STARTs in one scenario (the driver doesn't yet handle them).
266 */
267#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
268
269static struct i2c_gpio_platform_data pdata = {
270 .sda_pin = AT91_PIN_PA7,
271 .sda_is_open_drain = 1,
272 .scl_pin = AT91_PIN_PA8,
273 .scl_is_open_drain = 1,
274 .udelay = 2, /* ~100 kHz */
275};
276
277static struct platform_device at91sam9261_twi_device = {
278 .name = "i2c-gpio",
279 .id = -1,
280 .dev.platform_data = &pdata,
281};
282
283void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
284{
285 at91_set_GPIO_periph(AT91_PIN_PA7, 1); /* TWD (SDA) */
286 at91_set_multi_drive(AT91_PIN_PA7, 1);
287
288 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
289 at91_set_multi_drive(AT91_PIN_PA8, 1);
290
291 i2c_register_board_info(0, devices, nr_devices);
292 platform_device_register(&at91sam9261_twi_device);
293}
294
295#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
86ad76bb
AV		 296
297static struct resource twi_resources[] = {
298 [0] = {
299 .start = AT91SAM9261_BASE_TWI,
300 .end = AT91SAM9261_BASE_TWI + SZ_16K - 1,
301 .flags = IORESOURCE_MEM,
302 },
303 [1] = {
304 .start = AT91SAM9261_ID_TWI,
305 .end = AT91SAM9261_ID_TWI,
306 .flags = IORESOURCE_IRQ,
307 },
308};
309
310static struct platform_device at91sam9261_twi_device = {
311 .name = "at91_i2c",
312 .id = -1,
313 .resource = twi_resources,
314 .num_resources = ARRAY_SIZE(twi_resources),
315};
316
f230d3f5 317void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
86ad76bb
AV		 318{
319 /* pins used for TWI interface */
320 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */
321 at91_set_multi_drive(AT91_PIN_PA7, 1);
322
323 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */
324 at91_set_multi_drive(AT91_PIN_PA8, 1);
325
f230d3f5 326 i2c_register_board_info(0, devices, nr_devices);
86ad76bb
AV		 327 platform_device_register(&at91sam9261_twi_device);
328}
329#else
f230d3f5 330void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
86ad76bb
AV		 331#endif
332
333
334/* --------------------------------------------------------------------
335 * SPI
336 * -------------------------------------------------------------------- */
337
338#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 339static u64 spi_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 340
341static struct resource spi0_resources[] = {
342 [0] = {
343 .start = AT91SAM9261_BASE_SPI0,
344 .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
345 .flags = IORESOURCE_MEM,
346 },
347 [1] = {
348 .start = AT91SAM9261_ID_SPI0,
349 .end = AT91SAM9261_ID_SPI0,
350 .flags = IORESOURCE_IRQ,
351 },
352};
353
354static struct platform_device at91sam9261_spi0_device = {
355 .name = "atmel_spi",
356 .id = 0,
357 .dev = {
358 .dma_mask = &spi_dmamask,
c6686ff9 359 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 360 },
361 .resource = spi0_resources,
362 .num_resources = ARRAY_SIZE(spi0_resources),
363};
364
365static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
366
367static struct resource spi1_resources[] = {
368 [0] = {
369 .start = AT91SAM9261_BASE_SPI1,
370 .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
371 .flags = IORESOURCE_MEM,
372 },
373 [1] = {
374 .start = AT91SAM9261_ID_SPI1,
375 .end = AT91SAM9261_ID_SPI1,
376 .flags = IORESOURCE_IRQ,
377 },
378};
379
380static struct platform_device at91sam9261_spi1_device = {
381 .name = "atmel_spi",
382 .id = 1,
383 .dev = {
384 .dma_mask = &spi_dmamask,
c6686ff9 385 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 386 },
387 .resource = spi1_resources,
388 .num_resources = ARRAY_SIZE(spi1_resources),
389};
390
391static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
392
393void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
394{
395 int i;
396 unsigned long cs_pin;
397 short enable_spi0 = 0;
398 short enable_spi1 = 0;
399
400 /* Choose SPI chip-selects */
401 for (i = 0; i < nr_devices; i++) {
402 if (devices[i].controller_data)
403 cs_pin = (unsigned long) devices[i].controller_data;
404 else if (devices[i].bus_num == 0)
405 cs_pin = spi0_standard_cs[devices[i].chip_select];
406 else
407 cs_pin = spi1_standard_cs[devices[i].chip_select];
408
409 if (devices[i].bus_num == 0)
410 enable_spi0 = 1;
411 else
412 enable_spi1 = 1;
413
414 /* enable chip-select pin */
415 at91_set_gpio_output(cs_pin, 1);
416
417 /* pass chip-select pin to driver */
418 devices[i].controller_data = (void *) cs_pin;
419 }
420
421 spi_register_board_info(devices, nr_devices);
422
423 /* Configure SPI bus(es) */
424 if (enable_spi0) {
425 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
426 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
427 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
428
86ad76bb
AV		 429 platform_device_register(&at91sam9261_spi0_device);
430 }
431 if (enable_spi1) {
432 at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
433 at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
434 at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
435
86ad76bb
AV		 436 platform_device_register(&at91sam9261_spi1_device);
437 }
438}
439#else
440void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
441#endif
442
443
444/* --------------------------------------------------------------------
445 * LCD Controller
446 * -------------------------------------------------------------------- */
447
7776a94c 448#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
c6686ff9 449static u64 lcdc_dmamask = DMA_BIT_MASK(32);
7776a94c 450static struct atmel_lcdfb_info lcdc_data;
86ad76bb
AV		 451
452static struct resource lcdc_resources[] = {
453 [0] = {
454 .start = AT91SAM9261_LCDC_BASE,
455 .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
456 .flags = IORESOURCE_MEM,
457 },
458 [1] = {
459 .start = AT91SAM9261_ID_LCDC,
460 .end = AT91SAM9261_ID_LCDC,
461 .flags = IORESOURCE_IRQ,
462 },
463#if defined(CONFIG_FB_INTSRAM)
464 [2] = {
465 .start = AT91SAM9261_SRAM_BASE,
466 .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
467 .flags = IORESOURCE_MEM,
468 },
469#endif
470};
471
472static struct platform_device at91_lcdc_device = {
7776a94c 473 .name = "atmel_lcdfb",
86ad76bb
AV		 474 .id = 0,
475 .dev = {
476 .dma_mask = &lcdc_dmamask,
c6686ff9 477 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 478 .platform_data = &lcdc_data,
479 },
480 .resource = lcdc_resources,
481 .num_resources = ARRAY_SIZE(lcdc_resources),
482};
483
7776a94c 484void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
86ad76bb
AV		 485{
486 if (!data) {
487 return;
488 }
489
f06e656f
AV		 490#if defined(CONFIG_FB_ATMEL_STN)
491 at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
492 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
493 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
494 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
495 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
496 at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */
497 at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */
498 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
499 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
500#else
86ad76bb
AV		 501 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
502 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
503 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
504 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
505 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
506 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
507 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
508 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
509 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
510 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
511 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
512 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
513 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
514 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
515 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
516 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
517 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
518 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
519 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
520 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
521 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
522 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
f06e656f 523#endif
86ad76bb 524
01d3a5e7
HS		 525 if (ARRAY_SIZE(lcdc_resources) > 2) {
526 void __iomem *fb;
527 struct resource *fb_res = &lcdc_resources[2];
28f65c11 528 size_t fb_len = resource_size(fb_res);
01d3a5e7 529
90898709 530 fb = ioremap(fb_res->start, fb_len);
01d3a5e7
HS		 531 if (fb) {
532 memset(fb, 0, fb_len);
90898709 533 iounmap(fb);
01d3a5e7
HS		 534 }
535 }
86ad76bb
AV		 536 lcdc_data = *data;
537 platform_device_register(&at91_lcdc_device);
538}
539#else
7776a94c 540void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
86ad76bb
AV		 541#endif
542
543
e5f40bfa
AV		 544/* --------------------------------------------------------------------
545 * Timer/Counter block
546 * -------------------------------------------------------------------- */
547
548#ifdef CONFIG_ATMEL_TCLIB
549
550static struct resource tcb_resources[] = {
551 [0] = {
552 .start = AT91SAM9261_BASE_TCB0,
553 .end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
554 .flags = IORESOURCE_MEM,
555 },
556 [1] = {
557 .start = AT91SAM9261_ID_TC0,
558 .end = AT91SAM9261_ID_TC0,
559 .flags = IORESOURCE_IRQ,
560 },
561 [2] = {
562 .start = AT91SAM9261_ID_TC1,
563 .end = AT91SAM9261_ID_TC1,
564 .flags = IORESOURCE_IRQ,
565 },
566 [3] = {
567 .start = AT91SAM9261_ID_TC2,
568 .end = AT91SAM9261_ID_TC2,
569 .flags = IORESOURCE_IRQ,
570 },
571};
572
573static struct platform_device at91sam9261_tcb_device = {
574 .name = "atmel_tcb",
575 .id = 0,
576 .resource = tcb_resources,
577 .num_resources = ARRAY_SIZE(tcb_resources),
578};
579
580static void __init at91_add_device_tc(void)
581{
e5f40bfa
AV		 582 platform_device_register(&at91sam9261_tcb_device);
583}
584#else
585static void __init at91_add_device_tc(void) { }
586#endif
587
588
884f5a6a
AV		 589/* --------------------------------------------------------------------
590 * RTT
591 * -------------------------------------------------------------------- */
592
593static struct resource rtt_resources[] = {
594 {
595 .start = AT91_BASE_SYS + AT91_RTT,
596 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
597 .flags = IORESOURCE_MEM,
598 }
599};
600
601static struct platform_device at91sam9261_rtt_device = {
602 .name = "at91_rtt",
4fd9212c 603 .id = 0,
884f5a6a
AV		 604 .resource = rtt_resources,
605 .num_resources = ARRAY_SIZE(rtt_resources),
606};
607
608static void __init at91_add_device_rtt(void)
609{
610 platform_device_register(&at91sam9261_rtt_device);
611}
612
613
614/* --------------------------------------------------------------------
615 * Watchdog
616 * -------------------------------------------------------------------- */
617
2af29b78 618#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
884f5a6a
AV		 619static struct platform_device at91sam9261_wdt_device = {
620 .name = "at91_wdt",
621 .id = -1,
622 .num_resources = 0,
623};
624
625static void __init at91_add_device_watchdog(void)
626{
627 platform_device_register(&at91sam9261_wdt_device);
628}
629#else
630static void __init at91_add_device_watchdog(void) {}
631#endif
632
633
bfbc3266
AV		 634/* --------------------------------------------------------------------
635 * SSC -- Synchronous Serial Controller
636 * -------------------------------------------------------------------- */
637
638#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
639static u64 ssc0_dmamask = DMA_BIT_MASK(32);
640
641static struct resource ssc0_resources[] = {
642 [0] = {
643 .start = AT91SAM9261_BASE_SSC0,
644 .end = AT91SAM9261_BASE_SSC0 + SZ_16K - 1,
645 .flags = IORESOURCE_MEM,
646 },
647 [1] = {
648 .start = AT91SAM9261_ID_SSC0,
649 .end = AT91SAM9261_ID_SSC0,
650 .flags = IORESOURCE_IRQ,
651 },
652};
653
654static struct platform_device at91sam9261_ssc0_device = {
655 .name = "ssc",
656 .id = 0,
657 .dev = {
658 .dma_mask = &ssc0_dmamask,
659 .coherent_dma_mask = DMA_BIT_MASK(32),
660 },
661 .resource = ssc0_resources,
662 .num_resources = ARRAY_SIZE(ssc0_resources),
663};
664
665static inline void configure_ssc0_pins(unsigned pins)
666{
667 if (pins & ATMEL_SSC_TF)
668 at91_set_A_periph(AT91_PIN_PB21, 1);
669 if (pins & ATMEL_SSC_TK)
670 at91_set_A_periph(AT91_PIN_PB22, 1);
671 if (pins & ATMEL_SSC_TD)
672 at91_set_A_periph(AT91_PIN_PB23, 1);
673 if (pins & ATMEL_SSC_RD)
674 at91_set_A_periph(AT91_PIN_PB24, 1);
675 if (pins & ATMEL_SSC_RK)
676 at91_set_A_periph(AT91_PIN_PB25, 1);
677 if (pins & ATMEL_SSC_RF)
678 at91_set_A_periph(AT91_PIN_PB26, 1);
679}
680
681static u64 ssc1_dmamask = DMA_BIT_MASK(32);
682
683static struct resource ssc1_resources[] = {
684 [0] = {
685 .start = AT91SAM9261_BASE_SSC1,
686 .end = AT91SAM9261_BASE_SSC1 + SZ_16K - 1,
687 .flags = IORESOURCE_MEM,
688 },
689 [1] = {
690 .start = AT91SAM9261_ID_SSC1,
691 .end = AT91SAM9261_ID_SSC1,
692 .flags = IORESOURCE_IRQ,
693 },
694};
695
696static struct platform_device at91sam9261_ssc1_device = {
697 .name = "ssc",
698 .id = 1,
699 .dev = {
700 .dma_mask = &ssc1_dmamask,
701 .coherent_dma_mask = DMA_BIT_MASK(32),
702 },
703 .resource = ssc1_resources,
704 .num_resources = ARRAY_SIZE(ssc1_resources),
705};
706
707static inline void configure_ssc1_pins(unsigned pins)
708{
709 if (pins & ATMEL_SSC_TF)
710 at91_set_B_periph(AT91_PIN_PA17, 1);
711 if (pins & ATMEL_SSC_TK)
712 at91_set_B_periph(AT91_PIN_PA18, 1);
713 if (pins & ATMEL_SSC_TD)
714 at91_set_B_periph(AT91_PIN_PA19, 1);
715 if (pins & ATMEL_SSC_RD)
716 at91_set_B_periph(AT91_PIN_PA20, 1);
717 if (pins & ATMEL_SSC_RK)
718 at91_set_B_periph(AT91_PIN_PA21, 1);
719 if (pins & ATMEL_SSC_RF)
720 at91_set_B_periph(AT91_PIN_PA22, 1);
721}
722
723static u64 ssc2_dmamask = DMA_BIT_MASK(32);
724
725static struct resource ssc2_resources[] = {
726 [0] = {
727 .start = AT91SAM9261_BASE_SSC2,
728 .end = AT91SAM9261_BASE_SSC2 + SZ_16K - 1,
729 .flags = IORESOURCE_MEM,
730 },
731 [1] = {
732 .start = AT91SAM9261_ID_SSC2,
733 .end = AT91SAM9261_ID_SSC2,
734 .flags = IORESOURCE_IRQ,
735 },
736};
737
738static struct platform_device at91sam9261_ssc2_device = {
739 .name = "ssc",
740 .id = 2,
741 .dev = {
742 .dma_mask = &ssc2_dmamask,
743 .coherent_dma_mask = DMA_BIT_MASK(32),
744 },
745 .resource = ssc2_resources,
746 .num_resources = ARRAY_SIZE(ssc2_resources),
747};
748
749static inline void configure_ssc2_pins(unsigned pins)
750{
751 if (pins & ATMEL_SSC_TF)
752 at91_set_B_periph(AT91_PIN_PC25, 1);
753 if (pins & ATMEL_SSC_TK)
754 at91_set_B_periph(AT91_PIN_PC26, 1);
755 if (pins & ATMEL_SSC_TD)
756 at91_set_B_periph(AT91_PIN_PC27, 1);
757 if (pins & ATMEL_SSC_RD)
758 at91_set_B_periph(AT91_PIN_PC28, 1);
759 if (pins & ATMEL_SSC_RK)
760 at91_set_B_periph(AT91_PIN_PC29, 1);
761 if (pins & ATMEL_SSC_RF)
762 at91_set_B_periph(AT91_PIN_PC30, 1);
763}
764
765/*
766 * SSC controllers are accessed through library code, instead of any
767 * kind of all-singing/all-dancing driver. For example one could be
768 * used by a particular I2S audio codec's driver, while another one
769 * on the same system might be used by a custom data capture driver.
770 */
771void __init at91_add_device_ssc(unsigned id, unsigned pins)
772{
773 struct platform_device *pdev;
774
775 /*
776 * NOTE: caller is responsible for passing information matching
777 * "pins" to whatever will be using each particular controller.
778 */
779 switch (id) {
780 case AT91SAM9261_ID_SSC0:
781 pdev = &at91sam9261_ssc0_device;
782 configure_ssc0_pins(pins);
bfbc3266
AV		 783 break;
784 case AT91SAM9261_ID_SSC1:
785 pdev = &at91sam9261_ssc1_device;
786 configure_ssc1_pins(pins);
bfbc3266
AV		 787 break;
788 case AT91SAM9261_ID_SSC2:
789 pdev = &at91sam9261_ssc2_device;
790 configure_ssc2_pins(pins);
bfbc3266
AV		 791 break;
792 default:
793 return;
794 }
795
796 platform_device_register(pdev);
797}
798
799#else
800void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
801#endif
802
803
86ad76bb
AV		 804/* --------------------------------------------------------------------
805 * UART
806 * -------------------------------------------------------------------- */
807
808#if defined(CONFIG_SERIAL_ATMEL)
809static struct resource dbgu_resources[] = {
810 [0] = {
811 .start = AT91_VA_BASE_SYS + AT91_DBGU,
812 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
813 .flags = IORESOURCE_MEM,
814 },
815 [1] = {
816 .start = AT91_ID_SYS,
817 .end = AT91_ID_SYS,
818 .flags = IORESOURCE_IRQ,
819 },
820};
821
822static struct atmel_uart_data dbgu_data = {
823 .use_dma_tx = 0,
824 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
825 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
826};
827
c6686ff9
AV		 828static u64 dbgu_dmamask = DMA_BIT_MASK(32);
829
86ad76bb
AV		 830static struct platform_device at91sam9261_dbgu_device = {
831 .name = "atmel_usart",
832 .id = 0,
833 .dev = {
c6686ff9
AV		 834 .dma_mask = &dbgu_dmamask,
835 .coherent_dma_mask = DMA_BIT_MASK(32),
836 .platform_data = &dbgu_data,
86ad76bb
AV		 837 },
838 .resource = dbgu_resources,
839 .num_resources = ARRAY_SIZE(dbgu_resources),
840};
841
842static inline void configure_dbgu_pins(void)
843{
844 at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
845 at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
846}
847
848static struct resource uart0_resources[] = {
849 [0] = {
850 .start = AT91SAM9261_BASE_US0,
851 .end = AT91SAM9261_BASE_US0 + SZ_16K - 1,
852 .flags = IORESOURCE_MEM,
853 },
854 [1] = {
855 .start = AT91SAM9261_ID_US0,
856 .end = AT91SAM9261_ID_US0,
857 .flags = IORESOURCE_IRQ,
858 },
859};
860
861static struct atmel_uart_data uart0_data = {
862 .use_dma_tx = 1,
863 .use_dma_rx = 1,
864};
865
c6686ff9
AV		 866static u64 uart0_dmamask = DMA_BIT_MASK(32);
867
86ad76bb
AV		 868static struct platform_device at91sam9261_uart0_device = {
869 .name = "atmel_usart",
870 .id = 1,
871 .dev = {
c6686ff9
AV		 872 .dma_mask = &uart0_dmamask,
873 .coherent_dma_mask = DMA_BIT_MASK(32),
874 .platform_data = &uart0_data,
86ad76bb
AV		 875 },
876 .resource = uart0_resources,
877 .num_resources = ARRAY_SIZE(uart0_resources),
878};
879
c8f385a6 880static inline void configure_usart0_pins(unsigned pins)
86ad76bb
AV		 881{
882 at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
883 at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
c8f385a6
AV		 884
885 if (pins & ATMEL_UART_RTS)
886 at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
887 if (pins & ATMEL_UART_CTS)
888 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
86ad76bb
AV		 889}
890
891static struct resource uart1_resources[] = {
892 [0] = {
893 .start = AT91SAM9261_BASE_US1,
894 .end = AT91SAM9261_BASE_US1 + SZ_16K - 1,
895 .flags = IORESOURCE_MEM,
896 },
897 [1] = {
898 .start = AT91SAM9261_ID_US1,
899 .end = AT91SAM9261_ID_US1,
900 .flags = IORESOURCE_IRQ,
901 },
902};
903
904static struct atmel_uart_data uart1_data = {
905 .use_dma_tx = 1,
906 .use_dma_rx = 1,
907};
908
c6686ff9
AV		 909static u64 uart1_dmamask = DMA_BIT_MASK(32);
910
86ad76bb
AV		 911static struct platform_device at91sam9261_uart1_device = {
912 .name = "atmel_usart",
913 .id = 2,
914 .dev = {
c6686ff9
AV		 915 .dma_mask = &uart1_dmamask,
916 .coherent_dma_mask = DMA_BIT_MASK(32),
917 .platform_data = &uart1_data,
86ad76bb
AV		 918 },
919 .resource = uart1_resources,
920 .num_resources = ARRAY_SIZE(uart1_resources),
921};
922
c8f385a6 923static inline void configure_usart1_pins(unsigned pins)
86ad76bb
AV		 924{
925 at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
926 at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
c8f385a6
AV		 927
928 if (pins & ATMEL_UART_RTS)
929 at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */
930 if (pins & ATMEL_UART_CTS)
931 at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
86ad76bb
AV		 932}
933
934static struct resource uart2_resources[] = {
935 [0] = {
936 .start = AT91SAM9261_BASE_US2,
937 .end = AT91SAM9261_BASE_US2 + SZ_16K - 1,
938 .flags = IORESOURCE_MEM,
939 },
940 [1] = {
941 .start = AT91SAM9261_ID_US2,
942 .end = AT91SAM9261_ID_US2,
943 .flags = IORESOURCE_IRQ,
944 },
945};
946
947static struct atmel_uart_data uart2_data = {
948 .use_dma_tx = 1,
949 .use_dma_rx = 1,
950};
951
c6686ff9
AV		 952static u64 uart2_dmamask = DMA_BIT_MASK(32);
953
86ad76bb
AV		 954static struct platform_device at91sam9261_uart2_device = {
955 .name = "atmel_usart",
956 .id = 3,
957 .dev = {
c6686ff9
AV		 958 .dma_mask = &uart2_dmamask,
959 .coherent_dma_mask = DMA_BIT_MASK(32),
960 .platform_data = &uart2_data,
86ad76bb
AV		 961 },
962 .resource = uart2_resources,
963 .num_resources = ARRAY_SIZE(uart2_resources),
964};
965
c8f385a6 966static inline void configure_usart2_pins(unsigned pins)
86ad76bb
AV		 967{
968 at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
969 at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
c8f385a6
AV		 970
971 if (pins & ATMEL_UART_RTS)
972 at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/
973 if (pins & ATMEL_UART_CTS)
974 at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
86ad76bb
AV		 975}
976
11aadac4 977static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
86ad76bb
AV		 978struct platform_device *atmel_default_console_device; /* the serial console device */
979
c8f385a6
AV		 980void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
981{
982 struct platform_device *pdev;
2b348e2f 983 struct atmel_uart_data *pdata;
c8f385a6
AV		 984
985 switch (id) {
986 case 0: /* DBGU */
987 pdev = &at91sam9261_dbgu_device;
988 configure_dbgu_pins();
c8f385a6
AV		 989 break;
990 case AT91SAM9261_ID_US0:
991 pdev = &at91sam9261_uart0_device;
992 configure_usart0_pins(pins);
c8f385a6
AV		 993 break;
994 case AT91SAM9261_ID_US1:
995 pdev = &at91sam9261_uart1_device;
996 configure_usart1_pins(pins);
c8f385a6
AV		 997 break;
998 case AT91SAM9261_ID_US2:
999 pdev = &at91sam9261_uart2_device;
1000 configure_usart2_pins(pins);
c8f385a6
AV		 1001 break;
1002 default:
1003 return;
1004 }
2b348e2f
JCPV		 1005 pdata = pdev->dev.platform_data;
1006 pdata->num = portnr; /* update to mapped ID */
c8f385a6
AV		 1007
1008 if (portnr < ATMEL_MAX_UART)
1009 at91_uarts[portnr] = pdev;
1010}
1011
1012void __init at91_set_serial_console(unsigned portnr)
1013{
bd602995 1014 if (portnr < ATMEL_MAX_UART) {
c8f385a6 1015 atmel_default_console_device = at91_uarts[portnr];
bd602995
JCPV		 1016 at91sam9261_set_console_clock(portnr);
1017 }
c8f385a6
AV		 1018}
1019
86ad76bb
AV		 1020void __init at91_add_device_serial(void)
1021{
1022 int i;
1023
1024 for (i = 0; i < ATMEL_MAX_UART; i++) {
1025 if (at91_uarts[i])
1026 platform_device_register(at91_uarts[i]);
1027 }
11aadac4
AV		 1028
1029 if (!atmel_default_console_device)
1030 printk(KERN_INFO "AT91: No default serial console defined.\n");
86ad76bb
AV		 1031}
1032#else
c8f385a6
AV		 1033void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1034void __init at91_set_serial_console(unsigned portnr) {}
86ad76bb
AV		 1035void __init at91_add_device_serial(void) {}
1036#endif
1037
1038
1039/* -------------------------------------------------------------------- */
1040
1041/*
1042 * These devices are always present and don't need any board-specific
1043 * setup.
1044 */
1045static int __init at91_add_standard_devices(void)
1046{
884f5a6a
AV		 1047 at91_add_device_rtt();
1048 at91_add_device_watchdog();
e5f40bfa 1049 at91_add_device_tc();
86ad76bb
AV		 1050 return 0;
1051}
1052
1053arch_initcall(at91_add_standard_devices);
kernel source for telekom puls (alcatel/mediatek)