[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-at91 / at91sam9260.c

/*
 * arch/arm/mach-at91/at91sam9260.c
 *
 *  Copyright (C) 2006 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>

#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9260.h>
#include <mach/at91_pmc.h>

#include "at91_aic.h"
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
#include "clock.h"
#include "sam9_smc.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk adc_clk = {
	.name		= "adc_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_ADC,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk adc_op_clk = {
	.name		= "adc_op_clk",
	.type		= CLK_TYPE_PERIPHERAL,
	.rate_hz	= 5000000,
};

static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
	.name		= "mci_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_MCI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
	.name		= "udc_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_UDP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
	.name		= "twi_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TWI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc_clk = {
	.name		= "ssc_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_SSC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
	.name		= "tc0_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
	.name		= "tc1_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
	.name		= "tc2_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
	.name		= "ohci_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_UHP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
	.name		= "pclk",
	.pmc_mask	= 1 << AT91SAM9260_ID_EMAC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
	.name		= "isi_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_ISI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_US3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart4_clk = {
	.name		= "usart4_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_US4,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart5_clk = {
	.name		= "usart5_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_US5,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc3_clk = {
	.name		= "tc3_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TC3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc4_clk = {
	.name		= "tc4_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TC4,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc5_clk = {
	.name		= "tc5_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TC5,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&adc_clk,
	&adc_op_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&mmc_clk,
	&udc_clk,
	&twi_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc_clk,
	&tc0_clk,
	&tc1_clk,
	&tc2_clk,
	&ohci_clk,
	&macb_clk,
	&isi_clk,
	&usart3_clk,
	&usart4_clk,
	&usart5_clk,
	&tc3_clk,
	&tc4_clk,
	&tc5_clk,
	// irq0 .. irq2
};

static struct clk_lookup periph_clocks_lookups[] = {
	/* One additional fake clock for macb_hclk */
	CLKDEV_CON_ID("hclk", &macb_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
	CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
	/* more usart lookup table for DT entries */
	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
	CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
	CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
	/* more tc lookup table for DT entries */
	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
	CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
	/* fake hclk clock */
	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
	CLKDEV_CON_ID("pioA", &pioA_clk),
	CLKDEV_CON_ID("pioB", &pioB_clk),
	CLKDEV_CON_ID("pioC", &pioC_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
};

/*
 * The two programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};

static void __init at91sam9260_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
	{
		.id		= AT91SAM9260_ID_PIOA,
		.regbase	= AT91SAM9260_BASE_PIOA,
	}, {
		.id		= AT91SAM9260_ID_PIOB,
		.regbase	= AT91SAM9260_BASE_PIOB,
	}, {
		.id		= AT91SAM9260_ID_PIOC,
		.regbase	= AT91SAM9260_BASE_PIOC,
	}
};

/* --------------------------------------------------------------------
 *  AT91SAM9260 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9xe_map_io(void)
{
	unsigned long sram_size;

	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
		case AT91_CIDR_SRAMSIZ_32K:
			sram_size = 2 * SZ_16K;
			break;
		case AT91_CIDR_SRAMSIZ_16K:
		default:
			sram_size = SZ_16K;
	}

	at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
}

static void __init at91sam9260_map_io(void)
{
	if (cpu_is_at91sam9xe())
		at91sam9xe_map_io();
	else if (cpu_is_at91sam9g20())
		at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
	else
		at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
}

static void __init at91sam9260_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
	at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
	at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
	at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
}

static void __init at91sam9260_initialize(void)
{
	arm_pm_idle = at91sam9_idle;
	arm_pm_restart = at91sam9_alt_restart;
	at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
			| (1 << AT91SAM9260_ID_IRQ2);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9260_gpio, 3);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	0,	/* Analog-to-Digital Converter */
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	0,	/* Multimedia Card Interface */
	2,	/* USB Device Port */
	6,	/* Two-Wire Interface */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	5,	/* Serial Synchronous Controller */
	0,
	0,
	0,	/* Timer Counter 0 */
	0,	/* Timer Counter 1 */
	0,	/* Timer Counter 2 */
	2,	/* USB Host port */
	3,	/* Ethernet */
	0,	/* Image Sensor Interface */
	5,	/* USART 3 */
	5,	/* USART 4 */
	5,	/* USART 5 */
	0,	/* Timer Counter 3 */
	0,	/* Timer Counter 4 */
	0,	/* Timer Counter 5 */
	0,	/* Advanced Interrupt Controller */
	0,	/* Advanced Interrupt Controller */
	0,	/* Advanced Interrupt Controller */
};

AT91_SOC_START(sam9260)
	.map_io = at91sam9260_map_io,
	.default_irq_priority = at91sam9260_default_irq_priority,
	.ioremap_registers = at91sam9260_ioremap_registers,
	.register_clocks = at91sam9260_register_clocks,
	.init = at91sam9260_initialize,
AT91_SOC_END
Commit	Line	Data
62c1660d	1	/*
9d041268	2	* arch/arm/mach-at91/at91sam9260.c
62c1660d AV	3	*
	4	* Copyright (C) 2006 SAN People
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
	14
c9dfafba	15	#include <asm/proc-fns.h>
80b02c17	16	#include <asm/irq.h>
62c1660d AV	17	#include <asm/mach/arch.h>
62c1660d AV	18	#include <asm/mach/map.h>
9f97da78	19	#include <asm/system_misc.h>
a09e64fb	20	#include <mach/cpu.h>
8c3583b6	21	#include <mach/at91_dbgu.h>
a09e64fb RK	22	#include <mach/at91sam9260.h>
a09e64fb RK	23	#include <mach/at91_pmc.h>
62c1660d	24
a510b9ba	25	#include "at91_aic.h"
f0995d08	26	#include "at91_rstc.h"
21d08b9d	27	#include "soc.h"
62c1660d AV	28	#include "generic.h"
62c1660d AV	29	#include "clock.h"
faee0cc3	30	#include "sam9_smc.h"
62c1660d	31
62c1660d AV	32	/* --------------------------------------------------------------------
	33	* Clocks
	34	* -------------------------------------------------------------------- */
	35
	36	/*
	37	* The peripheral clocks.
	38	*/
	39	static struct clk pioA_clk = {
	40	.name = "pioA_clk",
	41	.pmc_mask = 1 << AT91SAM9260_ID_PIOA,
	42	.type = CLK_TYPE_PERIPHERAL,
	43	};
	44	static struct clk pioB_clk = {
	45	.name = "pioB_clk",
	46	.pmc_mask = 1 << AT91SAM9260_ID_PIOB,
	47	.type = CLK_TYPE_PERIPHERAL,
	48	};
	49	static struct clk pioC_clk = {
	50	.name = "pioC_clk",
	51	.pmc_mask = 1 << AT91SAM9260_ID_PIOC,
	52	.type = CLK_TYPE_PERIPHERAL,
	53	};
	54	static struct clk adc_clk = {
	55	.name = "adc_clk",
	56	.pmc_mask = 1 << AT91SAM9260_ID_ADC,
	57	.type = CLK_TYPE_PERIPHERAL,
	58	};
67b5d7b3 MR	59
	60	static struct clk adc_op_clk = {
	61	.name = "adc_op_clk",
	62	.type = CLK_TYPE_PERIPHERAL,
	63	.rate_hz = 5000000,
	64	};
	65
62c1660d AV	66	static struct clk usart0_clk = {
	67	.name = "usart0_clk",
	68	.pmc_mask = 1 << AT91SAM9260_ID_US0,
	69	.type = CLK_TYPE_PERIPHERAL,
	70	};
	71	static struct clk usart1_clk = {
	72	.name = "usart1_clk",
	73	.pmc_mask = 1 << AT91SAM9260_ID_US1,
	74	.type = CLK_TYPE_PERIPHERAL,
	75	};
	76	static struct clk usart2_clk = {
	77	.name = "usart2_clk",
	78	.pmc_mask = 1 << AT91SAM9260_ID_US2,
	79	.type = CLK_TYPE_PERIPHERAL,
	80	};
	81	static struct clk mmc_clk = {
	82	.name = "mci_clk",
	83	.pmc_mask = 1 << AT91SAM9260_ID_MCI,
	84	.type = CLK_TYPE_PERIPHERAL,
	85	};
	86	static struct clk udc_clk = {
	87	.name = "udc_clk",
	88	.pmc_mask = 1 << AT91SAM9260_ID_UDP,
	89	.type = CLK_TYPE_PERIPHERAL,
	90	};
	91	static struct clk twi_clk = {
	92	.name = "twi_clk",
	93	.pmc_mask = 1 << AT91SAM9260_ID_TWI,
	94	.type = CLK_TYPE_PERIPHERAL,
	95	};
	96	static struct clk spi0_clk = {
	97	.name = "spi0_clk",
	98	.pmc_mask = 1 << AT91SAM9260_ID_SPI0,
	99	.type = CLK_TYPE_PERIPHERAL,
	100	};
	101	static struct clk spi1_clk = {
	102	.name = "spi1_clk",
	103	.pmc_mask = 1 << AT91SAM9260_ID_SPI1,
	104	.type = CLK_TYPE_PERIPHERAL,
	105	};
e8788bab AV	106	static struct clk ssc_clk = {
	107	.name = "ssc_clk",
	108	.pmc_mask = 1 << AT91SAM9260_ID_SSC,
	109	.type = CLK_TYPE_PERIPHERAL,
	110	};
c177a1e7 AV	111	static struct clk tc0_clk = {
	112	.name = "tc0_clk",
	113	.pmc_mask = 1 << AT91SAM9260_ID_TC0,
	114	.type = CLK_TYPE_PERIPHERAL,
	115	};
	116	static struct clk tc1_clk = {
	117	.name = "tc1_clk",
	118	.pmc_mask = 1 << AT91SAM9260_ID_TC1,
	119	.type = CLK_TYPE_PERIPHERAL,
	120	};
	121	static struct clk tc2_clk = {
	122	.name = "tc2_clk",
	123	.pmc_mask = 1 << AT91SAM9260_ID_TC2,
	124	.type = CLK_TYPE_PERIPHERAL,
	125	};
62c1660d AV	126	static struct clk ohci_clk = {
	127	.name = "ohci_clk",
	128	.pmc_mask = 1 << AT91SAM9260_ID_UHP,
	129	.type = CLK_TYPE_PERIPHERAL,
	130	};
69b2e99c	131	static struct clk macb_clk = {
865d605e	132	.name = "pclk",
62c1660d AV	133	.pmc_mask = 1 << AT91SAM9260_ID_EMAC,
	134	.type = CLK_TYPE_PERIPHERAL,
	135	};
	136	static struct clk isi_clk = {
	137	.name = "isi_clk",
	138	.pmc_mask = 1 << AT91SAM9260_ID_ISI,
	139	.type = CLK_TYPE_PERIPHERAL,
	140	};
	141	static struct clk usart3_clk = {
	142	.name = "usart3_clk",
	143	.pmc_mask = 1 << AT91SAM9260_ID_US3,
	144	.type = CLK_TYPE_PERIPHERAL,
	145	};
	146	static struct clk usart4_clk = {
	147	.name = "usart4_clk",
	148	.pmc_mask = 1 << AT91SAM9260_ID_US4,
	149	.type = CLK_TYPE_PERIPHERAL,
	150	};
	151	static struct clk usart5_clk = {
	152	.name = "usart5_clk",
	153	.pmc_mask = 1 << AT91SAM9260_ID_US5,
	154	.type = CLK_TYPE_PERIPHERAL,
	155	};
c177a1e7 AV	156	static struct clk tc3_clk = {
	157	.name = "tc3_clk",
	158	.pmc_mask = 1 << AT91SAM9260_ID_TC3,
	159	.type = CLK_TYPE_PERIPHERAL,
	160	};
	161	static struct clk tc4_clk = {
	162	.name = "tc4_clk",
	163	.pmc_mask = 1 << AT91SAM9260_ID_TC4,
	164	.type = CLK_TYPE_PERIPHERAL,
	165	};
	166	static struct clk tc5_clk = {
	167	.name = "tc5_clk",
	168	.pmc_mask = 1 << AT91SAM9260_ID_TC5,
	169	.type = CLK_TYPE_PERIPHERAL,
	170	};
62c1660d AV	171
	172	static struct clk *periph_clocks[] __initdata = {
	173	&pioA_clk,
	174	&pioB_clk,
	175	&pioC_clk,
	176	&adc_clk,
67b5d7b3	177	&adc_op_clk,
62c1660d AV	178	&usart0_clk,
	179	&usart1_clk,
	180	&usart2_clk,
	181	&mmc_clk,
	182	&udc_clk,
	183	&twi_clk,
	184	&spi0_clk,
	185	&spi1_clk,
e8788bab	186	&ssc_clk,
c177a1e7 AV	187	&tc0_clk,
	188	&tc1_clk,
	189	&tc2_clk,
62c1660d	190	&ohci_clk,
69b2e99c	191	&macb_clk,
62c1660d AV	192	&isi_clk,
	193	&usart3_clk,
	194	&usart4_clk,
	195	&usart5_clk,
c177a1e7 AV	196	&tc3_clk,
	197	&tc4_clk,
	198	&tc5_clk,
62c1660d AV	199	// irq0 .. irq2
	200	};
	201
bd602995	202	static struct clk_lookup periph_clocks_lookups[] = {
865d605e JI	203	/* One additional fake clock for macb_hclk */
865d605e JI	204	CLKDEV_CON_ID("hclk", &macb_clk),
bd602995 JCPV	205	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	206	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	207	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	208	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	209	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
1808958d JCPV	210	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
	211	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
	212	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
636036d2	213	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
099343c6	214	CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
302090a6 BS	215	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
302090a6 BS	216	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
fea3158c JCPV	217	/* more usart lookup table for DT entries */
	218	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	219	CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
	220	CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
	221	CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
	222	CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
	223	CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
	224	CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
f7d19b90	225	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
3a61a5da NF	226	/* more tc lookup table for DT entries */
	227	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
	228	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
	229	CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
	230	CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
	231	CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
	232	CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
6a062459	233	CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
23e3b24f	234	CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
f0db66a5 RG	235	CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
f0db66a5 RG	236	CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
0af4316b JCPV	237	/* fake hclk clock */
0af4316b JCPV	238	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
619d4a4b JCPV	239	CLKDEV_CON_ID("pioA", &pioA_clk),
	240	CLKDEV_CON_ID("pioB", &pioB_clk),
	241	CLKDEV_CON_ID("pioC", &pioC_clk),
5314ec8e JCPV	242	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
	243	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
	244	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
bd602995 JCPV	245	};
	246
	247	static struct clk_lookup usart_clocks_lookups[] = {
	248	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	249	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	250	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	251	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	252	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
	253	CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
	254	CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
	255	};
	256
62c1660d AV	257	/*
	258	* The two programmable clocks.
	259	* You must configure pin multiplexing to bring these signals out.
	260	*/
	261	static struct clk pck0 = {
	262	.name = "pck0",
	263	.pmc_mask = AT91_PMC_PCK0,
	264	.type = CLK_TYPE_PROGRAMMABLE,
	265	.id = 0,
	266	};
	267	static struct clk pck1 = {
	268	.name = "pck1",
	269	.pmc_mask = AT91_PMC_PCK1,
	270	.type = CLK_TYPE_PROGRAMMABLE,
	271	.id = 1,
	272	};
	273
	274	static void __init at91sam9260_register_clocks(void)
	275	{
	276	int i;
	277
	278	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	279	clk_register(periph_clocks[i]);
	280
bd602995 JCPV	281	clkdev_add_table(periph_clocks_lookups,
	282	ARRAY_SIZE(periph_clocks_lookups));
	283	clkdev_add_table(usart_clocks_lookups,
	284	ARRAY_SIZE(usart_clocks_lookups));
	285
62c1660d AV	286	clk_register(&pck0);
	287	clk_register(&pck1);
	288	}
	289
	290	/* --------------------------------------------------------------------
	291	* GPIO
	292	* -------------------------------------------------------------------- */
	293
1a2d9156	294	static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
62c1660d AV	295	{
62c1660d AV	296	.id = AT91SAM9260_ID_PIOA,
80e91cb8	297	.regbase = AT91SAM9260_BASE_PIOA,
62c1660d AV	298	}, {
62c1660d AV	299	.id = AT91SAM9260_ID_PIOB,
80e91cb8	300	.regbase = AT91SAM9260_BASE_PIOB,
62c1660d AV	301	}, {
62c1660d AV	302	.id = AT91SAM9260_ID_PIOC,
80e91cb8	303	.regbase = AT91SAM9260_BASE_PIOC,
62c1660d AV	304	}
	305	};
	306
62c1660d AV	307	/* --------------------------------------------------------------------
	308	* AT91SAM9260 processor initialization
	309	* -------------------------------------------------------------------- */
	310
1b021a3b	311	static void __init at91sam9xe_map_io(void)
f7eee89b	312	{
8c3583b6	313	unsigned long sram_size;
f7eee89b	314
8c3583b6	315	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
f7eee89b AV	316	case AT91_CIDR_SRAMSIZ_32K:
	317	sram_size = 2 * SZ_16K;
	318	break;
	319	case AT91_CIDR_SRAMSIZ_16K:
	320	default:
	321	sram_size = SZ_16K;
	322	}
	323
f0051d82	324	at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
f7eee89b AV	325	}
f7eee89b AV	326
21d08b9d	327	static void __init at91sam9260_map_io(void)
62c1660d	328	{
c9b1e3ff	329	if (cpu_is_at91sam9xe())
1b021a3b	330	at91sam9xe_map_io();
c9b1e3ff JCPV	331	else if (cpu_is_at91sam9g20())
	332	at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
	333	else
	334	at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
1b021a3b	335	}
f7eee89b	336
cfa5a1fe JCPV	337	static void __init at91sam9260_ioremap_registers(void)
cfa5a1fe JCPV	338	{
f22deee5	339	at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
e9f68b5c	340	at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
f363c407	341	at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
4ab0c599	342	at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
faee0cc3	343	at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
4342d647	344	at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
cfa5a1fe JCPV	345	}
cfa5a1fe JCPV	346
46539374	347	static void __init at91sam9260_initialize(void)
1b021a3b	348	{
0d781716	349	arm_pm_idle = at91sam9_idle;
1b2073e7	350	arm_pm_restart = at91sam9_alt_restart;
62c1660d AV	351	at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) \| (1 << AT91SAM9260_ID_IRQ1)
	352	\| (1 << AT91SAM9260_ID_IRQ2);
	353
62c1660d AV	354	/* Register GPIO subsystem */
	355	at91_gpio_init(at91sam9260_gpio, 3);
	356	}
	357
	358	/* --------------------------------------------------------------------
	359	* Interrupt initialization
	360	* -------------------------------------------------------------------- */
	361
	362	/*
	363	* The default interrupt priority levels (0 = lowest, 7 = highest).
	364	*/
	365	static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
	366	7, /* Advanced Interrupt Controller */
	367	7, /* System Peripherals */
7cbed2b5 AV	368	1, /* Parallel IO Controller A */
	369	1, /* Parallel IO Controller B */
	370	1, /* Parallel IO Controller C */
62c1660d	371	0, /* Analog-to-Digital Converter */
7cbed2b5 AV	372	5, /* USART 0 */
	373	5, /* USART 1 */
	374	5, /* USART 2 */
62c1660d	375	0, /* Multimedia Card Interface */
7cbed2b5 AV	376	2, /* USB Device Port */
	377	6, /* Two-Wire Interface */
	378	5, /* Serial Peripheral Interface 0 */
	379	5, /* Serial Peripheral Interface 1 */
62c1660d AV	380	5, /* Serial Synchronous Controller */
	381	0,
	382	0,
	383	0, /* Timer Counter 0 */
	384	0, /* Timer Counter 1 */
	385	0, /* Timer Counter 2 */
7cbed2b5	386	2, /* USB Host port */
62c1660d AV	387	3, /* Ethernet */
62c1660d AV	388	0, /* Image Sensor Interface */
7cbed2b5 AV	389	5, /* USART 3 */
	390	5, /* USART 4 */
	391	5, /* USART 5 */
62c1660d AV	392	0, /* Timer Counter 3 */
	393	0, /* Timer Counter 4 */
	394	0, /* Timer Counter 5 */
	395	0, /* Advanced Interrupt Controller */
	396	0, /* Advanced Interrupt Controller */
	397	0, /* Advanced Interrupt Controller */
	398	};
	399
8d39e0fd	400	AT91_SOC_START(sam9260)
21d08b9d	401	.map_io = at91sam9260_map_io,
92100c12	402	.default_irq_priority = at91sam9260_default_irq_priority,
cfa5a1fe	403	.ioremap_registers = at91sam9260_ioremap_registers,
51ddec76	404	.register_clocks = at91sam9260_register_clocks,
21d08b9d	405	.init = at91sam9260_initialize,
8d39e0fd	406	AT91_SOC_END