Commit | Line | Data |
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ef6c8445 HZ |
1 | /* |
2 | * linux/arch/arm/kernel/pj4-cp0.c | |
3 | * | |
4 | * PJ4 iWMMXt coprocessor context switching and handling | |
5 | * | |
6 | * Copyright (c) 2010 Marvell International Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/signal.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/io.h> | |
20 | #include <asm/thread_notify.h> | |
21 | ||
22 | static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t) | |
23 | { | |
24 | struct thread_info *thread = t; | |
25 | ||
26 | switch (cmd) { | |
27 | case THREAD_NOTIFY_FLUSH: | |
28 | /* | |
29 | * flush_thread() zeroes thread->fpstate, so no need | |
30 | * to do anything here. | |
31 | * | |
32 | * FALLTHROUGH: Ensure we don't try to overwrite our newly | |
33 | * initialised state information on the first fault. | |
34 | */ | |
35 | ||
36 | case THREAD_NOTIFY_EXIT: | |
37 | iwmmxt_task_release(thread); | |
38 | break; | |
39 | ||
40 | case THREAD_NOTIFY_SWITCH: | |
41 | iwmmxt_task_switch(thread); | |
42 | break; | |
43 | } | |
44 | ||
45 | return NOTIFY_DONE; | |
46 | } | |
47 | ||
48 | static struct notifier_block iwmmxt_notifier_block = { | |
49 | .notifier_call = iwmmxt_do, | |
50 | }; | |
51 | ||
52 | ||
53 | static u32 __init pj4_cp_access_read(void) | |
54 | { | |
55 | u32 value; | |
56 | ||
57 | __asm__ __volatile__ ( | |
58 | "mrc p15, 0, %0, c1, c0, 2\n\t" | |
59 | : "=r" (value)); | |
60 | return value; | |
61 | } | |
62 | ||
63 | static void __init pj4_cp_access_write(u32 value) | |
64 | { | |
65 | u32 temp; | |
66 | ||
67 | __asm__ __volatile__ ( | |
68 | "mcr p15, 0, %1, c1, c0, 2\n\t" | |
69 | "mrc p15, 0, %0, c1, c0, 2\n\t" | |
70 | "mov %0, %0\n\t" | |
71 | "sub pc, pc, #4\n\t" | |
72 | : "=r" (temp) : "r" (value)); | |
73 | } | |
74 | ||
75 | ||
76 | /* | |
77 | * Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy | |
78 | * switch code handle iWMMXt context switching. | |
79 | */ | |
80 | static int __init pj4_cp0_init(void) | |
81 | { | |
82 | u32 cp_access; | |
83 | ||
84 | cp_access = pj4_cp_access_read() & ~0xf; | |
85 | pj4_cp_access_write(cp_access); | |
86 | ||
87 | printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n"); | |
88 | elf_hwcap |= HWCAP_IWMMXT; | |
89 | thread_register_notifier(&iwmmxt_notifier_block); | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
94 | late_initcall(pj4_cp0_init); |