projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 75d90832 HC |
1 | /* |
| 2 | * linux/arch/arm/kernel/head-nommu.S | |
| 3 | * | |
| 4 | * Copyright (C) 1994-2002 Russell King | |
| 5 | * Copyright (C) 2003-2006 Hyok S. Choi | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | * | |
| 11 | * Common kernel startup code (non-paged MM) | |
| 75d90832 HC |
12 | * |
| 13 | */ | |
| 75d90832 HC |
14 | #include <linux/linkage.h> |
| 15 | #include <linux/init.h> | |
| 16 | ||
| 17 | #include <asm/assembler.h> | |
| 75d90832 | 18 | #include <asm/ptrace.h> |
| 2eb9d315 | 19 | #include <asm/asm-offsets.h> |
| 3b920cef | 20 | #include <asm/thread_info.h> |
| 75d90832 HC |
21 | #include <asm/system.h> |
| 22 | ||
| 75d90832 HC |
23 | /* |
| 24 | * Kernel startup entry point. | |
| 25 | * --------------------------- | |
| 26 | * | |
| 27 | * This is normally called from the decompressor code. The requirements | |
| 28 | * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, | |
| 29 | * r1 = machine nr. | |
| 30 | * | |
| 31 | * See linux/arch/arm/tools/mach-types for the complete list of machine | |
| 32 | * numbers for r1. | |
| 33 | * | |
| 34 | */ | |
| 2abc1c50 | 35 | __HEAD |
| 75d90832 | 36 | ENTRY(stext) |
| b86040a5 | 37 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode |
| 75d90832 | 38 | @ and irqs disabled |
| f12d0d7c HC |
39 | #ifndef CONFIG_CPU_CP15 |
| 40 | ldr r9, =CONFIG_PROCESSOR_ID | |
| 41 | #else | |
| 75d90832 | 42 | mrc p15, 0, r9, c0, c0 @ get processor id |
| f12d0d7c | 43 | #endif |
| 75d90832 HC |
44 | bl __lookup_processor_type @ r5=procinfo r9=cpuid |
| 45 | movs r10, r5 @ invalid processor (r5=0)? | |
| 46 | beq __error_p @ yes, error 'p' | |
| 47 | bl __lookup_machine_type @ r5=machinfo | |
| 48 | movs r8, r5 @ invalid machine (r5=0)? | |
| 49 | beq __error_a @ yes, error 'a' | |
| 50 | ||
| b86040a5 CM |
51 | adr lr, BSYM(__after_proc_init) @ return (PIC) address |
| 52 | ARM( add pc, r10, #PROCINFO_INITFUNC ) | |
| 53 | THUMB( add r12, r10, #PROCINFO_INITFUNC ) | |
| 54 | THUMB( mov pc, r12 ) | |
| 93ed3970 | 55 | ENDPROC(stext) |
| 75d90832 HC |
56 | |
| 57 | /* | |
| 58 | * Set the Control Register and Read the process ID. | |
| 59 | */ | |
| 75d90832 | 60 | __after_proc_init: |
| f12d0d7c | 61 | #ifdef CONFIG_CPU_CP15 |
| 05efde9d CM |
62 | /* |
| 63 | * CP15 system control register value returned in r0 from | |
| 64 | * the CPU init function. | |
| 65 | */ | |
| 75d90832 HC |
66 | #ifdef CONFIG_ALIGNMENT_TRAP |
| 67 | orr r0, r0, #CR_A | |
| 68 | #else | |
| 69 | bic r0, r0, #CR_A | |
| 70 | #endif | |
| 71 | #ifdef CONFIG_CPU_DCACHE_DISABLE | |
| 72 | bic r0, r0, #CR_C | |
| 73 | #endif | |
| 74 | #ifdef CONFIG_CPU_BPREDICT_DISABLE | |
| 75 | bic r0, r0, #CR_Z | |
| 76 | #endif | |
| 77 | #ifdef CONFIG_CPU_ICACHE_DISABLE | |
| 78 | bic r0, r0, #CR_I | |
| 6afd6fae HC |
79 | #endif |
| 80 | #ifdef CONFIG_CPU_HIGH_VECTOR | |
| 81 | orr r0, r0, #CR_V | |
| 82 | #else | |
| 83 | bic r0, r0, #CR_V | |
| 75d90832 HC |
84 | #endif |
| 85 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
| f12d0d7c | 86 | #endif /* CONFIG_CPU_CP15 */ |
| 75d90832 | 87 | |
| f131a080 | 88 | b __mmap_switched @ clear the BSS and jump |
| 75d90832 | 89 | @ to start_kernel |
| 93ed3970 | 90 | ENDPROC(__after_proc_init) |
| 3b920cef | 91 | .ltorg |
| 75d90832 HC |
92 | |
| 93 | #include "head-common.S" |