projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 75d90832 HC |
1 | /* |
| 2 | * linux/arch/arm/kernel/head-nommu.S | |
| 3 | * | |
| 4 | * Copyright (C) 1994-2002 Russell King | |
| 5 | * Copyright (C) 2003-2006 Hyok S. Choi | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | * | |
| 11 | * Common kernel startup code (non-paged MM) | |
| 75d90832 HC |
12 | * |
| 13 | */ | |
| 75d90832 HC |
14 | #include <linux/linkage.h> |
| 15 | #include <linux/init.h> | |
| 16 | ||
| 17 | #include <asm/assembler.h> | |
| 75d90832 | 18 | #include <asm/ptrace.h> |
| 2eb9d315 | 19 | #include <asm/asm-offsets.h> |
| 15d07dc9 | 20 | #include <asm/cp15.h> |
| 3b920cef | 21 | #include <asm/thread_info.h> |
| 75d90832 | 22 | |
| 75d90832 HC |
23 | /* |
| 24 | * Kernel startup entry point. | |
| 25 | * --------------------------- | |
| 26 | * | |
| 27 | * This is normally called from the decompressor code. The requirements | |
| 28 | * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, | |
| 29 | * r1 = machine nr. | |
| 30 | * | |
| 31 | * See linux/arch/arm/tools/mach-types for the complete list of machine | |
| 32 | * numbers for r1. | |
| 33 | * | |
| 34 | */ | |
| 540b5738 DM |
35 | .arm |
| 36 | ||
| 2abc1c50 | 37 | __HEAD |
| 75d90832 | 38 | ENTRY(stext) |
| 540b5738 DM |
39 | |
| 40 | THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. | |
| 41 | THUMB( bx r9 ) @ If this is a Thumb-2 kernel, | |
| 42 | THUMB( .thumb ) @ switch to Thumb now. | |
| 43 | THUMB(1: ) | |
| 44 | ||
| b86040a5 | 45 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode |
| 75d90832 | 46 | @ and irqs disabled |
| f12d0d7c HC |
47 | #ifndef CONFIG_CPU_CP15 |
| 48 | ldr r9, =CONFIG_PROCESSOR_ID | |
| 49 | #else | |
| 75d90832 | 50 | mrc p15, 0, r9, c0, c0 @ get processor id |
| f12d0d7c | 51 | #endif |
| 75d90832 HC |
52 | bl __lookup_processor_type @ r5=procinfo r9=cpuid |
| 53 | movs r10, r5 @ invalid processor (r5=0)? | |
| 54 | beq __error_p @ yes, error 'p' | |
| 75d90832 | 55 | |
| b86040a5 CM |
56 | adr lr, BSYM(__after_proc_init) @ return (PIC) address |
| 57 | ARM( add pc, r10, #PROCINFO_INITFUNC ) | |
| 58 | THUMB( add r12, r10, #PROCINFO_INITFUNC ) | |
| 59 | THUMB( mov pc, r12 ) | |
| 93ed3970 | 60 | ENDPROC(stext) |
| 75d90832 HC |
61 | |
| 62 | /* | |
| 63 | * Set the Control Register and Read the process ID. | |
| 64 | */ | |
| 75d90832 | 65 | __after_proc_init: |
| f12d0d7c | 66 | #ifdef CONFIG_CPU_CP15 |
| 05efde9d CM |
67 | /* |
| 68 | * CP15 system control register value returned in r0 from | |
| 69 | * the CPU init function. | |
| 70 | */ | |
| 76e09204 | 71 | #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 |
| 75d90832 HC |
72 | orr r0, r0, #CR_A |
| 73 | #else | |
| 74 | bic r0, r0, #CR_A | |
| 75 | #endif | |
| 76 | #ifdef CONFIG_CPU_DCACHE_DISABLE | |
| 77 | bic r0, r0, #CR_C | |
| 78 | #endif | |
| 79 | #ifdef CONFIG_CPU_BPREDICT_DISABLE | |
| 80 | bic r0, r0, #CR_Z | |
| 81 | #endif | |
| 82 | #ifdef CONFIG_CPU_ICACHE_DISABLE | |
| 83 | bic r0, r0, #CR_I | |
| 6afd6fae HC |
84 | #endif |
| 85 | #ifdef CONFIG_CPU_HIGH_VECTOR | |
| 86 | orr r0, r0, #CR_V | |
| 87 | #else | |
| 88 | bic r0, r0, #CR_V | |
| 75d90832 HC |
89 | #endif |
| 90 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
| f12d0d7c | 91 | #endif /* CONFIG_CPU_CP15 */ |
| 75d90832 | 92 | |
| f131a080 | 93 | b __mmap_switched @ clear the BSS and jump |
| 75d90832 | 94 | @ to start_kernel |
| 93ed3970 | 95 | ENDPROC(__after_proc_init) |
| 3b920cef | 96 | .ltorg |
| 75d90832 HC |
97 | |
| 98 | #include "head-common.S" |