[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / kernel / asm-offsets.c

/*
 * Copyright (C) 1995-2003 Russell King
 *               2001-2002 Keith Owens
 *     
 * Generate definitions needed by assembly language modules.
 * This code generates raw asm output which is post-processed to extract
 * and format the required data.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#ifdef CONFIG_KVM_ARM_HOST
#include <linux/kvm_host.h>
#endif
#include <asm/cacheflush.h>
#include <asm/glue-df.h>
#include <asm/glue-pf.h>
#include <asm/mach/arch.h>
#include <asm/thread_info.h>
#include <asm/memory.h>
#include <asm/procinfo.h>
#include <asm/hardware/cache-l2x0.h>
#include <linux/kbuild.h>

/*
 * Make sure that the compiler and target are compatible.
 */
#if defined(__APCS_26__)
#error Sorry, your compiler targets APCS-26 but this kernel requires APCS-32
#endif
/*
 * GCC 3.0, 3.1: general bad code generation.
 * GCC 3.2.0: incorrect function argument offset calculation.
 * GCC 3.2.x: miscompiles NEW_AUX_ENT in fs/binfmt_elf.c
 *            (http://gcc.gnu.org/PR8896) and incorrect structure
 *	      initialisation in fs/jffs2/erase.c
 */
#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
#error Your compiler is too buggy; it is known to miscompile kernels.
#error    Known good compilers: 3.3
#endif

int main(void)
{
  DEFINE(TSK_ACTIVE_MM,		offsetof(struct task_struct, active_mm));
#ifdef CONFIG_CC_STACKPROTECTOR
  DEFINE(TSK_STACK_CANARY,	offsetof(struct task_struct, stack_canary));
#endif
  BLANK();
  DEFINE(TI_FLAGS,		offsetof(struct thread_info, flags));
  DEFINE(TI_PREEMPT,		offsetof(struct thread_info, preempt_count));
  DEFINE(TI_ADDR_LIMIT,		offsetof(struct thread_info, addr_limit));
  DEFINE(TI_TASK,		offsetof(struct thread_info, task));
  DEFINE(TI_EXEC_DOMAIN,	offsetof(struct thread_info, exec_domain));
  DEFINE(TI_CPU,		offsetof(struct thread_info, cpu));
  DEFINE(TI_CPU_DOMAIN,		offsetof(struct thread_info, cpu_domain));
  DEFINE(TI_CPU_SAVE,		offsetof(struct thread_info, cpu_context));
  DEFINE(TI_USED_CP,		offsetof(struct thread_info, used_cp));
  DEFINE(TI_TP_VALUE,		offsetof(struct thread_info, tp_value));
  DEFINE(TI_FPSTATE,		offsetof(struct thread_info, fpstate));
#ifdef CONFIG_VFP
  DEFINE(TI_VFPSTATE,		offsetof(struct thread_info, vfpstate));
#ifdef CONFIG_SMP
  DEFINE(VFP_CPU,		offsetof(union vfp_state, hard.cpu));
#endif
#endif
#ifdef CONFIG_ARM_THUMBEE
  DEFINE(TI_THUMBEE_STATE,	offsetof(struct thread_info, thumbee_state));
#endif
#ifdef CONFIG_IWMMXT
  DEFINE(TI_IWMMXT_STATE,	offsetof(struct thread_info, fpstate.iwmmxt));
#endif
#ifdef CONFIG_CRUNCH
  DEFINE(TI_CRUNCH_STATE,	offsetof(struct thread_info, crunchstate));
#endif
  BLANK();
  DEFINE(S_R0,			offsetof(struct pt_regs, ARM_r0));
  DEFINE(S_R1,			offsetof(struct pt_regs, ARM_r1));
  DEFINE(S_R2,			offsetof(struct pt_regs, ARM_r2));
  DEFINE(S_R3,			offsetof(struct pt_regs, ARM_r3));
  DEFINE(S_R4,			offsetof(struct pt_regs, ARM_r4));
  DEFINE(S_R5,			offsetof(struct pt_regs, ARM_r5));
  DEFINE(S_R6,			offsetof(struct pt_regs, ARM_r6));
  DEFINE(S_R7,			offsetof(struct pt_regs, ARM_r7));
  DEFINE(S_R8,			offsetof(struct pt_regs, ARM_r8));
  DEFINE(S_R9,			offsetof(struct pt_regs, ARM_r9));
  DEFINE(S_R10,			offsetof(struct pt_regs, ARM_r10));
  DEFINE(S_FP,			offsetof(struct pt_regs, ARM_fp));
  DEFINE(S_IP,			offsetof(struct pt_regs, ARM_ip));
  DEFINE(S_SP,			offsetof(struct pt_regs, ARM_sp));
  DEFINE(S_LR,			offsetof(struct pt_regs, ARM_lr));
  DEFINE(S_PC,			offsetof(struct pt_regs, ARM_pc));
  DEFINE(S_PSR,			offsetof(struct pt_regs, ARM_cpsr));
  DEFINE(S_OLD_R0,		offsetof(struct pt_regs, ARM_ORIG_r0));
  DEFINE(S_FRAME_SIZE,		sizeof(struct pt_regs));
  BLANK();
#ifdef CONFIG_CACHE_L2X0
  DEFINE(L2X0_R_PHY_BASE,	offsetof(struct l2x0_regs, phy_base));
  DEFINE(L2X0_R_AUX_CTRL,	offsetof(struct l2x0_regs, aux_ctrl));
  DEFINE(L2X0_R_TAG_LATENCY,	offsetof(struct l2x0_regs, tag_latency));
  DEFINE(L2X0_R_DATA_LATENCY,	offsetof(struct l2x0_regs, data_latency));
  DEFINE(L2X0_R_FILTER_START,	offsetof(struct l2x0_regs, filter_start));
  DEFINE(L2X0_R_FILTER_END,	offsetof(struct l2x0_regs, filter_end));
  DEFINE(L2X0_R_PREFETCH_CTRL,	offsetof(struct l2x0_regs, prefetch_ctrl));
  DEFINE(L2X0_R_PWR_CTRL,	offsetof(struct l2x0_regs, pwr_ctrl));
  BLANK();
#endif
#ifdef CONFIG_CPU_HAS_ASID
  DEFINE(MM_CONTEXT_ID,		offsetof(struct mm_struct, context.id.counter));
  BLANK();
#endif
  DEFINE(VMA_VM_MM,		offsetof(struct vm_area_struct, vm_mm));
  DEFINE(VMA_VM_FLAGS,		offsetof(struct vm_area_struct, vm_flags));
  BLANK();
  DEFINE(VM_EXEC,	       	VM_EXEC);
  BLANK();
  DEFINE(PAGE_SZ,	       	PAGE_SIZE);
  BLANK();
  DEFINE(SYS_ERROR0,		0x9f0000);
  BLANK();
  DEFINE(SIZEOF_MACHINE_DESC,	sizeof(struct machine_desc));
  DEFINE(MACHINFO_TYPE,		offsetof(struct machine_desc, nr));
  DEFINE(MACHINFO_NAME,		offsetof(struct machine_desc, name));
  BLANK();
  DEFINE(PROC_INFO_SZ,		sizeof(struct proc_info_list));
  DEFINE(PROCINFO_INITFUNC,	offsetof(struct proc_info_list, __cpu_flush));
  DEFINE(PROCINFO_MM_MMUFLAGS,	offsetof(struct proc_info_list, __cpu_mm_mmu_flags));
  DEFINE(PROCINFO_IO_MMUFLAGS,	offsetof(struct proc_info_list, __cpu_io_mmu_flags));
  BLANK();
#ifdef MULTI_DABORT
  DEFINE(PROCESSOR_DABT_FUNC,	offsetof(struct processor, _data_abort));
#endif
#ifdef MULTI_PABORT
  DEFINE(PROCESSOR_PABT_FUNC,	offsetof(struct processor, _prefetch_abort));
#endif
#ifdef MULTI_CPU
  DEFINE(CPU_SLEEP_SIZE,	offsetof(struct processor, suspend_size));
  DEFINE(CPU_DO_SUSPEND,	offsetof(struct processor, do_suspend));
  DEFINE(CPU_DO_RESUME,		offsetof(struct processor, do_resume));
#endif
#ifdef MULTI_CACHE
  DEFINE(CACHE_FLUSH_KERN_ALL,	offsetof(struct cpu_cache_fns, flush_kern_all));
#endif
  BLANK();
  DEFINE(DMA_BIDIRECTIONAL,	DMA_BIDIRECTIONAL);
  DEFINE(DMA_TO_DEVICE,		DMA_TO_DEVICE);
  DEFINE(DMA_FROM_DEVICE,	DMA_FROM_DEVICE);
  BLANK();
  DEFINE(CACHE_WRITEBACK_ORDER, __CACHE_WRITEBACK_ORDER);
  DEFINE(CACHE_WRITEBACK_GRANULE, __CACHE_WRITEBACK_GRANULE);
  BLANK();
#ifdef CONFIG_KVM_ARM_HOST
  DEFINE(VCPU_KVM,		offsetof(struct kvm_vcpu, kvm));
  DEFINE(VCPU_MIDR,		offsetof(struct kvm_vcpu, arch.midr));
  DEFINE(VCPU_CP15,		offsetof(struct kvm_vcpu, arch.cp15));
  DEFINE(VCPU_VFP_GUEST,	offsetof(struct kvm_vcpu, arch.vfp_guest));
  DEFINE(VCPU_VFP_HOST,		offsetof(struct kvm_vcpu, arch.host_cpu_context));
  DEFINE(VCPU_REGS,		offsetof(struct kvm_vcpu, arch.regs));
  DEFINE(VCPU_USR_REGS,		offsetof(struct kvm_vcpu, arch.regs.usr_regs));
  DEFINE(VCPU_SVC_REGS,		offsetof(struct kvm_vcpu, arch.regs.svc_regs));
  DEFINE(VCPU_ABT_REGS,		offsetof(struct kvm_vcpu, arch.regs.abt_regs));
  DEFINE(VCPU_UND_REGS,		offsetof(struct kvm_vcpu, arch.regs.und_regs));
  DEFINE(VCPU_IRQ_REGS,		offsetof(struct kvm_vcpu, arch.regs.irq_regs));
  DEFINE(VCPU_FIQ_REGS,		offsetof(struct kvm_vcpu, arch.regs.fiq_regs));
  DEFINE(VCPU_PC,		offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc));
  DEFINE(VCPU_CPSR,		offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr));
  DEFINE(VCPU_IRQ_LINES,	offsetof(struct kvm_vcpu, arch.irq_lines));
  DEFINE(VCPU_HSR,		offsetof(struct kvm_vcpu, arch.fault.hsr));
  DEFINE(VCPU_HxFAR,		offsetof(struct kvm_vcpu, arch.fault.hxfar));
  DEFINE(VCPU_HPFAR,		offsetof(struct kvm_vcpu, arch.fault.hpfar));
  DEFINE(VCPU_HYP_PC,		offsetof(struct kvm_vcpu, arch.fault.hyp_pc));
#ifdef CONFIG_KVM_ARM_VGIC
  DEFINE(VCPU_VGIC_CPU,		offsetof(struct kvm_vcpu, arch.vgic_cpu));
  DEFINE(VGIC_CPU_HCR,		offsetof(struct vgic_cpu, vgic_hcr));
  DEFINE(VGIC_CPU_VMCR,		offsetof(struct vgic_cpu, vgic_vmcr));
  DEFINE(VGIC_CPU_MISR,		offsetof(struct vgic_cpu, vgic_misr));
  DEFINE(VGIC_CPU_EISR,		offsetof(struct vgic_cpu, vgic_eisr));
  DEFINE(VGIC_CPU_ELRSR,	offsetof(struct vgic_cpu, vgic_elrsr));
  DEFINE(VGIC_CPU_APR,		offsetof(struct vgic_cpu, vgic_apr));
  DEFINE(VGIC_CPU_LR,		offsetof(struct vgic_cpu, vgic_lr));
  DEFINE(VGIC_CPU_NR_LR,	offsetof(struct vgic_cpu, nr_lr));
#ifdef CONFIG_KVM_ARM_TIMER
  DEFINE(VCPU_TIMER_CNTV_CTL,	offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));
  DEFINE(VCPU_TIMER_CNTV_CVAL,	offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval));
  DEFINE(KVM_TIMER_CNTVOFF,	offsetof(struct kvm, arch.timer.cntvoff));
  DEFINE(KVM_TIMER_ENABLED,	offsetof(struct kvm, arch.timer.enabled));
#endif
  DEFINE(KVM_VGIC_VCTRL,	offsetof(struct kvm, arch.vgic.vctrl_base));
#endif
  DEFINE(KVM_VTTBR,		offsetof(struct kvm, arch.vttbr));
#endif
  return 0; 
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 1995-2003 Russell King
	3	* 2001-2002 Keith Owens
	4	*
	5	* Generate definitions needed by assembly language modules.
	6	* This code generates raw asm output which is post-processed to extract
	7	* and format the required data.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13	#include <linux/sched.h>
	14	#include <linux/mm.h>
a9c9147e	15	#include <linux/dma-mapping.h>
f7ed45be CD	16	#ifdef CONFIG_KVM_ARM_HOST
	17	#include <linux/kvm_host.h>
	18	#endif
f6b0fa02	19	#include <asm/cacheflush.h>
753790e7 RK	20	#include <asm/glue-df.h>
753790e7 RK	21	#include <asm/glue-pf.h>
1da177e4 LT	22	#include <asm/mach/arch.h>
	23	#include <asm/thread_info.h>
	24	#include <asm/memory.h>
ee90dabc	25	#include <asm/procinfo.h>
91c2ebb9	26	#include <asm/hardware/cache-l2x0.h>
02cbe474	27	#include <linux/kbuild.h>
1da177e4 LT	28
	29	/*
	30	* Make sure that the compiler and target are compatible.
	31	*/
	32	#if defined(__APCS_26__)
	33	#error Sorry, your compiler targets APCS-26 but this kernel requires APCS-32
	34	#endif
	35	/*
1da177e4 LT	36	* GCC 3.0, 3.1: general bad code generation.
	37	* GCC 3.2.0: incorrect function argument offset calculation.
	38	* GCC 3.2.x: miscompiles NEW_AUX_ENT in fs/binfmt_elf.c
	39	* (http://gcc.gnu.org/PR8896) and incorrect structure
	40	* initialisation in fs/jffs2/erase.c
	41	*/
a1365647	42	#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
1da177e4	43	#error Your compiler is too buggy; it is known to miscompile kernels.
a1365647	44	#error Known good compilers: 3.3
1da177e4 LT	45	#endif
1da177e4 LT	46
1da177e4 LT	47	int main(void)
	48	{
	49	DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
df0698be NP	50	#ifdef CONFIG_CC_STACKPROTECTOR
	51	DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary));
	52	#endif
1da177e4 LT	53	BLANK();
	54	DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
	55	DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
	56	DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit));
	57	DEFINE(TI_TASK, offsetof(struct thread_info, task));
	58	DEFINE(TI_EXEC_DOMAIN, offsetof(struct thread_info, exec_domain));
	59	DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
	60	DEFINE(TI_CPU_DOMAIN, offsetof(struct thread_info, cpu_domain));
	61	DEFINE(TI_CPU_SAVE, offsetof(struct thread_info, cpu_context));
	62	DEFINE(TI_USED_CP, offsetof(struct thread_info, used_cp));
	63	DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value));
	64	DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate));
9fc31ddc	65	#ifdef CONFIG_VFP
1da177e4	66	DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate));
f8f2a852 RK	67	#ifdef CONFIG_SMP
	68	DEFINE(VFP_CPU, offsetof(union vfp_state, hard.cpu));
	69	#endif
9fc31ddc	70	#endif
d7f864be CM	71	#ifdef CONFIG_ARM_THUMBEE
	72	DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state));
	73	#endif
cdaabbd7 RK	74	#ifdef CONFIG_IWMMXT
cdaabbd7 RK	75	DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt));
c17fad11 LB	76	#endif
	77	#ifdef CONFIG_CRUNCH
	78	DEFINE(TI_CRUNCH_STATE, offsetof(struct thread_info, crunchstate));
cdaabbd7	79	#endif
1da177e4	80	BLANK();
925c8a1a RK	81	DEFINE(S_R0, offsetof(struct pt_regs, ARM_r0));
	82	DEFINE(S_R1, offsetof(struct pt_regs, ARM_r1));
	83	DEFINE(S_R2, offsetof(struct pt_regs, ARM_r2));
	84	DEFINE(S_R3, offsetof(struct pt_regs, ARM_r3));
	85	DEFINE(S_R4, offsetof(struct pt_regs, ARM_r4));
	86	DEFINE(S_R5, offsetof(struct pt_regs, ARM_r5));
	87	DEFINE(S_R6, offsetof(struct pt_regs, ARM_r6));
	88	DEFINE(S_R7, offsetof(struct pt_regs, ARM_r7));
	89	DEFINE(S_R8, offsetof(struct pt_regs, ARM_r8));
	90	DEFINE(S_R9, offsetof(struct pt_regs, ARM_r9));
	91	DEFINE(S_R10, offsetof(struct pt_regs, ARM_r10));
	92	DEFINE(S_FP, offsetof(struct pt_regs, ARM_fp));
	93	DEFINE(S_IP, offsetof(struct pt_regs, ARM_ip));
	94	DEFINE(S_SP, offsetof(struct pt_regs, ARM_sp));
	95	DEFINE(S_LR, offsetof(struct pt_regs, ARM_lr));
	96	DEFINE(S_PC, offsetof(struct pt_regs, ARM_pc));
	97	DEFINE(S_PSR, offsetof(struct pt_regs, ARM_cpsr));
	98	DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0));
	99	DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
	100	BLANK();
91c2ebb9 BS	101	#ifdef CONFIG_CACHE_L2X0
	102	DEFINE(L2X0_R_PHY_BASE, offsetof(struct l2x0_regs, phy_base));
	103	DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl));
	104	DEFINE(L2X0_R_TAG_LATENCY, offsetof(struct l2x0_regs, tag_latency));
	105	DEFINE(L2X0_R_DATA_LATENCY, offsetof(struct l2x0_regs, data_latency));
	106	DEFINE(L2X0_R_FILTER_START, offsetof(struct l2x0_regs, filter_start));
	107	DEFINE(L2X0_R_FILTER_END, offsetof(struct l2x0_regs, filter_end));
	108	DEFINE(L2X0_R_PREFETCH_CTRL, offsetof(struct l2x0_regs, prefetch_ctrl));
	109	DEFINE(L2X0_R_PWR_CTRL, offsetof(struct l2x0_regs, pwr_ctrl));
	110	BLANK();
	111	#endif
516793c6	112	#ifdef CONFIG_CPU_HAS_ASID
8a4e3a9e	113	DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
1da177e4 LT	114	BLANK();
	115	#endif
	116	DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
	117	DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
	118	BLANK();
	119	DEFINE(VM_EXEC, VM_EXEC);
	120	BLANK();
	121	DEFINE(PAGE_SZ, PAGE_SIZE);
1da177e4 LT	122	BLANK();
	123	DEFINE(SYS_ERROR0, 0x9f0000);
	124	BLANK();
	125	DEFINE(SIZEOF_MACHINE_DESC, sizeof(struct machine_desc));
2eb9d315 UZ	126	DEFINE(MACHINFO_TYPE, offsetof(struct machine_desc, nr));
2eb9d315 UZ	127	DEFINE(MACHINFO_NAME, offsetof(struct machine_desc, name));
2ceec0c8 UZ	128	BLANK();
2ceec0c8 UZ	129	DEFINE(PROC_INFO_SZ, sizeof(struct proc_info_list));
2eb9d315	130	DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush));
8799ee9f RK	131	DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags));
8799ee9f RK	132	DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags));
48d7927b PB	133	BLANK();
	134	#ifdef MULTI_DABORT
	135	DEFINE(PROCESSOR_DABT_FUNC, offsetof(struct processor, _data_abort));
	136	#endif
	137	#ifdef MULTI_PABORT
	138	DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort));
f6b0fa02 RK	139	#endif
	140	#ifdef MULTI_CPU
	141	DEFINE(CPU_SLEEP_SIZE, offsetof(struct processor, suspend_size));
	142	DEFINE(CPU_DO_SUSPEND, offsetof(struct processor, do_suspend));
	143	DEFINE(CPU_DO_RESUME, offsetof(struct processor, do_resume));
	144	#endif
	145	#ifdef MULTI_CACHE
	146	DEFINE(CACHE_FLUSH_KERN_ALL, offsetof(struct cpu_cache_fns, flush_kern_all));
48d7927b	147	#endif
a9c9147e RK	148	BLANK();
	149	DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
	150	DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
	151	DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
7fe31d28	152	BLANK();
1ae98561	153	DEFINE(CACHE_WRITEBACK_ORDER, __CACHE_WRITEBACK_ORDER);
7fe31d28 DM	154	DEFINE(CACHE_WRITEBACK_GRANULE, __CACHE_WRITEBACK_GRANULE);
7fe31d28 DM	155	BLANK();
f7ed45be CD	156	#ifdef CONFIG_KVM_ARM_HOST
	157	DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
	158	DEFINE(VCPU_MIDR, offsetof(struct kvm_vcpu, arch.midr));
	159	DEFINE(VCPU_CP15, offsetof(struct kvm_vcpu, arch.cp15));
	160	DEFINE(VCPU_VFP_GUEST, offsetof(struct kvm_vcpu, arch.vfp_guest));
3de50da6	161	DEFINE(VCPU_VFP_HOST, offsetof(struct kvm_vcpu, arch.host_cpu_context));
f7ed45be CD	162	DEFINE(VCPU_REGS, offsetof(struct kvm_vcpu, arch.regs));
	163	DEFINE(VCPU_USR_REGS, offsetof(struct kvm_vcpu, arch.regs.usr_regs));
	164	DEFINE(VCPU_SVC_REGS, offsetof(struct kvm_vcpu, arch.regs.svc_regs));
	165	DEFINE(VCPU_ABT_REGS, offsetof(struct kvm_vcpu, arch.regs.abt_regs));
	166	DEFINE(VCPU_UND_REGS, offsetof(struct kvm_vcpu, arch.regs.und_regs));
	167	DEFINE(VCPU_IRQ_REGS, offsetof(struct kvm_vcpu, arch.regs.irq_regs));
	168	DEFINE(VCPU_FIQ_REGS, offsetof(struct kvm_vcpu, arch.regs.fiq_regs));
	169	DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc));
	170	DEFINE(VCPU_CPSR, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr));
	171	DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines));
7393b599 MZ	172	DEFINE(VCPU_HSR, offsetof(struct kvm_vcpu, arch.fault.hsr));
	173	DEFINE(VCPU_HxFAR, offsetof(struct kvm_vcpu, arch.fault.hxfar));
	174	DEFINE(VCPU_HPFAR, offsetof(struct kvm_vcpu, arch.fault.hpfar));
	175	DEFINE(VCPU_HYP_PC, offsetof(struct kvm_vcpu, arch.fault.hyp_pc));
348b2b07 MZ	176	#ifdef CONFIG_KVM_ARM_VGIC
	177	DEFINE(VCPU_VGIC_CPU, offsetof(struct kvm_vcpu, arch.vgic_cpu));
	178	DEFINE(VGIC_CPU_HCR, offsetof(struct vgic_cpu, vgic_hcr));
	179	DEFINE(VGIC_CPU_VMCR, offsetof(struct vgic_cpu, vgic_vmcr));
	180	DEFINE(VGIC_CPU_MISR, offsetof(struct vgic_cpu, vgic_misr));
	181	DEFINE(VGIC_CPU_EISR, offsetof(struct vgic_cpu, vgic_eisr));
	182	DEFINE(VGIC_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_elrsr));
	183	DEFINE(VGIC_CPU_APR, offsetof(struct vgic_cpu, vgic_apr));
	184	DEFINE(VGIC_CPU_LR, offsetof(struct vgic_cpu, vgic_lr));
	185	DEFINE(VGIC_CPU_NR_LR, offsetof(struct vgic_cpu, nr_lr));
c7e3ba64 MZ	186	#ifdef CONFIG_KVM_ARM_TIMER
	187	DEFINE(VCPU_TIMER_CNTV_CTL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));
	188	DEFINE(VCPU_TIMER_CNTV_CVAL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval));
	189	DEFINE(KVM_TIMER_CNTVOFF, offsetof(struct kvm, arch.timer.cntvoff));
	190	DEFINE(KVM_TIMER_ENABLED, offsetof(struct kvm, arch.timer.enabled));
	191	#endif
348b2b07 MZ	192	DEFINE(KVM_VGIC_VCTRL, offsetof(struct kvm, arch.vgic.vctrl_base));
348b2b07 MZ	193	#endif
f7ed45be CD	194	DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr));
f7ed45be CD	195	#endif
1da177e4 LT	196	return 0;
1da177e4 LT	197	}