[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / common / timer-sp.c

/*
 *  linux/arch/arm/common/timer-sp.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>

#include <asm/hardware/arm_timer.h>

/*
 * These timers are currently always setup to be clocked at 1MHz.
 */
#define TIMER_FREQ_KHZ	(1000)
#define TIMER_RELOAD	(TIMER_FREQ_KHZ * 1000 / HZ)

static void __iomem *clksrc_base;

static cycle_t sp804_read(struct clocksource *cs)
{
	return ~readl(clksrc_base + TIMER_VALUE);
}

static struct clocksource clocksource_sp804 = {
	.name		= "timer3",
	.rating		= 200,
	.read		= sp804_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

void __init sp804_clocksource_init(void __iomem *base)
{
	struct clocksource *cs = &clocksource_sp804;

	clksrc_base = base;

	/* setup timer 0 as free-running clocksource */
	writel(0, clksrc_base + TIMER_CTRL);
	writel(0xffffffff, clksrc_base + TIMER_LOAD);
	writel(0xffffffff, clksrc_base + TIMER_VALUE);
	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
		clksrc_base + TIMER_CTRL);

	clocksource_register_khz(cs, TIMER_FREQ_KHZ);
}


static void __iomem *clkevt_base;

/*
 * IRQ handler for the timer
 */
static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void sp804_set_mode(enum clock_event_mode mode,
	struct clock_event_device *evt)
{
	unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;

	writel(ctrl, clkevt_base + TIMER_CTRL);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD);
		ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		/* period set, and timer enabled in 'next_event' hook */
		ctrl |= TIMER_CTRL_ONESHOT;
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		break;
	}

	writel(ctrl, clkevt_base + TIMER_CTRL);
}

static int sp804_set_next_event(unsigned long next,
	struct clock_event_device *evt)
{
	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);

	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device sp804_clockevent = {
	.name		= "timer0",
	.shift		= 32,
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= sp804_set_mode,
	.set_next_event	= sp804_set_next_event,
	.rating		= 300,
	.cpumask	= cpu_all_mask,
};

static struct irqaction sp804_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= sp804_timer_interrupt,
	.dev_id		= &sp804_clockevent,
};

void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq)
{
	struct clock_event_device *evt = &sp804_clockevent;

	clkevt_base = base;

	evt->irq = timer_irq;
	evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift);
	evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
	evt->min_delta_ns = clockevent_delta2ns(0xf, evt);

	setup_irq(timer_irq, &sp804_timer_irq);
	clockevents_register_device(evt);
}
Commit	Line	Data
e3887714	1	/*
8a9618f5	2	* linux/arch/arm/common/timer-sp.c
e3887714 RK	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21	#include <linux/clocksource.h>
	22	#include <linux/clockchips.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/irq.h>
	25	#include <linux/io.h>
	26
	27	#include <asm/hardware/arm_timer.h>
	28
e3887714	29	/*
4ce17552	30	* These timers are currently always setup to be clocked at 1MHz.
e3887714	31	*/
4ce17552 RK	32	#define TIMER_FREQ_KHZ (1000)
4ce17552 RK	33	#define TIMER_RELOAD (TIMER_FREQ_KHZ * 1000 / HZ)
e3887714 RK	34
	35	static void __iomem *clksrc_base;
	36
	37	static cycle_t sp804_read(struct clocksource *cs)
	38	{
	39	return ~readl(clksrc_base + TIMER_VALUE);
	40	}
	41
	42	static struct clocksource clocksource_sp804 = {
	43	.name = "timer3",
	44	.rating = 200,
	45	.read = sp804_read,
	46	.mask = CLOCKSOURCE_MASK(32),
e3887714 RK	47	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	48	};
	49
	50	void __init sp804_clocksource_init(void __iomem *base)
	51	{
	52	struct clocksource *cs = &clocksource_sp804;
	53
	54	clksrc_base = base;
	55
	56	/* setup timer 0 as free-running clocksource */
	57	writel(0, clksrc_base + TIMER_CTRL);
	58	writel(0xffffffff, clksrc_base + TIMER_LOAD);
	59	writel(0xffffffff, clksrc_base + TIMER_VALUE);
	60	writel(TIMER_CTRL_32BIT \| TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC,
	61	clksrc_base + TIMER_CTRL);
	62
11e718a6	63	clocksource_register_khz(cs, TIMER_FREQ_KHZ);
e3887714 RK	64	}
	65
	66
	67	static void __iomem *clkevt_base;
	68
	69	/*
	70	* IRQ handler for the timer
	71	*/
	72	static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
	73	{
	74	struct clock_event_device *evt = dev_id;
	75
	76	/* clear the interrupt */
	77	writel(1, clkevt_base + TIMER_INTCLR);
	78
	79	evt->event_handler(evt);
	80
	81	return IRQ_HANDLED;
	82	}
	83
	84	static void sp804_set_mode(enum clock_event_mode mode,
	85	struct clock_event_device *evt)
	86	{
	87	unsigned long ctrl = TIMER_CTRL_32BIT \| TIMER_CTRL_IE;
	88
	89	writel(ctrl, clkevt_base + TIMER_CTRL);
	90
	91	switch (mode) {
	92	case CLOCK_EVT_MODE_PERIODIC:
	93	writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD);
	94	ctrl \|= TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
	95	break;
	96
	97	case CLOCK_EVT_MODE_ONESHOT:
	98	/* period set, and timer enabled in 'next_event' hook */
	99	ctrl \|= TIMER_CTRL_ONESHOT;
	100	break;
	101
	102	case CLOCK_EVT_MODE_UNUSED:
	103	case CLOCK_EVT_MODE_SHUTDOWN:
	104	default:
	105	break;
	106	}
	107
	108	writel(ctrl, clkevt_base + TIMER_CTRL);
	109	}
	110
	111	static int sp804_set_next_event(unsigned long next,
	112	struct clock_event_device *evt)
	113	{
	114	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
	115
	116	writel(next, clkevt_base + TIMER_LOAD);
	117	writel(ctrl \| TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	118
	119	return 0;
	120	}
	121
	122	static struct clock_event_device sp804_clockevent = {
	123	.name = "timer0",
	124	.shift = 32,
	125	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	126	.set_mode = sp804_set_mode,
	127	.set_next_event = sp804_set_next_event,
128	.rating = 300,
129	.cpumask = cpu_all_mask,
130	};
131
132	static struct irqaction sp804_timer_irq = {
133	.name = "timer",
134	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
135	.handler = sp804_timer_interrupt,
136	.dev_id = &sp804_clockevent,
137	};
138
139	void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq)
140	{
141	struct clock_event_device *evt = &sp804_clockevent;
142
143	clkevt_base = base;
144
145	evt->irq = timer_irq;
4ce17552	146	evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift);
e3887714 RK	147	evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
	148	evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
	149
	150	setup_irq(timer_irq, &sp804_timer_irq);
	151	clockevents_register_device(evt);
	152	}