[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / boot / dts / versatile-ab.dts

/dts-v1/;
/include/ "skeleton.dtsi"

/ {
	model = "ARM Versatile AB";
	compatible = "arm,versatile-ab";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&vic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		i2c0 = &i2c0;
	};

	memory {
		reg = <0x0 0x08000000>;
	};

	flash@34000000 {
		compatible = "arm,versatile-flash";
		reg = <0x34000000 0x4000000>;
		bank-width = <4>;
	};

	i2c0: i2c@10002000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "arm,versatile-i2c";
		reg = <0x10002000 0x1000>;

		rtc@68 {
			compatible = "dallas,ds1338";
			reg = <0x68>;
		};
	};

	net@10010000 {
		compatible = "smsc,lan91c111";
		reg = <0x10010000 0x10000>;
		interrupts = <25>;
	};

	lcd@10008000 {
		compatible = "arm,versatile-lcd";
		reg = <0x10008000 0x1000>;
	};

	amba {
		compatible = "arm,amba-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		vic: intc@10140000 {
			compatible = "arm,versatile-vic";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x10140000 0x1000>;
		};

		sic: intc@10003000 {
			compatible = "arm,versatile-sic";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x10003000 0x1000>;
			interrupt-parent = <&vic>;
			interrupts = <31>; /* Cascaded to vic */
		};

		dma@10130000 {
			compatible = "arm,pl081", "arm,primecell";
			reg = <0x10130000 0x1000>;
			interrupts = <17>;
		};

		uart0: uart@101f1000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f1000 0x1000>;
			interrupts = <12>;
		};

		uart1: uart@101f2000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f2000 0x1000>;
			interrupts = <13>;
		};

		uart2: uart@101f3000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f3000 0x1000>;
			interrupts = <14>;
		};

		smc@10100000 {
			compatible = "arm,primecell";
			reg = <0x10100000 0x1000>;
		};

		mpmc@10110000 {
			compatible = "arm,primecell";
			reg = <0x10110000 0x1000>;
		};

		display@10120000 {
			compatible = "arm,pl110", "arm,primecell";
			reg = <0x10120000 0x1000>;
			interrupts = <16>;
		};

		sctl@101e0000 {
			compatible = "arm,primecell";
			reg = <0x101e0000 0x1000>;
		};

		watchdog@101e1000 {
			compatible = "arm,primecell";
			reg = <0x101e1000 0x1000>;
			interrupts = <0>;
		};

		gpio0: gpio@101e4000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x101e4000 0x1000>;
			gpio-controller;
			interrupts = <6>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@101e5000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x101e5000 0x1000>;
			interrupts = <7>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		rtc@101e8000 {
			compatible = "arm,pl030", "arm,primecell";
			reg = <0x101e8000 0x1000>;
			interrupts = <10>;
		};

		sci@101f0000 {
			compatible = "arm,primecell";
			reg = <0x101f0000 0x1000>;
			interrupts = <15>;
		};

		ssp@101f4000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x101f4000 0x1000>;
			interrupts = <11>;
		};

		fpga {
			compatible = "arm,versatile-fpga", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x10000000 0x10000>;

			aaci@4000 {
				compatible = "arm,primecell";
				reg = <0x4000 0x1000>;
				interrupts = <24>;
			};
			mmc@5000 {
				compatible = "arm,primecell";
				reg = < 0x5000 0x1000>;
				interrupts = <22 34>;
			};
			kmi@6000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x6000 0x1000>;
				interrupt-parent = <&sic>;
				interrupts = <3>;
			};
			kmi@7000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x7000 0x1000>;
				interrupt-parent = <&sic>;
				interrupts = <4>;
			};
		};
	};
};
Commit	Line	Data
3ba7222a GL	1	/dts-v1/;
	2	/include/ "skeleton.dtsi"
	3
	4	/ {
	5	model = "ARM Versatile AB";
	6	compatible = "arm,versatile-ab";
	7	#address-cells = <1>;
	8	#size-cells = <1>;
	9	interrupt-parent = <&vic>;
	10
	11	aliases {
	12	serial0 = &uart0;
	13	serial1 = &uart1;
	14	serial2 = &uart2;
	15	i2c0 = &i2c0;
	16	};
	17
	18	memory {
	19	reg = <0x0 0x08000000>;
	20	};
	21
	22	flash@34000000 {
	23	compatible = "arm,versatile-flash";
	24	reg = <0x34000000 0x4000000>;
	25	bank-width = <4>;
	26	};
	27
	28	i2c0: i2c@10002000 {
	29	#address-cells = <1>;
	30	#size-cells = <0>;
	31	compatible = "arm,versatile-i2c";
	32	reg = <0x10002000 0x1000>;
	33
	34	rtc@68 {
	35	compatible = "dallas,ds1338";
	36	reg = <0x68>;
	37	};
	38	};
	39
	40	net@10010000 {
	41	compatible = "smsc,lan91c111";
	42	reg = <0x10010000 0x10000>;
	43	interrupts = <25>;
	44	};
	45
	46	lcd@10008000 {
	47	compatible = "arm,versatile-lcd";
	48	reg = <0x10008000 0x1000>;
	49	};
	50
	51	amba {
	52	compatible = "arm,amba-bus";
	53	#address-cells = <1>;
	54	#size-cells = <1>;
	55	ranges;
	56
	57	vic: intc@10140000 {
	58	compatible = "arm,versatile-vic";
	59	interrupt-controller;
	60	#interrupt-cells = <1>;
	61	reg = <0x10140000 0x1000>;
	62	};
	63
	64	sic: intc@10003000 {
65	compatible = "arm,versatile-sic";
66	interrupt-controller;
67	#interrupt-cells = <1>;
68	reg = <0x10003000 0x1000>;
69	interrupt-parent = <&vic>;
70	interrupts = <31>; /* Cascaded to vic */
71	};
72
73	dma@10130000 {
74	compatible = "arm,pl081", "arm,primecell";
75	reg = <0x10130000 0x1000>;
76	interrupts = <17>;
77	};
78
79	uart0: uart@101f1000 {
80	compatible = "arm,pl011", "arm,primecell";
81	reg = <0x101f1000 0x1000>;
82	interrupts = <12>;
83	};
84
85	uart1: uart@101f2000 {
86	compatible = "arm,pl011", "arm,primecell";
87	reg = <0x101f2000 0x1000>;
88	interrupts = <13>;
89	};
90
91	uart2: uart@101f3000 {
92	compatible = "arm,pl011", "arm,primecell";
93	reg = <0x101f3000 0x1000>;
94	interrupts = <14>;
95	};
96
97	smc@10100000 {
98	compatible = "arm,primecell";
99	reg = <0x10100000 0x1000>;
100	};
101
102	mpmc@10110000 {
103	compatible = "arm,primecell";
104	reg = <0x10110000 0x1000>;
105	};
106
107	display@10120000 {
108	compatible = "arm,pl110", "arm,primecell";
109	reg = <0x10120000 0x1000>;
110	interrupts = <16>;
111	};
112
113	sctl@101e0000 {
114	compatible = "arm,primecell";
115	reg = <0x101e0000 0x1000>;
116	};
117
118	watchdog@101e1000 {
119	compatible = "arm,primecell";
120	reg = <0x101e1000 0x1000>;
121	interrupts = <0>;
122	};
123
124	gpio0: gpio@101e4000 {
125	compatible = "arm,pl061", "arm,primecell";
126	reg = <0x101e4000 0x1000>;
127	gpio-controller;
128	interrupts = <6>;
129	#gpio-cells = <2>;
130	interrupt-controller;
131	#interrupt-cells = <2>;
132	};
133
134	gpio1: gpio@101e5000 {
135	compatible = "arm,pl061", "arm,primecell";
136	reg = <0x101e5000 0x1000>;
137	interrupts = <7>;
138	gpio-controller;
139	#gpio-cells = <2>;
140	interrupt-controller;
141	#interrupt-cells = <2>;
142	};
143
144	rtc@101e8000 {
145	compatible = "arm,pl030", "arm,primecell";
146	reg = <0x101e8000 0x1000>;
147	interrupts = <10>;
148	};
149
150	sci@101f0000 {
151	compatible = "arm,primecell";
152	reg = <0x101f0000 0x1000>;
153	interrupts = <15>;
154	};
155
156	ssp@101f4000 {
157	compatible = "arm,pl022", "arm,primecell";
158	reg = <0x101f4000 0x1000>;
159	interrupts = <11>;
160	};
161
162	fpga {
163	compatible = "arm,versatile-fpga", "simple-bus";
164	#address-cells = <1>;
165	#size-cells = <1>;
166	ranges = <0 0x10000000 0x10000>;
167
168	aaci@4000 {
169	compatible = "arm,primecell";
170	reg = <0x4000 0x1000>;
171	interrupts = <24>;
172	};
173	mmc@5000 {
174	compatible = "arm,primecell";
175	reg = < 0x5000 0x1000>;
754aba43	176	interrupts = <22 34>;
3ba7222a GL	177	};
	178	kmi@6000 {
	179	compatible = "arm,pl050", "arm,primecell";
	180	reg = <0x6000 0x1000>;
	181	interrupt-parent = <&sic>;
	182	interrupts = <3>;
	183	};
	184	kmi@7000 {
	185	compatible = "arm,pl050", "arm,primecell";
	186	reg = <0x7000 0x1000>;
	187	interrupt-parent = <&sic>;
	188	interrupts = <4>;
	189	};
	190	};
	191	};
	192	};