[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / arch / arm / boot / dts / uniphier-proxstream2.dtsi

/*
 * Device Tree Source for UniPhier ProXstream2 SoC
 *
 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/include/ "skeleton.dtsi"

/ {
	compatible = "socionext,proxstream2";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "socionext,uniphier-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
		};
	};

	clocks {
		arm_timer_clk: arm_timer_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};

		uart_clk: uart_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <88900000>;
		};

		i2c_clk: i2c_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		extbus: extbus {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <1>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			interrupts = <0 33 4>;
			clocks = <&uart_clk>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			interrupts = <0 35 4>;
			clocks = <&uart_clk>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			interrupts = <0 37 4>;
			clocks = <&uart_clk>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			interrupts = <0 177 4>;
			clocks = <&uart_clk>;
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			interrupts = <0 41 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			interrupts = <0 42 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			interrupts = <0 43 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			interrupts = <0 44 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c4: i2c@58784000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58784000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for STM */
		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 25 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for HDMI */
		i2c6: i2c@58786000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58786000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 26 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <400000>;
		};

		system-bus-controller-misc@59800000 {
			compatible = "socionext,uniphier-system-bus-controller-misc",
				     "syscon";
			reg = <0x59800000 0x2000>;
		};

		pinctrl: pinctrl@5f801000 {
			compatible = "socionext,proxstream2-pinctrl", "syscon";
			reg = <0x5f801000 0xe00>;
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <1 11 0x304>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <1 13 0x304>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
		};
	};
};

/include/ "uniphier-pinctrl.dtsi"
Commit	Line	Data
a5e921b4 MY	1	/*
	2	* Device Tree Source for UniPhier ProXstream2 SoC
	3	*
	4	* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
	45	/include/ "skeleton.dtsi"
	46
	47	/ {
	48	compatible = "socionext,proxstream2";
	49
	50	cpus {
	51	#address-cells = <1>;
	52	#size-cells = <0>;
	53	enable-method = "socionext,uniphier-smp";
	54
	55	cpu@0 {
	56	device_type = "cpu";
	57	compatible = "arm,cortex-a9";
	58	reg = <0>;
	59	};
	60
	61	cpu@1 {
	62	device_type = "cpu";
	63	compatible = "arm,cortex-a9";
	64	reg = <1>;
65	};
66
67	cpu@2 {
68	device_type = "cpu";
69	compatible = "arm,cortex-a9";
70	reg = <2>;
71	};
72
73	cpu@3 {
74	device_type = "cpu";
75	compatible = "arm,cortex-a9";
76	reg = <3>;
77	};
78	};
79
80	clocks {
81	arm_timer_clk: arm_timer_clk {
82	#clock-cells = <0>;
83	compatible = "fixed-clock";
84	clock-frequency = <50000000>;
85	};
86
87	uart_clk: uart_clk {
88	#clock-cells = <0>;
89	compatible = "fixed-clock";
90	clock-frequency = <88900000>;
91	};
92
93	i2c_clk: i2c_clk {
94	#clock-cells = <0>;
95	compatible = "fixed-clock";
96	clock-frequency = <50000000>;
97	};
98	};
99
100	soc {
101	compatible = "simple-bus";
102	#address-cells = <1>;
103	#size-cells = <1>;
104	ranges;
105	interrupt-parent = <&intc>;
106
107	extbus: extbus {
108	compatible = "simple-bus";
109	#address-cells = <2>;
110	#size-cells = <1>;
111	};
112
113	serial0: serial@54006800 {
114	compatible = "socionext,uniphier-uart";
115	status = "disabled";
116	reg = <0x54006800 0x40>;
117	pinctrl-names = "default";
118	pinctrl-0 = <&pinctrl_uart0>;
119	interrupts = <0 33 4>;
120	clocks = <&uart_clk>;
121	};
122
123	serial1: serial@54006900 {
124	compatible = "socionext,uniphier-uart";
125	status = "disabled";
126	reg = <0x54006900 0x40>;
127	pinctrl-names = "default";
128	pinctrl-0 = <&pinctrl_uart1>;
129	interrupts = <0 35 4>;
130	clocks = <&uart_clk>;
131	};
132
133	serial2: serial@54006a00 {
134	compatible = "socionext,uniphier-uart";
135	status = "disabled";
136	reg = <0x54006a00 0x40>;
137	pinctrl-names = "default";
138	pinctrl-0 = <&pinctrl_uart2>;
139	interrupts = <0 37 4>;
140	clocks = <&uart_clk>;
141	};
142
143	serial3: serial@54006b00 {
144	compatible = "socionext,uniphier-uart";
145	status = "disabled";
146	reg = <0x54006b00 0x40>;
147	pinctrl-names = "default";
148	pinctrl-0 = <&pinctrl_uart3>;
149	interrupts = <0 177 4>;
150	clocks = <&uart_clk>;
151	};
152
153	i2c0: i2c@58780000 {
154	compatible = "socionext,uniphier-fi2c";
155	status = "disabled";
156	reg = <0x58780000 0x80>;
157	#address-cells = <1>;
158	#size-cells = <0>;
159	pinctrl-names = "default";
160	pinctrl-0 = <&pinctrl_i2c0>;
161	interrupts = <0 41 4>;
162	clocks = <&i2c_clk>;
163	clock-frequency = <100000>;
164	};
165
166	i2c1: i2c@58781000 {
167	compatible = "socionext,uniphier-fi2c";
168	status = "disabled";
169	reg = <0x58781000 0x80>;
170	#address-cells = <1>;
171	#size-cells = <0>;
172	pinctrl-names = "default";
173	pinctrl-0 = <&pinctrl_i2c1>;
174	interrupts = <0 42 4>;
175	clocks = <&i2c_clk>;
176	clock-frequency = <100000>;
177	};
178
179	i2c2: i2c@58782000 {
180	compatible = "socionext,uniphier-fi2c";
181	status = "disabled";
182	reg = <0x58782000 0x80>;
183	#address-cells = <1>;
184	#size-cells = <0>;
185	pinctrl-names = "default";
186	pinctrl-0 = <&pinctrl_i2c2>;
187	interrupts = <0 43 4>;
188	clocks = <&i2c_clk>;
189	clock-frequency = <100000>;
190	};
191
192	i2c3: i2c@58783000 {
193	compatible = "socionext,uniphier-fi2c";
194	status = "disabled";
195	reg = <0x58783000 0x80>;
196	#address-cells = <1>;
197	#size-cells = <0>;
198	pinctrl-names = "default";
199	pinctrl-0 = <&pinctrl_i2c3>;
200	interrupts = <0 44 4>;
201	clocks = <&i2c_clk>;
202	clock-frequency = <100000>;
203	};
204
205	/* chip-internal connection for DMD */
206	i2c4: i2c@58784000 {
207	compatible = "socionext,uniphier-fi2c";
208	reg = <0x58784000 0x80>;
209	#address-cells = <1>;
210	#size-cells = <0>;
211	interrupts = <0 45 4>;
212	clocks = <&i2c_clk>;
213	clock-frequency = <400000>;
214	};
215
216	/* chip-internal connection for STM */
217	i2c5: i2c@58785000 {
218	compatible = "socionext,uniphier-fi2c";
219	reg = <0x58785000 0x80>;
220	#address-cells = <1>;
221	#size-cells = <0>;
222	interrupts = <0 25 4>;
223	clocks = <&i2c_clk>;
224	clock-frequency = <400000>;
225	};
226
227	/* chip-internal connection for HDMI */
228	i2c6: i2c@58786000 {
229	compatible = "socionext,uniphier-fi2c";
230	reg = <0x58786000 0x80>;
231	#address-cells = <1>;
232	#size-cells = <0>;
233	interrupts = <0 26 4>;
234	clocks = <&i2c_clk>;
235	clock-frequency = <400000>;
236	};
237
238	system-bus-controller-misc@59800000 {
239	compatible = "socionext,uniphier-system-bus-controller-misc",
240	"syscon";
241	reg = <0x59800000 0x2000>;
242	};
243
244	pinctrl: pinctrl@5f801000 {
245	compatible = "socionext,proxstream2-pinctrl", "syscon";
246	reg = <0x5f801000 0xe00>;
247	};
248
249	timer@60000200 {
250	compatible = "arm,cortex-a9-global-timer";
251	reg = <0x60000200 0x20>;
252	interrupts = <1 11 0x304>;
253	clocks = <&arm_timer_clk>;
254	};
255
256	timer@60000600 {
257	compatible = "arm,cortex-a9-twd-timer";
258	reg = <0x60000600 0x20>;
259	interrupts = <1 13 0x304>;
260	clocks = <&arm_timer_clk>;
261	};
262
263	intc: interrupt-controller@60001000 {
264	compatible = "arm,cortex-a9-gic";
265	#interrupt-cells = <3>;
266	interrupt-controller;
267	reg = <0x60001000 0x1000>,
268	<0x60000100 0x100>;
269	};
270	};
271	};
272
273	/include/ "uniphier-pinctrl.dtsi"