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34dcedfb CK |
1 | /* |
2 | * SAMSUNG EXYNOS5420 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. | |
8 | * EXYNOS5420 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
c9cf996d | 16 | #include "exynos54xx.dtsi" |
1dd4e599 | 17 | #include <dt-bindings/clock/exynos5420.h> |
602408e3 | 18 | #include <dt-bindings/clock/exynos-audss-clk.h> |
e5995e6d | 19 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
35e82775 | 20 | |
34dcedfb | 21 | / { |
8bdb31b4 | 22 | compatible = "samsung,exynos5420", "samsung,exynos5"; |
34dcedfb | 23 | |
d81c6cbe | 24 | aliases { |
0e2c5915 YK |
25 | mshc0 = &mmc_0; |
26 | mshc1 = &mmc_1; | |
27 | mshc2 = &mmc_2; | |
d81c6cbe LKA |
28 | pinctrl0 = &pinctrl_0; |
29 | pinctrl1 = &pinctrl_1; | |
30 | pinctrl2 = &pinctrl_2; | |
31 | pinctrl3 = &pinctrl_3; | |
32 | pinctrl4 = &pinctrl_4; | |
1a9110d6 SK |
33 | i2c8 = &hsi2c_8; |
34 | i2c9 = &hsi2c_9; | |
35 | i2c10 = &hsi2c_10; | |
01eb4636 LKA |
36 | gsc0 = &gsc_0; |
37 | gsc1 = &gsc_1; | |
e84a2d91 LKA |
38 | spi0 = &spi_0; |
39 | spi1 = &spi_1; | |
40 | spi2 = &spi_2; | |
66a4a1fb TA |
41 | }; |
42 | ||
4f0d20ec KK |
43 | /* |
44 | * The 'cpus' node is not present here but instead it is provided | |
45 | * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. | |
46 | */ | |
5b56642b | 47 | |
5d99cc59 KK |
48 | soc: soc { |
49 | cluster_a15_opp_table: opp_table0 { | |
50 | compatible = "operating-points-v2"; | |
51 | opp-shared; | |
6a611d14 | 52 | opp-1800000000 { |
5d99cc59 KK |
53 | opp-hz = /bits/ 64 <1800000000>; |
54 | opp-microvolt = <1250000>; | |
55 | clock-latency-ns = <140000>; | |
56 | }; | |
6a611d14 | 57 | opp-1700000000 { |
5d99cc59 KK |
58 | opp-hz = /bits/ 64 <1700000000>; |
59 | opp-microvolt = <1212500>; | |
60 | clock-latency-ns = <140000>; | |
61 | }; | |
6a611d14 | 62 | opp-1600000000 { |
5d99cc59 KK |
63 | opp-hz = /bits/ 64 <1600000000>; |
64 | opp-microvolt = <1175000>; | |
65 | clock-latency-ns = <140000>; | |
66 | }; | |
6a611d14 | 67 | opp-1500000000 { |
5d99cc59 KK |
68 | opp-hz = /bits/ 64 <1500000000>; |
69 | opp-microvolt = <1137500>; | |
70 | clock-latency-ns = <140000>; | |
71 | }; | |
6a611d14 | 72 | opp-1400000000 { |
5d99cc59 KK |
73 | opp-hz = /bits/ 64 <1400000000>; |
74 | opp-microvolt = <1112500>; | |
75 | clock-latency-ns = <140000>; | |
76 | }; | |
6a611d14 | 77 | opp-1300000000 { |
5d99cc59 KK |
78 | opp-hz = /bits/ 64 <1300000000>; |
79 | opp-microvolt = <1062500>; | |
80 | clock-latency-ns = <140000>; | |
81 | }; | |
6a611d14 | 82 | opp-1200000000 { |
5d99cc59 KK |
83 | opp-hz = /bits/ 64 <1200000000>; |
84 | opp-microvolt = <1037500>; | |
85 | clock-latency-ns = <140000>; | |
86 | }; | |
6a611d14 | 87 | opp-1100000000 { |
5d99cc59 KK |
88 | opp-hz = /bits/ 64 <1100000000>; |
89 | opp-microvolt = <1012500>; | |
90 | clock-latency-ns = <140000>; | |
91 | }; | |
6a611d14 | 92 | opp-1000000000 { |
5d99cc59 KK |
93 | opp-hz = /bits/ 64 <1000000000>; |
94 | opp-microvolt = < 987500>; | |
95 | clock-latency-ns = <140000>; | |
96 | }; | |
6a611d14 | 97 | opp-900000000 { |
5d99cc59 KK |
98 | opp-hz = /bits/ 64 <900000000>; |
99 | opp-microvolt = < 962500>; | |
100 | clock-latency-ns = <140000>; | |
101 | }; | |
6a611d14 | 102 | opp-800000000 { |
5d99cc59 KK |
103 | opp-hz = /bits/ 64 <800000000>; |
104 | opp-microvolt = < 937500>; | |
105 | clock-latency-ns = <140000>; | |
106 | }; | |
6a611d14 | 107 | opp-700000000 { |
5d99cc59 KK |
108 | opp-hz = /bits/ 64 <700000000>; |
109 | opp-microvolt = < 912500>; | |
110 | clock-latency-ns = <140000>; | |
111 | }; | |
112 | }; | |
113 | ||
114 | cluster_a7_opp_table: opp_table1 { | |
115 | compatible = "operating-points-v2"; | |
116 | opp-shared; | |
6a611d14 | 117 | opp-1300000000 { |
5d99cc59 KK |
118 | opp-hz = /bits/ 64 <1300000000>; |
119 | opp-microvolt = <1275000>; | |
120 | clock-latency-ns = <140000>; | |
121 | }; | |
6a611d14 | 122 | opp-1200000000 { |
5d99cc59 KK |
123 | opp-hz = /bits/ 64 <1200000000>; |
124 | opp-microvolt = <1212500>; | |
125 | clock-latency-ns = <140000>; | |
126 | }; | |
6a611d14 | 127 | opp-1100000000 { |
5d99cc59 KK |
128 | opp-hz = /bits/ 64 <1100000000>; |
129 | opp-microvolt = <1162500>; | |
130 | clock-latency-ns = <140000>; | |
131 | }; | |
6a611d14 | 132 | opp-1000000000 { |
5d99cc59 KK |
133 | opp-hz = /bits/ 64 <1000000000>; |
134 | opp-microvolt = <1112500>; | |
135 | clock-latency-ns = <140000>; | |
136 | }; | |
6a611d14 | 137 | opp-900000000 { |
5d99cc59 KK |
138 | opp-hz = /bits/ 64 <900000000>; |
139 | opp-microvolt = <1062500>; | |
140 | clock-latency-ns = <140000>; | |
141 | }; | |
6a611d14 | 142 | opp-800000000 { |
5d99cc59 KK |
143 | opp-hz = /bits/ 64 <800000000>; |
144 | opp-microvolt = <1025000>; | |
145 | clock-latency-ns = <140000>; | |
146 | }; | |
6a611d14 | 147 | opp-700000000 { |
5d99cc59 KK |
148 | opp-hz = /bits/ 64 <700000000>; |
149 | opp-microvolt = <975000>; | |
150 | clock-latency-ns = <140000>; | |
151 | }; | |
6a611d14 | 152 | opp-600000000 { |
5d99cc59 KK |
153 | opp-hz = /bits/ 64 <600000000>; |
154 | opp-microvolt = <937500>; | |
155 | clock-latency-ns = <140000>; | |
156 | }; | |
157 | }; | |
158 | ||
159 | cci: cci@10d20000 { | |
160 | compatible = "arm,cci-400"; | |
161 | #address-cells = <1>; | |
162 | #size-cells = <1>; | |
163 | reg = <0x10d20000 0x1000>; | |
164 | ranges = <0x0 0x10d20000 0x6000>; | |
165 | ||
166 | cci_control0: slave-if@4000 { | |
167 | compatible = "arm,cci-400-ctrl-if"; | |
168 | interface-type = "ace"; | |
169 | reg = <0x4000 0x1000>; | |
170 | }; | |
171 | cci_control1: slave-if@5000 { | |
172 | compatible = "arm,cci-400-ctrl-if"; | |
173 | interface-type = "ace"; | |
174 | reg = <0x5000 0x1000>; | |
175 | }; | |
176 | }; | |
177 | ||
5d99cc59 KK |
178 | clock: clock-controller@10010000 { |
179 | compatible = "samsung,exynos5420-clock"; | |
180 | reg = <0x10010000 0x30000>; | |
181 | #clock-cells = <1>; | |
182 | }; | |
183 | ||
184 | clock_audss: audss-clock-controller@3810000 { | |
185 | compatible = "samsung,exynos5420-audss-clock"; | |
186 | reg = <0x03810000 0x0C>; | |
187 | #clock-cells = <1>; | |
188 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, | |
189 | <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; | |
190 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; | |
191 | }; | |
192 | ||
193 | mfc: codec@11000000 { | |
194 | compatible = "samsung,mfc-v7"; | |
195 | reg = <0x11000000 0x10000>; | |
c92a4fb2 | 196 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
197 | clocks = <&clock CLK_MFC>; |
198 | clock-names = "mfc"; | |
199 | power-domains = <&mfc_pd>; | |
200 | iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; | |
201 | iommu-names = "left", "right"; | |
202 | }; | |
203 | ||
204 | mmc_0: mmc@12200000 { | |
205 | compatible = "samsung,exynos5420-dw-mshc-smu"; | |
c92a4fb2 | 206 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
207 | #address-cells = <1>; |
208 | #size-cells = <0>; | |
209 | reg = <0x12200000 0x2000>; | |
210 | clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; | |
211 | clock-names = "biu", "ciu"; | |
212 | fifo-depth = <0x40>; | |
213 | status = "disabled"; | |
1c0e0854 | 214 | }; |
b3205dea | 215 | |
5d99cc59 KK |
216 | mmc_1: mmc@12210000 { |
217 | compatible = "samsung,exynos5420-dw-mshc-smu"; | |
c92a4fb2 | 218 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
219 | #address-cells = <1>; |
220 | #size-cells = <0>; | |
221 | reg = <0x12210000 0x2000>; | |
222 | clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; | |
223 | clock-names = "biu", "ciu"; | |
224 | fifo-depth = <0x40>; | |
225 | status = "disabled"; | |
b3205dea SK |
226 | }; |
227 | ||
5d99cc59 KK |
228 | mmc_2: mmc@12220000 { |
229 | compatible = "samsung,exynos5420-dw-mshc"; | |
c92a4fb2 | 230 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
231 | #address-cells = <1>; |
232 | #size-cells = <0>; | |
233 | reg = <0x12220000 0x1000>; | |
234 | clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; | |
235 | clock-names = "biu", "ciu"; | |
236 | fifo-depth = <0x40>; | |
237 | status = "disabled"; | |
1c0e0854 | 238 | }; |
34dcedfb | 239 | |
5d99cc59 KK |
240 | nocp_mem0_0: nocp@10CA1000 { |
241 | compatible = "samsung,exynos5420-nocp"; | |
242 | reg = <0x10CA1000 0x200>; | |
243 | status = "disabled"; | |
34dcedfb | 244 | }; |
f09d062f | 245 | |
5d99cc59 KK |
246 | nocp_mem0_1: nocp@10CA1400 { |
247 | compatible = "samsung,exynos5420-nocp"; | |
248 | reg = <0x10CA1400 0x200>; | |
249 | status = "disabled"; | |
d81c6cbe | 250 | }; |
0e2c5915 | 251 | |
5d99cc59 KK |
252 | nocp_mem1_0: nocp@10CA1800 { |
253 | compatible = "samsung,exynos5420-nocp"; | |
254 | reg = <0x10CA1800 0x200>; | |
e6015c1f | 255 | status = "disabled"; |
e3188533 | 256 | }; |
0e2c5915 | 257 | |
5d99cc59 KK |
258 | nocp_mem1_1: nocp@10CA1C00 { |
259 | compatible = "samsung,exynos5420-nocp"; | |
260 | reg = <0x10CA1C00 0x200>; | |
261 | status = "disabled"; | |
9843a223 | 262 | }; |
0e2c5915 | 263 | |
5d99cc59 KK |
264 | nocp_g3d_0: nocp@11A51000 { |
265 | compatible = "samsung,exynos5420-nocp"; | |
266 | reg = <0x11A51000 0x200>; | |
267 | status = "disabled"; | |
34dcedfb | 268 | }; |
34dcedfb | 269 | |
5d99cc59 KK |
270 | nocp_g3d_1: nocp@11A51400 { |
271 | compatible = "samsung,exynos5420-nocp"; | |
272 | reg = <0x11A51400 0x200>; | |
273 | status = "disabled"; | |
f070267b | 274 | }; |
f018c987 | 275 | |
5d99cc59 KK |
276 | gsc_pd: power-domain@10044000 { |
277 | compatible = "samsung,exynos4210-pd"; | |
278 | reg = <0x10044000 0x20>; | |
279 | #power-domain-cells = <0>; | |
55d74adf | 280 | label = "GSC"; |
5d99cc59 KK |
281 | clocks = <&clock CLK_FIN_PLL>, |
282 | <&clock CLK_MOUT_USER_ACLK300_GSCL>, | |
283 | <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; | |
284 | clock-names = "oscclk", "clk0", "asb0", "asb1"; | |
6674fd92 | 285 | }; |
f018c987 | 286 | |
5d99cc59 KK |
287 | isp_pd: power-domain@10044020 { |
288 | compatible = "samsung,exynos4210-pd"; | |
289 | reg = <0x10044020 0x20>; | |
290 | #power-domain-cells = <0>; | |
55d74adf | 291 | label = "ISP"; |
6674fd92 | 292 | }; |
f018c987 | 293 | |
5d99cc59 KK |
294 | mfc_pd: power-domain@10044060 { |
295 | compatible = "samsung,exynos4210-pd"; | |
296 | reg = <0x10044060 0x20>; | |
95eb940c OJ |
297 | clocks = <&clock CLK_FIN_PLL>, |
298 | <&clock CLK_MOUT_USER_ACLK333>, | |
299 | <&clock CLK_ACLK333>; | |
300 | clock-names = "oscclk", "clk0","asb0"; | |
5d99cc59 | 301 | #power-domain-cells = <0>; |
55d74adf | 302 | label = "MFC"; |
b04a62d3 | 303 | }; |
f018c987 | 304 | |
5d99cc59 KK |
305 | msc_pd: power-domain@10044120 { |
306 | compatible = "samsung,exynos4210-pd"; | |
307 | reg = <0x10044120 0x20>; | |
308 | #power-domain-cells = <0>; | |
55d74adf | 309 | label = "MSC"; |
b04a62d3 | 310 | }; |
f018c987 | 311 | |
5d99cc59 KK |
312 | disp_pd: power-domain@100440C0 { |
313 | compatible = "samsung,exynos4210-pd"; | |
314 | reg = <0x100440C0 0x20>; | |
315 | #power-domain-cells = <0>; | |
55d74adf | 316 | label = "DISP"; |
5d99cc59 KK |
317 | clocks = <&clock CLK_FIN_PLL>, |
318 | <&clock CLK_MOUT_USER_ACLK200_DISP1>, | |
319 | <&clock CLK_MOUT_USER_ACLK300_DISP1>, | |
320 | <&clock CLK_MOUT_USER_ACLK400_DISP1>, | |
321 | <&clock CLK_FIMD1>, <&clock CLK_MIXER>; | |
322 | clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; | |
b04a62d3 | 323 | }; |
f018c987 | 324 | |
5d99cc59 KK |
325 | pinctrl_0: pinctrl@13400000 { |
326 | compatible = "samsung,exynos5420-pinctrl"; | |
327 | reg = <0x13400000 0x1000>; | |
c92a4fb2 | 328 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
dcfca2cc | 329 | |
5d99cc59 KK |
330 | wakeup-interrupt-controller { |
331 | compatible = "samsung,exynos4210-wakeup-eint"; | |
332 | interrupt-parent = <&gic>; | |
c92a4fb2 | 333 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 | 334 | }; |
b04a62d3 | 335 | }; |
dcfca2cc | 336 | |
5d99cc59 KK |
337 | pinctrl_1: pinctrl@13410000 { |
338 | compatible = "samsung,exynos5420-pinctrl"; | |
339 | reg = <0x13410000 0x1000>; | |
c92a4fb2 | 340 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
b04a62d3 | 341 | }; |
dcfca2cc | 342 | |
5d99cc59 KK |
343 | pinctrl_2: pinctrl@14000000 { |
344 | compatible = "samsung,exynos5420-pinctrl"; | |
345 | reg = <0x14000000 0x1000>; | |
c92a4fb2 | 346 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
b04a62d3 | 347 | }; |
dcfca2cc | 348 | |
5d99cc59 KK |
349 | pinctrl_3: pinctrl@14010000 { |
350 | compatible = "samsung,exynos5420-pinctrl"; | |
351 | reg = <0x14010000 0x1000>; | |
c92a4fb2 | 352 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
b04a62d3 | 353 | }; |
dcfca2cc | 354 | |
5d99cc59 KK |
355 | pinctrl_4: pinctrl@03860000 { |
356 | compatible = "samsung,exynos5420-pinctrl"; | |
357 | reg = <0x03860000 0x1000>; | |
c92a4fb2 | 358 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
b04a62d3 | 359 | }; |
d81c6cbe | 360 | |
5d99cc59 KK |
361 | amba { |
362 | #address-cells = <1>; | |
363 | #size-cells = <1>; | |
364 | compatible = "simple-bus"; | |
d81c6cbe | 365 | interrupt-parent = <&gic>; |
5d99cc59 KK |
366 | ranges; |
367 | ||
368 | adma: adma@03880000 { | |
369 | compatible = "arm,pl330", "arm,primecell"; | |
370 | reg = <0x03880000 0x1000>; | |
c92a4fb2 | 371 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
372 | clocks = <&clock_audss EXYNOS_ADMA>; |
373 | clock-names = "apb_pclk"; | |
374 | #dma-cells = <1>; | |
375 | #dma-channels = <6>; | |
376 | #dma-requests = <16>; | |
377 | }; | |
378 | ||
379 | pdma0: pdma@121A0000 { | |
380 | compatible = "arm,pl330", "arm,primecell"; | |
381 | reg = <0x121A0000 0x1000>; | |
c92a4fb2 | 382 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
383 | clocks = <&clock CLK_PDMA0>; |
384 | clock-names = "apb_pclk"; | |
385 | #dma-cells = <1>; | |
386 | #dma-channels = <8>; | |
387 | #dma-requests = <32>; | |
388 | }; | |
389 | ||
390 | pdma1: pdma@121B0000 { | |
391 | compatible = "arm,pl330", "arm,primecell"; | |
392 | reg = <0x121B0000 0x1000>; | |
c92a4fb2 | 393 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
394 | clocks = <&clock CLK_PDMA1>; |
395 | clock-names = "apb_pclk"; | |
396 | #dma-cells = <1>; | |
397 | #dma-channels = <8>; | |
398 | #dma-requests = <32>; | |
399 | }; | |
400 | ||
401 | mdma0: mdma@10800000 { | |
402 | compatible = "arm,pl330", "arm,primecell"; | |
403 | reg = <0x10800000 0x1000>; | |
c92a4fb2 | 404 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
405 | clocks = <&clock CLK_MDMA0>; |
406 | clock-names = "apb_pclk"; | |
407 | #dma-cells = <1>; | |
408 | #dma-channels = <8>; | |
409 | #dma-requests = <1>; | |
410 | }; | |
411 | ||
412 | mdma1: mdma@11C10000 { | |
413 | compatible = "arm,pl330", "arm,primecell"; | |
414 | reg = <0x11C10000 0x1000>; | |
c92a4fb2 | 415 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
416 | clocks = <&clock CLK_MDMA1>; |
417 | clock-names = "apb_pclk"; | |
418 | #dma-cells = <1>; | |
419 | #dma-channels = <8>; | |
420 | #dma-requests = <1>; | |
421 | /* | |
422 | * MDMA1 can support both secure and non-secure | |
423 | * AXI transactions. When this is enabled in | |
424 | * the kernel for boards that run in secure | |
425 | * mode, we are getting imprecise external | |
426 | * aborts causing the kernel to oops. | |
427 | */ | |
428 | status = "disabled"; | |
429 | }; | |
430 | }; | |
431 | ||
432 | i2s0: i2s@03830000 { | |
433 | compatible = "samsung,exynos5420-i2s"; | |
434 | reg = <0x03830000 0x100>; | |
435 | dmas = <&adma 0 | |
436 | &adma 2 | |
437 | &adma 1>; | |
438 | dma-names = "tx", "rx", "tx-sec"; | |
439 | clocks = <&clock_audss EXYNOS_I2S_BUS>, | |
440 | <&clock_audss EXYNOS_I2S_BUS>, | |
441 | <&clock_audss EXYNOS_SCLK_I2S>; | |
442 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
443 | #clock-cells = <1>; | |
444 | clock-output-names = "i2s_cdclk0"; | |
445 | #sound-dai-cells = <1>; | |
446 | samsung,idma-addr = <0x03000000>; | |
447 | pinctrl-names = "default"; | |
448 | pinctrl-0 = <&i2s0_bus>; | |
449 | status = "disabled"; | |
d81c6cbe | 450 | }; |
d81c6cbe | 451 | |
5d99cc59 KK |
452 | i2s1: i2s@12D60000 { |
453 | compatible = "samsung,exynos5420-i2s"; | |
454 | reg = <0x12D60000 0x100>; | |
455 | dmas = <&pdma1 12 | |
456 | &pdma1 11>; | |
457 | dma-names = "tx", "rx"; | |
458 | clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; | |
459 | clock-names = "iis", "i2s_opclk0"; | |
460 | #clock-cells = <1>; | |
461 | clock-output-names = "i2s_cdclk1"; | |
462 | #sound-dai-cells = <1>; | |
463 | pinctrl-names = "default"; | |
464 | pinctrl-0 = <&i2s1_bus>; | |
e6015c1f | 465 | status = "disabled"; |
e3188533 | 466 | }; |
b0e505ce | 467 | |
5d99cc59 KK |
468 | i2s2: i2s@12D70000 { |
469 | compatible = "samsung,exynos5420-i2s"; | |
470 | reg = <0x12D70000 0x100>; | |
471 | dmas = <&pdma0 12 | |
472 | &pdma0 11>; | |
473 | dma-names = "tx", "rx"; | |
474 | clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; | |
475 | clock-names = "iis", "i2s_opclk0"; | |
476 | #clock-cells = <1>; | |
477 | clock-output-names = "i2s_cdclk2"; | |
478 | #sound-dai-cells = <1>; | |
479 | pinctrl-names = "default"; | |
480 | pinctrl-0 = <&i2s2_bus>; | |
481 | status = "disabled"; | |
9843a223 | 482 | }; |
1d287620 | 483 | |
5d99cc59 KK |
484 | spi_0: spi@12d20000 { |
485 | compatible = "samsung,exynos4210-spi"; | |
486 | reg = <0x12d20000 0x100>; | |
c92a4fb2 | 487 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
488 | dmas = <&pdma0 5 |
489 | &pdma0 4>; | |
490 | dma-names = "tx", "rx"; | |
491 | #address-cells = <1>; | |
492 | #size-cells = <0>; | |
493 | pinctrl-names = "default"; | |
494 | pinctrl-0 = <&spi0_bus>; | |
495 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; | |
496 | clock-names = "spi", "spi_busclk0"; | |
497 | status = "disabled"; | |
f070267b | 498 | }; |
3cb7d1cd | 499 | |
5d99cc59 KK |
500 | spi_1: spi@12d30000 { |
501 | compatible = "samsung,exynos4210-spi"; | |
502 | reg = <0x12d30000 0x100>; | |
c92a4fb2 | 503 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
504 | dmas = <&pdma1 5 |
505 | &pdma1 4>; | |
506 | dma-names = "tx", "rx"; | |
507 | #address-cells = <1>; | |
508 | #size-cells = <0>; | |
509 | pinctrl-names = "default"; | |
510 | pinctrl-0 = <&spi1_bus>; | |
511 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; | |
512 | clock-names = "spi", "spi_busclk0"; | |
513 | status = "disabled"; | |
f070267b | 514 | }; |
6674fd92 | 515 | |
5d99cc59 KK |
516 | spi_2: spi@12d40000 { |
517 | compatible = "samsung,exynos4210-spi"; | |
518 | reg = <0x12d40000 0x100>; | |
c92a4fb2 | 519 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
520 | dmas = <&pdma0 7 |
521 | &pdma0 6>; | |
522 | dma-names = "tx", "rx"; | |
523 | #address-cells = <1>; | |
524 | #size-cells = <0>; | |
525 | pinctrl-names = "default"; | |
526 | pinctrl-0 = <&spi2_bus>; | |
527 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; | |
528 | clock-names = "spi", "spi_busclk0"; | |
529 | status = "disabled"; | |
6674fd92 | 530 | }; |
6674fd92 | 531 | |
5d99cc59 KK |
532 | dp_phy: dp-video-phy { |
533 | compatible = "samsung,exynos5420-dp-video-phy"; | |
534 | samsung,pmu-syscon = <&pmu_system_controller>; | |
535 | #phy-cells = <0>; | |
6674fd92 | 536 | }; |
b7004516 | 537 | |
5d99cc59 KK |
538 | mipi_phy: mipi-video-phy { |
539 | compatible = "samsung,s5pv210-mipi-video-phy"; | |
540 | syscon = <&pmu_system_controller>; | |
541 | #phy-cells = <1>; | |
b04a62d3 | 542 | }; |
b04a62d3 | 543 | |
5d99cc59 KK |
544 | dsi@14500000 { |
545 | compatible = "samsung,exynos5410-mipi-dsi"; | |
546 | reg = <0x14500000 0x10000>; | |
c92a4fb2 | 547 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
548 | phys = <&mipi_phy 1>; |
549 | phy-names = "dsim"; | |
550 | clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; | |
551 | clock-names = "bus_clk", "pll_clk"; | |
552 | #address-cells = <1>; | |
553 | #size-cells = <0>; | |
554 | status = "disabled"; | |
b04a62d3 | 555 | }; |
b04a62d3 | 556 | |
5d99cc59 KK |
557 | adc: adc@12D10000 { |
558 | compatible = "samsung,exynos-adc-v2"; | |
559 | reg = <0x12D10000 0x100>; | |
c92a4fb2 | 560 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
561 | clocks = <&clock CLK_TSADC>; |
562 | clock-names = "adc"; | |
563 | #io-channel-cells = <1>; | |
564 | io-channel-ranges; | |
565 | samsung,syscon-phandle = <&pmu_system_controller>; | |
566 | status = "disabled"; | |
b04a62d3 | 567 | }; |
b04a62d3 | 568 | |
5d99cc59 KK |
569 | hsi2c_8: i2c@12E00000 { |
570 | compatible = "samsung,exynos5250-hsi2c"; | |
571 | reg = <0x12E00000 0x1000>; | |
c92a4fb2 | 572 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
573 | #address-cells = <1>; |
574 | #size-cells = <0>; | |
575 | pinctrl-names = "default"; | |
576 | pinctrl-0 = <&i2c8_hs_bus>; | |
577 | clocks = <&clock CLK_USI4>; | |
578 | clock-names = "hsi2c"; | |
579 | status = "disabled"; | |
b04a62d3 | 580 | }; |
b04a62d3 | 581 | |
5d99cc59 KK |
582 | hsi2c_9: i2c@12E10000 { |
583 | compatible = "samsung,exynos5250-hsi2c"; | |
584 | reg = <0x12E10000 0x1000>; | |
c92a4fb2 | 585 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
586 | #address-cells = <1>; |
587 | #size-cells = <0>; | |
588 | pinctrl-names = "default"; | |
589 | pinctrl-0 = <&i2c9_hs_bus>; | |
590 | clocks = <&clock CLK_USI5>; | |
591 | clock-names = "hsi2c"; | |
592 | status = "disabled"; | |
b04a62d3 | 593 | }; |
b04a62d3 | 594 | |
5d99cc59 KK |
595 | hsi2c_10: i2c@12E20000 { |
596 | compatible = "samsung,exynos5250-hsi2c"; | |
597 | reg = <0x12E20000 0x1000>; | |
c92a4fb2 | 598 | interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
599 | #address-cells = <1>; |
600 | #size-cells = <0>; | |
601 | pinctrl-names = "default"; | |
602 | pinctrl-0 = <&i2c10_hs_bus>; | |
603 | clocks = <&clock CLK_USI6>; | |
604 | clock-names = "hsi2c"; | |
605 | status = "disabled"; | |
b04a62d3 | 606 | }; |
b04a62d3 | 607 | |
5d99cc59 KK |
608 | hdmi: hdmi@14530000 { |
609 | compatible = "samsung,exynos5420-hdmi"; | |
610 | reg = <0x14530000 0x70000>; | |
c92a4fb2 | 611 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
612 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
613 | <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
614 | <&clock CLK_MOUT_HDMI>; | |
615 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", | |
616 | "sclk_hdmiphy", "mout_hdmi"; | |
617 | phy = <&hdmiphy>; | |
618 | samsung,syscon-phandle = <&pmu_system_controller>; | |
619 | status = "disabled"; | |
620 | power-domains = <&disp_pd>; | |
621 | }; | |
622 | ||
623 | hdmiphy: hdmiphy@145D0000 { | |
624 | reg = <0x145D0000 0x20>; | |
625 | }; | |
626 | ||
5343b157 MS |
627 | hdmicec: cec@101B0000 { |
628 | compatible = "samsung,s5p-cec"; | |
629 | reg = <0x101B0000 0x200>; | |
630 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
631 | clocks = <&clock CLK_HDMI_CEC>; | |
632 | clock-names = "hdmicec"; | |
633 | samsung,syscon-phandle = <&pmu_system_controller>; | |
634 | hdmi-phandle = <&hdmi>; | |
635 | pinctrl-names = "default"; | |
636 | pinctrl-0 = <&hdmi_cec>; | |
637 | status = "disabled"; | |
638 | }; | |
639 | ||
5d99cc59 KK |
640 | mixer: mixer@14450000 { |
641 | compatible = "samsung,exynos5420-mixer"; | |
642 | reg = <0x14450000 0x10000>; | |
c92a4fb2 | 643 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
644 | clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, |
645 | <&clock CLK_SCLK_HDMI>; | |
646 | clock-names = "mixer", "hdmi", "sclk_hdmi"; | |
647 | power-domains = <&disp_pd>; | |
648 | iommus = <&sysmmu_tv>; | |
649 | }; | |
650 | ||
651 | rotator: rotator@11C00000 { | |
652 | compatible = "samsung,exynos5250-rotator"; | |
653 | reg = <0x11C00000 0x64>; | |
c92a4fb2 | 654 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
655 | clocks = <&clock CLK_ROTATOR>; |
656 | clock-names = "rotator"; | |
657 | iommus = <&sysmmu_rotator>; | |
658 | }; | |
659 | ||
660 | gsc_0: video-scaler@13e00000 { | |
661 | compatible = "samsung,exynos5-gsc"; | |
662 | reg = <0x13e00000 0x1000>; | |
c92a4fb2 | 663 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
664 | clocks = <&clock CLK_GSCL0>; |
665 | clock-names = "gscl"; | |
666 | power-domains = <&gsc_pd>; | |
667 | iommus = <&sysmmu_gscl0>; | |
668 | }; | |
669 | ||
670 | gsc_1: video-scaler@13e10000 { | |
671 | compatible = "samsung,exynos5-gsc"; | |
672 | reg = <0x13e10000 0x1000>; | |
c92a4fb2 | 673 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
674 | clocks = <&clock CLK_GSCL1>; |
675 | clock-names = "gscl"; | |
676 | power-domains = <&gsc_pd>; | |
677 | iommus = <&sysmmu_gscl1>; | |
678 | }; | |
679 | ||
680 | jpeg_0: jpeg@11F50000 { | |
681 | compatible = "samsung,exynos5420-jpeg"; | |
682 | reg = <0x11F50000 0x1000>; | |
c92a4fb2 | 683 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
684 | clock-names = "jpeg"; |
685 | clocks = <&clock CLK_JPEG>; | |
686 | iommus = <&sysmmu_jpeg0>; | |
687 | }; | |
688 | ||
689 | jpeg_1: jpeg@11F60000 { | |
690 | compatible = "samsung,exynos5420-jpeg"; | |
691 | reg = <0x11F60000 0x1000>; | |
c92a4fb2 | 692 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
693 | clock-names = "jpeg"; |
694 | clocks = <&clock CLK_JPEG2>; | |
695 | iommus = <&sysmmu_jpeg1>; | |
696 | }; | |
697 | ||
698 | pmu_system_controller: system-controller@10040000 { | |
699 | compatible = "samsung,exynos5420-pmu", "syscon"; | |
700 | reg = <0x10040000 0x5000>; | |
701 | clock-names = "clkout16"; | |
702 | clocks = <&clock CLK_FIN_PLL>; | |
703 | #clock-cells = <1>; | |
704 | interrupt-controller; | |
705 | #interrupt-cells = <3>; | |
706 | interrupt-parent = <&gic>; | |
b04a62d3 | 707 | }; |
b04a62d3 | 708 | |
5d99cc59 KK |
709 | tmu_cpu0: tmu@10060000 { |
710 | compatible = "samsung,exynos5420-tmu"; | |
711 | reg = <0x10060000 0x100>; | |
c92a4fb2 | 712 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
713 | clocks = <&clock CLK_TMU>; |
714 | clock-names = "tmu_apbif"; | |
28928a3c | 715 | #include "exynos5420-tmu-sensor-conf.dtsi" |
5d99cc59 KK |
716 | }; |
717 | ||
718 | tmu_cpu1: tmu@10064000 { | |
719 | compatible = "samsung,exynos5420-tmu"; | |
720 | reg = <0x10064000 0x100>; | |
c92a4fb2 | 721 | interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
722 | clocks = <&clock CLK_TMU>; |
723 | clock-names = "tmu_apbif"; | |
28928a3c | 724 | #include "exynos5420-tmu-sensor-conf.dtsi" |
5d99cc59 KK |
725 | }; |
726 | ||
727 | tmu_cpu2: tmu@10068000 { | |
728 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | |
729 | reg = <0x10068000 0x100>, <0x1006c000 0x4>; | |
c92a4fb2 | 730 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
731 | clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; |
732 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; | |
28928a3c | 733 | #include "exynos5420-tmu-sensor-conf.dtsi" |
5d99cc59 KK |
734 | }; |
735 | ||
736 | tmu_cpu3: tmu@1006c000 { | |
737 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | |
738 | reg = <0x1006c000 0x100>, <0x100a0000 0x4>; | |
c92a4fb2 | 739 | interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
740 | clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; |
741 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; | |
28928a3c | 742 | #include "exynos5420-tmu-sensor-conf.dtsi" |
5d99cc59 KK |
743 | }; |
744 | ||
745 | tmu_gpu: tmu@100a0000 { | |
746 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | |
747 | reg = <0x100a0000 0x100>, <0x10068000 0x4>; | |
c92a4fb2 | 748 | interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
749 | clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; |
750 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; | |
28928a3c | 751 | #include "exynos5420-tmu-sensor-conf.dtsi" |
5d99cc59 KK |
752 | }; |
753 | ||
5d99cc59 KK |
754 | sysmmu_g2dr: sysmmu@0x10A60000 { |
755 | compatible = "samsung,exynos-sysmmu"; | |
756 | reg = <0x10A60000 0x1000>; | |
757 | interrupt-parent = <&combiner>; | |
758 | interrupts = <24 5>; | |
759 | clock-names = "sysmmu", "master"; | |
760 | clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; | |
761 | #iommu-cells = <0>; | |
762 | }; | |
763 | ||
764 | sysmmu_g2dw: sysmmu@0x10A70000 { | |
765 | compatible = "samsung,exynos-sysmmu"; | |
766 | reg = <0x10A70000 0x1000>; | |
767 | interrupt-parent = <&combiner>; | |
768 | interrupts = <22 2>; | |
769 | clock-names = "sysmmu", "master"; | |
770 | clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; | |
771 | #iommu-cells = <0>; | |
772 | }; | |
773 | ||
774 | sysmmu_tv: sysmmu@0x14650000 { | |
775 | compatible = "samsung,exynos-sysmmu"; | |
776 | reg = <0x14650000 0x1000>; | |
777 | interrupt-parent = <&combiner>; | |
778 | interrupts = <7 4>; | |
779 | clock-names = "sysmmu", "master"; | |
780 | clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; | |
781 | power-domains = <&disp_pd>; | |
782 | #iommu-cells = <0>; | |
783 | }; | |
784 | ||
785 | sysmmu_gscl0: sysmmu@0x13E80000 { | |
786 | compatible = "samsung,exynos-sysmmu"; | |
787 | reg = <0x13E80000 0x1000>; | |
788 | interrupt-parent = <&combiner>; | |
789 | interrupts = <2 0>; | |
790 | clock-names = "sysmmu", "master"; | |
791 | clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; | |
792 | power-domains = <&gsc_pd>; | |
793 | #iommu-cells = <0>; | |
794 | }; | |
795 | ||
796 | sysmmu_gscl1: sysmmu@0x13E90000 { | |
797 | compatible = "samsung,exynos-sysmmu"; | |
798 | reg = <0x13E90000 0x1000>; | |
799 | interrupt-parent = <&combiner>; | |
800 | interrupts = <2 2>; | |
801 | clock-names = "sysmmu", "master"; | |
802 | clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; | |
803 | power-domains = <&gsc_pd>; | |
804 | #iommu-cells = <0>; | |
805 | }; | |
806 | ||
807 | sysmmu_scaler0r: sysmmu@0x12880000 { | |
808 | compatible = "samsung,exynos-sysmmu"; | |
809 | reg = <0x12880000 0x1000>; | |
810 | interrupt-parent = <&combiner>; | |
811 | interrupts = <22 4>; | |
812 | clock-names = "sysmmu", "master"; | |
813 | clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; | |
814 | #iommu-cells = <0>; | |
815 | }; | |
816 | ||
817 | sysmmu_scaler1r: sysmmu@0x12890000 { | |
818 | compatible = "samsung,exynos-sysmmu"; | |
819 | reg = <0x12890000 0x1000>; | |
c92a4fb2 | 820 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
821 | clock-names = "sysmmu", "master"; |
822 | clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; | |
823 | #iommu-cells = <0>; | |
824 | }; | |
825 | ||
826 | sysmmu_scaler2r: sysmmu@0x128A0000 { | |
827 | compatible = "samsung,exynos-sysmmu"; | |
828 | reg = <0x128A0000 0x1000>; | |
c92a4fb2 | 829 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
830 | clock-names = "sysmmu", "master"; |
831 | clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; | |
832 | #iommu-cells = <0>; | |
833 | }; | |
834 | ||
835 | sysmmu_scaler0w: sysmmu@0x128C0000 { | |
836 | compatible = "samsung,exynos-sysmmu"; | |
837 | reg = <0x128C0000 0x1000>; | |
838 | interrupt-parent = <&combiner>; | |
839 | interrupts = <27 2>; | |
840 | clock-names = "sysmmu", "master"; | |
841 | clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; | |
842 | #iommu-cells = <0>; | |
843 | }; | |
844 | ||
845 | sysmmu_scaler1w: sysmmu@0x128D0000 { | |
846 | compatible = "samsung,exynos-sysmmu"; | |
847 | reg = <0x128D0000 0x1000>; | |
848 | interrupt-parent = <&combiner>; | |
849 | interrupts = <22 6>; | |
850 | clock-names = "sysmmu", "master"; | |
851 | clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; | |
852 | #iommu-cells = <0>; | |
853 | }; | |
854 | ||
855 | sysmmu_scaler2w: sysmmu@0x128E0000 { | |
856 | compatible = "samsung,exynos-sysmmu"; | |
857 | reg = <0x128E0000 0x1000>; | |
858 | interrupt-parent = <&combiner>; | |
859 | interrupts = <19 6>; | |
860 | clock-names = "sysmmu", "master"; | |
861 | clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; | |
862 | #iommu-cells = <0>; | |
863 | }; | |
864 | ||
865 | sysmmu_rotator: sysmmu@0x11D40000 { | |
866 | compatible = "samsung,exynos-sysmmu"; | |
867 | reg = <0x11D40000 0x1000>; | |
868 | interrupt-parent = <&combiner>; | |
869 | interrupts = <4 0>; | |
870 | clock-names = "sysmmu", "master"; | |
871 | clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; | |
872 | #iommu-cells = <0>; | |
873 | }; | |
874 | ||
875 | sysmmu_jpeg0: sysmmu@0x11F10000 { | |
876 | compatible = "samsung,exynos-sysmmu"; | |
877 | reg = <0x11F10000 0x1000>; | |
878 | interrupt-parent = <&combiner>; | |
879 | interrupts = <4 2>; | |
880 | clock-names = "sysmmu", "master"; | |
881 | clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; | |
882 | #iommu-cells = <0>; | |
883 | }; | |
884 | ||
885 | sysmmu_jpeg1: sysmmu@0x11F20000 { | |
886 | compatible = "samsung,exynos-sysmmu"; | |
887 | reg = <0x11F20000 0x1000>; | |
c92a4fb2 | 888 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
5d99cc59 KK |
889 | clock-names = "sysmmu", "master"; |
890 | clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; | |
891 | #iommu-cells = <0>; | |
892 | }; | |
893 | ||
894 | sysmmu_mfc_l: sysmmu@0x11200000 { | |
895 | compatible = "samsung,exynos-sysmmu"; | |
896 | reg = <0x11200000 0x1000>; | |
897 | interrupt-parent = <&combiner>; | |
898 | interrupts = <6 2>; | |
899 | clock-names = "sysmmu", "master"; | |
900 | clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; | |
901 | power-domains = <&mfc_pd>; | |
902 | #iommu-cells = <0>; | |
903 | }; | |
904 | ||
905 | sysmmu_mfc_r: sysmmu@0x11210000 { | |
906 | compatible = "samsung,exynos-sysmmu"; | |
907 | reg = <0x11210000 0x1000>; | |
908 | interrupt-parent = <&combiner>; | |
909 | interrupts = <8 5>; | |
910 | clock-names = "sysmmu", "master"; | |
911 | clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; | |
912 | power-domains = <&mfc_pd>; | |
913 | #iommu-cells = <0>; | |
914 | }; | |
915 | ||
916 | sysmmu_fimd1_0: sysmmu@0x14640000 { | |
917 | compatible = "samsung,exynos-sysmmu"; | |
918 | reg = <0x14640000 0x1000>; | |
919 | interrupt-parent = <&combiner>; | |
920 | interrupts = <3 2>; | |
921 | clock-names = "sysmmu", "master"; | |
922 | clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; | |
923 | power-domains = <&disp_pd>; | |
924 | #iommu-cells = <0>; | |
925 | }; | |
926 | ||
927 | sysmmu_fimd1_1: sysmmu@0x14680000 { | |
928 | compatible = "samsung,exynos-sysmmu"; | |
929 | reg = <0x14680000 0x1000>; | |
930 | interrupt-parent = <&combiner>; | |
931 | interrupts = <3 0>; | |
932 | clock-names = "sysmmu", "master"; | |
933 | clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; | |
934 | power-domains = <&disp_pd>; | |
935 | #iommu-cells = <0>; | |
936 | }; | |
937 | ||
938 | bus_wcore: bus_wcore { | |
939 | compatible = "samsung,exynos-bus"; | |
940 | clocks = <&clock CLK_DOUT_ACLK400_WCORE>; | |
941 | clock-names = "bus"; | |
942 | operating-points-v2 = <&bus_wcore_opp_table>; | |
943 | status = "disabled"; | |
b04a62d3 | 944 | }; |
b04a62d3 | 945 | |
5d99cc59 KK |
946 | bus_noc: bus_noc { |
947 | compatible = "samsung,exynos-bus"; | |
948 | clocks = <&clock CLK_DOUT_ACLK100_NOC>; | |
949 | clock-names = "bus"; | |
950 | operating-points-v2 = <&bus_noc_opp_table>; | |
951 | status = "disabled"; | |
b04a62d3 | 952 | }; |
b04a62d3 | 953 | |
5d99cc59 KK |
954 | bus_fsys_apb: bus_fsys_apb { |
955 | compatible = "samsung,exynos-bus"; | |
956 | clocks = <&clock CLK_DOUT_PCLK200_FSYS>; | |
957 | clock-names = "bus"; | |
958 | operating-points-v2 = <&bus_fsys_apb_opp_table>; | |
959 | status = "disabled"; | |
b04a62d3 | 960 | }; |
b04a62d3 | 961 | |
5d99cc59 KK |
962 | bus_fsys: bus_fsys { |
963 | compatible = "samsung,exynos-bus"; | |
964 | clocks = <&clock CLK_DOUT_ACLK200_FSYS>; | |
965 | clock-names = "bus"; | |
966 | operating-points-v2 = <&bus_fsys_apb_opp_table>; | |
967 | status = "disabled"; | |
b04a62d3 | 968 | }; |
5d99cc59 KK |
969 | |
970 | bus_fsys2: bus_fsys2 { | |
971 | compatible = "samsung,exynos-bus"; | |
972 | clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; | |
973 | clock-names = "bus"; | |
974 | operating-points-v2 = <&bus_fsys2_opp_table>; | |
975 | status = "disabled"; | |
b04a62d3 | 976 | }; |
5d99cc59 KK |
977 | |
978 | bus_mfc: bus_mfc { | |
979 | compatible = "samsung,exynos-bus"; | |
980 | clocks = <&clock CLK_DOUT_ACLK333>; | |
981 | clock-names = "bus"; | |
982 | operating-points-v2 = <&bus_mfc_opp_table>; | |
983 | status = "disabled"; | |
b04a62d3 | 984 | }; |
b04a62d3 | 985 | |
5d99cc59 KK |
986 | bus_gen: bus_gen { |
987 | compatible = "samsung,exynos-bus"; | |
988 | clocks = <&clock CLK_DOUT_ACLK266>; | |
989 | clock-names = "bus"; | |
990 | operating-points-v2 = <&bus_gen_opp_table>; | |
991 | status = "disabled"; | |
992 | }; | |
b04a62d3 | 993 | |
5d99cc59 KK |
994 | bus_peri: bus_peri { |
995 | compatible = "samsung,exynos-bus"; | |
996 | clocks = <&clock CLK_DOUT_ACLK66>; | |
997 | clock-names = "bus"; | |
998 | operating-points-v2 = <&bus_peri_opp_table>; | |
999 | status = "disabled"; | |
b04a62d3 | 1000 | }; |
5d99cc59 KK |
1001 | |
1002 | bus_g2d: bus_g2d { | |
1003 | compatible = "samsung,exynos-bus"; | |
1004 | clocks = <&clock CLK_DOUT_ACLK333_G2D>; | |
1005 | clock-names = "bus"; | |
1006 | operating-points-v2 = <&bus_g2d_opp_table>; | |
1007 | status = "disabled"; | |
b04a62d3 | 1008 | }; |
b04a62d3 | 1009 | |
5d99cc59 KK |
1010 | bus_g2d_acp: bus_g2d_acp { |
1011 | compatible = "samsung,exynos-bus"; | |
1012 | clocks = <&clock CLK_DOUT_ACLK266_G2D>; | |
1013 | clock-names = "bus"; | |
1014 | operating-points-v2 = <&bus_g2d_acp_opp_table>; | |
1015 | status = "disabled"; | |
1016 | }; | |
b04a62d3 | 1017 | |
5d99cc59 KK |
1018 | bus_jpeg: bus_jpeg { |
1019 | compatible = "samsung,exynos-bus"; | |
1020 | clocks = <&clock CLK_DOUT_ACLK300_JPEG>; | |
1021 | clock-names = "bus"; | |
1022 | operating-points-v2 = <&bus_jpeg_opp_table>; | |
1023 | status = "disabled"; | |
b04a62d3 | 1024 | }; |
5d99cc59 KK |
1025 | |
1026 | bus_jpeg_apb: bus_jpeg_apb { | |
1027 | compatible = "samsung,exynos-bus"; | |
1028 | clocks = <&clock CLK_DOUT_ACLK166>; | |
1029 | clock-names = "bus"; | |
1030 | operating-points-v2 = <&bus_jpeg_apb_opp_table>; | |
1031 | status = "disabled"; | |
b04a62d3 | 1032 | }; |
5d99cc59 KK |
1033 | |
1034 | bus_disp1_fimd: bus_disp1_fimd { | |
1035 | compatible = "samsung,exynos-bus"; | |
1036 | clocks = <&clock CLK_DOUT_ACLK300_DISP1>; | |
1037 | clock-names = "bus"; | |
1038 | operating-points-v2 = <&bus_disp1_fimd_opp_table>; | |
1039 | status = "disabled"; | |
b04a62d3 | 1040 | }; |
b04a62d3 | 1041 | |
5d99cc59 KK |
1042 | bus_disp1: bus_disp1 { |
1043 | compatible = "samsung,exynos-bus"; | |
1044 | clocks = <&clock CLK_DOUT_ACLK400_DISP1>; | |
1045 | clock-names = "bus"; | |
1046 | operating-points-v2 = <&bus_disp1_opp_table>; | |
1047 | status = "disabled"; | |
1048 | }; | |
b04a62d3 | 1049 | |
5d99cc59 KK |
1050 | bus_gscl_scaler: bus_gscl_scaler { |
1051 | compatible = "samsung,exynos-bus"; | |
1052 | clocks = <&clock CLK_DOUT_ACLK300_GSCL>; | |
1053 | clock-names = "bus"; | |
1054 | operating-points-v2 = <&bus_gscl_opp_table>; | |
1055 | status = "disabled"; | |
b04a62d3 | 1056 | }; |
5d99cc59 KK |
1057 | |
1058 | bus_mscl: bus_mscl { | |
1059 | compatible = "samsung,exynos-bus"; | |
1060 | clocks = <&clock CLK_DOUT_ACLK400_MSCL>; | |
1061 | clock-names = "bus"; | |
1062 | operating-points-v2 = <&bus_mscl_opp_table>; | |
1063 | status = "disabled"; | |
b04a62d3 | 1064 | }; |
5d99cc59 KK |
1065 | |
1066 | bus_wcore_opp_table: opp_table2 { | |
1067 | compatible = "operating-points-v2"; | |
1068 | ||
1069 | opp00 { | |
1070 | opp-hz = /bits/ 64 <84000000>; | |
1071 | opp-microvolt = <925000>; | |
1072 | }; | |
1073 | opp01 { | |
1074 | opp-hz = /bits/ 64 <111000000>; | |
1075 | opp-microvolt = <950000>; | |
1076 | }; | |
1077 | opp02 { | |
1078 | opp-hz = /bits/ 64 <222000000>; | |
1079 | opp-microvolt = <950000>; | |
1080 | }; | |
1081 | opp03 { | |
1082 | opp-hz = /bits/ 64 <333000000>; | |
1083 | opp-microvolt = <950000>; | |
1084 | }; | |
1085 | opp04 { | |
1086 | opp-hz = /bits/ 64 <400000000>; | |
1087 | opp-microvolt = <987500>; | |
1088 | }; | |
1089 | }; | |
1090 | ||
1091 | bus_noc_opp_table: opp_table3 { | |
1092 | compatible = "operating-points-v2"; | |
1093 | ||
1094 | opp00 { | |
1095 | opp-hz = /bits/ 64 <67000000>; | |
1096 | }; | |
1097 | opp01 { | |
1098 | opp-hz = /bits/ 64 <75000000>; | |
1099 | }; | |
1100 | opp02 { | |
1101 | opp-hz = /bits/ 64 <86000000>; | |
1102 | }; | |
1103 | opp03 { | |
1104 | opp-hz = /bits/ 64 <100000000>; | |
1105 | }; | |
1106 | }; | |
1107 | ||
1108 | bus_fsys_apb_opp_table: opp_table4 { | |
1109 | compatible = "operating-points-v2"; | |
1110 | opp-shared; | |
1111 | ||
1112 | opp00 { | |
1113 | opp-hz = /bits/ 64 <100000000>; | |
1114 | }; | |
1115 | opp01 { | |
1116 | opp-hz = /bits/ 64 <200000000>; | |
1117 | }; | |
1118 | }; | |
1119 | ||
1120 | bus_fsys2_opp_table: opp_table5 { | |
1121 | compatible = "operating-points-v2"; | |
1122 | ||
1123 | opp00 { | |
1124 | opp-hz = /bits/ 64 <75000000>; | |
1125 | }; | |
1126 | opp01 { | |
1127 | opp-hz = /bits/ 64 <100000000>; | |
1128 | }; | |
1129 | opp02 { | |
1130 | opp-hz = /bits/ 64 <150000000>; | |
1131 | }; | |
1132 | }; | |
1133 | ||
1134 | bus_mfc_opp_table: opp_table6 { | |
1135 | compatible = "operating-points-v2"; | |
1136 | ||
1137 | opp00 { | |
1138 | opp-hz = /bits/ 64 <96000000>; | |
1139 | }; | |
1140 | opp01 { | |
1141 | opp-hz = /bits/ 64 <111000000>; | |
1142 | }; | |
1143 | opp02 { | |
1144 | opp-hz = /bits/ 64 <167000000>; | |
1145 | }; | |
1146 | opp03 { | |
1147 | opp-hz = /bits/ 64 <222000000>; | |
1148 | }; | |
1149 | opp04 { | |
1150 | opp-hz = /bits/ 64 <333000000>; | |
1151 | }; | |
1152 | }; | |
1153 | ||
1154 | bus_gen_opp_table: opp_table7 { | |
1155 | compatible = "operating-points-v2"; | |
1156 | ||
1157 | opp00 { | |
1158 | opp-hz = /bits/ 64 <89000000>; | |
1159 | }; | |
1160 | opp01 { | |
1161 | opp-hz = /bits/ 64 <133000000>; | |
1162 | }; | |
1163 | opp02 { | |
1164 | opp-hz = /bits/ 64 <178000000>; | |
1165 | }; | |
1166 | opp03 { | |
1167 | opp-hz = /bits/ 64 <267000000>; | |
1168 | }; | |
1169 | }; | |
1170 | ||
1171 | bus_peri_opp_table: opp_table8 { | |
1172 | compatible = "operating-points-v2"; | |
1173 | ||
1174 | opp00 { | |
1175 | opp-hz = /bits/ 64 <67000000>; | |
1176 | }; | |
1177 | }; | |
1178 | ||
1179 | bus_g2d_opp_table: opp_table9 { | |
1180 | compatible = "operating-points-v2"; | |
1181 | ||
1182 | opp00 { | |
1183 | opp-hz = /bits/ 64 <84000000>; | |
1184 | }; | |
1185 | opp01 { | |
1186 | opp-hz = /bits/ 64 <167000000>; | |
1187 | }; | |
1188 | opp02 { | |
1189 | opp-hz = /bits/ 64 <222000000>; | |
1190 | }; | |
1191 | opp03 { | |
1192 | opp-hz = /bits/ 64 <300000000>; | |
1193 | }; | |
1194 | opp04 { | |
1195 | opp-hz = /bits/ 64 <333000000>; | |
1196 | }; | |
1197 | }; | |
1198 | ||
1199 | bus_g2d_acp_opp_table: opp_table10 { | |
1200 | compatible = "operating-points-v2"; | |
1201 | ||
1202 | opp00 { | |
1203 | opp-hz = /bits/ 64 <67000000>; | |
1204 | }; | |
1205 | opp01 { | |
1206 | opp-hz = /bits/ 64 <133000000>; | |
1207 | }; | |
1208 | opp02 { | |
1209 | opp-hz = /bits/ 64 <178000000>; | |
1210 | }; | |
1211 | opp03 { | |
1212 | opp-hz = /bits/ 64 <267000000>; | |
1213 | }; | |
1214 | }; | |
1215 | ||
1216 | bus_jpeg_opp_table: opp_table11 { | |
1217 | compatible = "operating-points-v2"; | |
1218 | ||
1219 | opp00 { | |
1220 | opp-hz = /bits/ 64 <75000000>; | |
1221 | }; | |
1222 | opp01 { | |
1223 | opp-hz = /bits/ 64 <150000000>; | |
1224 | }; | |
1225 | opp02 { | |
1226 | opp-hz = /bits/ 64 <200000000>; | |
1227 | }; | |
1228 | opp03 { | |
1229 | opp-hz = /bits/ 64 <300000000>; | |
1230 | }; | |
1231 | }; | |
1232 | ||
1233 | bus_jpeg_apb_opp_table: opp_table12 { | |
1234 | compatible = "operating-points-v2"; | |
1235 | ||
1236 | opp00 { | |
1237 | opp-hz = /bits/ 64 <84000000>; | |
1238 | }; | |
1239 | opp01 { | |
1240 | opp-hz = /bits/ 64 <111000000>; | |
1241 | }; | |
1242 | opp02 { | |
1243 | opp-hz = /bits/ 64 <134000000>; | |
1244 | }; | |
1245 | opp03 { | |
1246 | opp-hz = /bits/ 64 <167000000>; | |
1247 | }; | |
1248 | }; | |
1249 | ||
1250 | bus_disp1_fimd_opp_table: opp_table13 { | |
1251 | compatible = "operating-points-v2"; | |
1252 | ||
1253 | opp00 { | |
1254 | opp-hz = /bits/ 64 <120000000>; | |
1255 | }; | |
1256 | opp01 { | |
1257 | opp-hz = /bits/ 64 <200000000>; | |
1258 | }; | |
1259 | }; | |
1260 | ||
1261 | bus_disp1_opp_table: opp_table14 { | |
1262 | compatible = "operating-points-v2"; | |
1263 | ||
1264 | opp00 { | |
1265 | opp-hz = /bits/ 64 <120000000>; | |
1266 | }; | |
1267 | opp01 { | |
1268 | opp-hz = /bits/ 64 <200000000>; | |
1269 | }; | |
1270 | opp02 { | |
1271 | opp-hz = /bits/ 64 <300000000>; | |
1272 | }; | |
1273 | }; | |
1274 | ||
1275 | bus_gscl_opp_table: opp_table15 { | |
1276 | compatible = "operating-points-v2"; | |
1277 | ||
1278 | opp00 { | |
1279 | opp-hz = /bits/ 64 <150000000>; | |
1280 | }; | |
1281 | opp01 { | |
1282 | opp-hz = /bits/ 64 <200000000>; | |
1283 | }; | |
1284 | opp02 { | |
1285 | opp-hz = /bits/ 64 <300000000>; | |
1286 | }; | |
1287 | }; | |
1288 | ||
1289 | bus_mscl_opp_table: opp_table16 { | |
1290 | compatible = "operating-points-v2"; | |
1291 | ||
1292 | opp00 { | |
1293 | opp-hz = /bits/ 64 <84000000>; | |
1294 | }; | |
1295 | opp01 { | |
1296 | opp-hz = /bits/ 64 <167000000>; | |
1297 | }; | |
1298 | opp02 { | |
1299 | opp-hz = /bits/ 64 <222000000>; | |
1300 | }; | |
1301 | opp03 { | |
1302 | opp-hz = /bits/ 64 <333000000>; | |
1303 | }; | |
1304 | opp04 { | |
1305 | opp-hz = /bits/ 64 <400000000>; | |
1306 | }; | |
b04a62d3 CC |
1307 | }; |
1308 | }; | |
1309 | ||
5d99cc59 KK |
1310 | thermal-zones { |
1311 | cpu0_thermal: cpu0-thermal { | |
1312 | thermal-sensors = <&tmu_cpu0>; | |
1313 | #include "exynos5420-trip-points.dtsi" | |
b04a62d3 | 1314 | }; |
5d99cc59 KK |
1315 | cpu1_thermal: cpu1-thermal { |
1316 | thermal-sensors = <&tmu_cpu1>; | |
1317 | #include "exynos5420-trip-points.dtsi" | |
b04a62d3 | 1318 | }; |
5d99cc59 KK |
1319 | cpu2_thermal: cpu2-thermal { |
1320 | thermal-sensors = <&tmu_cpu2>; | |
1321 | #include "exynos5420-trip-points.dtsi" | |
b04a62d3 | 1322 | }; |
5d99cc59 KK |
1323 | cpu3_thermal: cpu3-thermal { |
1324 | thermal-sensors = <&tmu_cpu3>; | |
1325 | #include "exynos5420-trip-points.dtsi" | |
b04a62d3 | 1326 | }; |
5d99cc59 KK |
1327 | gpu_thermal: gpu-thermal { |
1328 | thermal-sensors = <&tmu_gpu>; | |
1329 | #include "exynos5420-trip-points.dtsi" | |
b04a62d3 CC |
1330 | }; |
1331 | }; | |
34dcedfb | 1332 | }; |
3a3cf6c4 KK |
1333 | |
1334 | &dp { | |
1335 | clocks = <&clock CLK_DP1>; | |
1336 | clock-names = "dp"; | |
1337 | phys = <&dp_phy>; | |
1338 | phy-names = "dp"; | |
1339 | power-domains = <&disp_pd>; | |
1340 | }; | |
1341 | ||
1342 | &fimd { | |
6dc62f12 | 1343 | compatible = "samsung,exynos5420-fimd"; |
3a3cf6c4 KK |
1344 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
1345 | clock-names = "sclk_fimd", "fimd"; | |
1346 | power-domains = <&disp_pd>; | |
b7004516 MS |
1347 | iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; |
1348 | iommu-names = "m0", "m1"; | |
3a3cf6c4 KK |
1349 | }; |
1350 | ||
5a124fe0 KK |
1351 | &i2c_0 { |
1352 | clocks = <&clock CLK_I2C0>; | |
1353 | clock-names = "i2c"; | |
1354 | pinctrl-names = "default"; | |
1355 | pinctrl-0 = <&i2c0_bus>; | |
1356 | }; | |
1357 | ||
1358 | &i2c_1 { | |
1359 | clocks = <&clock CLK_I2C1>; | |
1360 | clock-names = "i2c"; | |
1361 | pinctrl-names = "default"; | |
1362 | pinctrl-0 = <&i2c1_bus>; | |
1363 | }; | |
1364 | ||
1365 | &i2c_2 { | |
1366 | clocks = <&clock CLK_I2C2>; | |
1367 | clock-names = "i2c"; | |
1368 | pinctrl-names = "default"; | |
1369 | pinctrl-0 = <&i2c2_bus>; | |
1370 | }; | |
1371 | ||
1372 | &i2c_3 { | |
1373 | clocks = <&clock CLK_I2C3>; | |
1374 | clock-names = "i2c"; | |
1375 | pinctrl-names = "default"; | |
1376 | pinctrl-0 = <&i2c3_bus>; | |
1377 | }; | |
1378 | ||
538fc7ad KK |
1379 | &hsi2c_4 { |
1380 | clocks = <&clock CLK_USI0>; | |
1381 | clock-names = "hsi2c"; | |
1382 | pinctrl-names = "default"; | |
1383 | pinctrl-0 = <&i2c4_hs_bus>; | |
1384 | }; | |
1385 | ||
1386 | &hsi2c_5 { | |
1387 | clocks = <&clock CLK_USI1>; | |
1388 | clock-names = "hsi2c"; | |
1389 | pinctrl-names = "default"; | |
1390 | pinctrl-0 = <&i2c5_hs_bus>; | |
1391 | }; | |
1392 | ||
1393 | &hsi2c_6 { | |
1394 | clocks = <&clock CLK_USI2>; | |
1395 | clock-names = "hsi2c"; | |
1396 | pinctrl-names = "default"; | |
1397 | pinctrl-0 = <&i2c6_hs_bus>; | |
1398 | }; | |
1399 | ||
1400 | &hsi2c_7 { | |
1401 | clocks = <&clock CLK_USI3>; | |
1402 | clock-names = "hsi2c"; | |
1403 | pinctrl-names = "default"; | |
1404 | pinctrl-0 = <&i2c7_hs_bus>; | |
1405 | }; | |
1406 | ||
c9cf996d KK |
1407 | &mct { |
1408 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; | |
1409 | clock-names = "fin_pll", "mct"; | |
1410 | }; | |
1411 | ||
5a124fe0 KK |
1412 | &pwm { |
1413 | clocks = <&clock CLK_PWM>; | |
1414 | clock-names = "timers"; | |
1415 | }; | |
1416 | ||
3a3cf6c4 KK |
1417 | &rtc { |
1418 | clocks = <&clock CLK_RTC>; | |
1419 | clock-names = "rtc"; | |
1420 | interrupt-parent = <&pmu_system_controller>; | |
1421 | status = "disabled"; | |
1422 | }; | |
1423 | ||
1424 | &serial_0 { | |
1425 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; | |
1426 | clock-names = "uart", "clk_uart_baud0"; | |
3590312f MS |
1427 | dmas = <&pdma0 13>, <&pdma0 14>; |
1428 | dma-names = "rx", "tx"; | |
3a3cf6c4 KK |
1429 | }; |
1430 | ||
1431 | &serial_1 { | |
1432 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; | |
1433 | clock-names = "uart", "clk_uart_baud0"; | |
3590312f MS |
1434 | dmas = <&pdma1 15>, <&pdma1 16>; |
1435 | dma-names = "rx", "tx"; | |
3a3cf6c4 KK |
1436 | }; |
1437 | ||
1438 | &serial_2 { | |
1439 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; | |
1440 | clock-names = "uart", "clk_uart_baud0"; | |
3590312f MS |
1441 | dmas = <&pdma0 15>, <&pdma0 16>; |
1442 | dma-names = "rx", "tx"; | |
3a3cf6c4 KK |
1443 | }; |
1444 | ||
1445 | &serial_3 { | |
1446 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; | |
1447 | clock-names = "uart", "clk_uart_baud0"; | |
3590312f MS |
1448 | dmas = <&pdma1 17>, <&pdma1 18>; |
1449 | dma-names = "rx", "tx"; | |
3a3cf6c4 | 1450 | }; |
c07f8270 | 1451 | |
b8bd7e23 KK |
1452 | &sss { |
1453 | clocks = <&clock CLK_SSS>; | |
1454 | clock-names = "secss"; | |
1455 | }; | |
1456 | ||
cb089656 KK |
1457 | &usbdrd3_0 { |
1458 | clocks = <&clock CLK_USBD300>; | |
1459 | clock-names = "usbdrd30"; | |
1460 | }; | |
1461 | ||
1462 | &usbdrd_phy0 { | |
1463 | clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; | |
1464 | clock-names = "phy", "ref"; | |
1465 | samsung,pmu-syscon = <&pmu_system_controller>; | |
1466 | }; | |
1467 | ||
1468 | &usbdrd3_1 { | |
1469 | clocks = <&clock CLK_USBD301>; | |
1470 | clock-names = "usbdrd30"; | |
1471 | }; | |
1472 | ||
e5995e6d | 1473 | &usbdrd_dwc3_1 { |
6abdf8d1 | 1474 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
e5995e6d KK |
1475 | }; |
1476 | ||
cb089656 KK |
1477 | &usbdrd_phy1 { |
1478 | clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; | |
1479 | clock-names = "phy", "ref"; | |
1480 | samsung,pmu-syscon = <&pmu_system_controller>; | |
1481 | }; | |
1482 | ||
1483 | &usbhost1 { | |
1484 | clocks = <&clock CLK_USBH20>; | |
1485 | clock-names = "usbhost"; | |
1486 | }; | |
1487 | ||
1488 | &usbhost2 { | |
1489 | clocks = <&clock CLK_USBH20>; | |
1490 | clock-names = "usbhost"; | |
1491 | }; | |
1492 | ||
1493 | &usb2_phy { | |
1494 | clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; | |
1495 | clock-names = "phy", "ref"; | |
1496 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
1497 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
1498 | }; | |
1499 | ||
b8bd7e23 KK |
1500 | &watchdog { |
1501 | clocks = <&clock CLK_WDT>; | |
1502 | clock-names = "watchdog"; | |
1503 | samsung,syscon-phandle = <&pmu_system_controller>; | |
1504 | }; | |
1505 | ||
c07f8270 | 1506 | #include "exynos5420-pinctrl.dtsi" |