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f3d953ea TL |
1 | /* |
2 | * This file is licensed under the terms of the GNU General Public License | |
3 | * version 2. This program is licensed "as is" without any warranty of any | |
4 | * kind, whether express or implied. | |
5 | */ | |
6 | ||
7 | #include <dt-bindings/gpio/gpio.h> | |
8 | #include <dt-bindings/pinctrl/omap.h> | |
9 | ||
10 | #include "skeleton.dtsi" | |
11 | ||
12 | / { | |
13 | compatible = "ti,dm814"; | |
14 | interrupt-parent = <&intc>; | |
15 | ||
16 | aliases { | |
17 | i2c0 = &i2c1; | |
18 | i2c1 = &i2c2; | |
19 | serial0 = &uart1; | |
20 | serial1 = &uart2; | |
21 | serial2 = &uart3; | |
22 | ethernet0 = &cpsw_emac0; | |
23 | ethernet1 = &cpsw_emac1; | |
24 | }; | |
25 | ||
26 | cpus { | |
27 | #address-cells = <1>; | |
28 | #size-cells = <0>; | |
29 | cpu@0 { | |
30 | compatible = "arm,cortex-a8"; | |
31 | device_type = "cpu"; | |
32 | reg = <0>; | |
33 | }; | |
34 | }; | |
35 | ||
36 | pmu { | |
37 | compatible = "arm,cortex-a8-pmu"; | |
38 | interrupts = <3>; | |
39 | }; | |
40 | ||
41 | /* | |
42 | * The soc node represents the soc top level view. It is used for IPs | |
43 | * that are not memory mapped in the MPU view or for the MPU itself. | |
44 | */ | |
45 | soc { | |
46 | compatible = "ti,omap-infra"; | |
47 | mpu { | |
48 | compatible = "ti,omap3-mpu"; | |
49 | ti,hwmods = "mpu"; | |
50 | }; | |
51 | }; | |
52 | ||
53 | ocp { | |
54 | compatible = "simple-bus"; | |
55 | #address-cells = <1>; | |
56 | #size-cells = <1>; | |
57 | ranges; | |
58 | ti,hwmods = "l3_main"; | |
59 | ||
60 | /* | |
61 | * See TRM "Table 1-317. L4LS Instance Summary", just deduct | |
62 | * 0x1000 from the 1-317 addresses to get the device address | |
63 | */ | |
64 | l4ls: l4ls@48000000 { | |
65 | compatible = "ti,dm814-l4ls", "simple-bus"; | |
66 | #address-cells = <1>; | |
67 | #size-cells = <1>; | |
68 | ranges = <0 0x48000000 0x2000000>; | |
69 | ||
70 | i2c1: i2c@28000 { | |
71 | compatible = "ti,omap4-i2c"; | |
72 | #address-cells = <1>; | |
73 | #size-cells = <0>; | |
74 | ti,hwmods = "i2c1"; | |
75 | reg = <0x28000 0x1000>; | |
76 | interrupts = <70>; | |
77 | }; | |
78 | ||
79 | elm: elm@80000 { | |
80 | compatible = "ti,814-elm"; | |
81 | ti,hwmods = "elm"; | |
82 | reg = <0x80000 0x2000>; | |
83 | interrupts = <4>; | |
84 | }; | |
85 | ||
86 | gpio1: gpio@32000 { | |
87 | compatible = "ti,omap4-gpio"; | |
88 | ti,hwmods = "gpio1"; | |
89 | ti,gpio-always-on; | |
90 | reg = <0x32000 0x2000>; | |
91 | interrupts = <96>; | |
92 | gpio-controller; | |
93 | #gpio-cells = <2>; | |
94 | interrupt-controller; | |
95 | #interrupt-cells = <2>; | |
96 | }; | |
97 | ||
98 | gpio2: gpio@4c000 { | |
99 | compatible = "ti,omap4-gpio"; | |
100 | ti,hwmods = "gpio2"; | |
101 | ti,gpio-always-on; | |
102 | reg = <0x4c000 0x2000>; | |
103 | interrupts = <98>; | |
104 | gpio-controller; | |
105 | #gpio-cells = <2>; | |
106 | interrupt-controller; | |
107 | #interrupt-cells = <2>; | |
108 | }; | |
109 | ||
110 | i2c2: i2c@2a000 { | |
111 | compatible = "ti,omap4-i2c"; | |
112 | #address-cells = <1>; | |
113 | #size-cells = <0>; | |
114 | ti,hwmods = "i2c2"; | |
115 | reg = <0x2a000 0x1000>; | |
116 | interrupts = <71>; | |
117 | }; | |
118 | ||
119 | mcspi1: spi@30000 { | |
120 | compatible = "ti,omap4-mcspi"; | |
121 | reg = <0x30000 0x1000>; | |
122 | #address-cells = <1>; | |
123 | #size-cells = <0>; | |
124 | interrupts = <65>; | |
125 | ti,spi-num-cs = <4>; | |
126 | ti,hwmods = "mcspi1"; | |
127 | dmas = <&edma 16 &edma 17 | |
128 | &edma 18 &edma 19>; | |
129 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
130 | }; | |
131 | ||
132 | timer1: timer@2e000 { | |
133 | compatible = "ti,dm814-timer"; | |
134 | reg = <0x2e000 0x2000>; | |
135 | interrupts = <67>; | |
136 | ti,hwmods = "timer1"; | |
137 | ti,timer-alwon; | |
138 | }; | |
139 | ||
140 | uart1: uart@20000 { | |
141 | compatible = "ti,omap3-uart"; | |
142 | ti,hwmods = "uart1"; | |
143 | reg = <0x20000 0x2000>; | |
144 | clock-frequency = <48000000>; | |
145 | interrupts = <72>; | |
146 | dmas = <&edma 26 &edma 27>; | |
147 | dma-names = "tx", "rx"; | |
148 | }; | |
149 | ||
150 | uart2: uart@22000 { | |
151 | compatible = "ti,omap3-uart"; | |
152 | ti,hwmods = "uart2"; | |
153 | reg = <0x22000 0x2000>; | |
154 | clock-frequency = <48000000>; | |
155 | interrupts = <73>; | |
156 | dmas = <&edma 28 &edma 29>; | |
157 | dma-names = "tx", "rx"; | |
158 | }; | |
159 | ||
160 | uart3: uart@24000 { | |
161 | compatible = "ti,omap3-uart"; | |
162 | ti,hwmods = "uart3"; | |
163 | reg = <0x24000 0x2000>; | |
164 | clock-frequency = <48000000>; | |
165 | interrupts = <74>; | |
166 | dmas = <&edma 30 &edma 31>; | |
167 | dma-names = "tx", "rx"; | |
168 | }; | |
169 | ||
170 | timer2: timer@40000 { | |
171 | compatible = "ti,dm814-timer"; | |
172 | reg = <0x40000 0x2000>; | |
173 | interrupts = <68>; | |
174 | ti,hwmods = "timer2"; | |
175 | }; | |
176 | ||
177 | timer3: timer@42000 { | |
178 | compatible = "ti,dm814-timer"; | |
179 | reg = <0x42000 0x2000>; | |
180 | interrupts = <69>; | |
181 | ti,hwmods = "timer3"; | |
182 | }; | |
183 | ||
87ee15ec | 184 | control: control@140000 { |
f3d953ea | 185 | compatible = "ti,dm814-scm", "simple-bus"; |
87ee15ec | 186 | reg = <0x140000 0x16d000>; |
f3d953ea TL |
187 | #address-cells = <1>; |
188 | #size-cells = <1>; | |
189 | ranges = <0 0x160000 0x16d000>; | |
190 | ||
191 | scm_conf: scm_conf@0 { | |
192 | compatible = "syscon"; | |
193 | reg = <0x0 0x800>; | |
194 | #address-cells = <1>; | |
195 | #size-cells = <1>; | |
196 | ||
197 | scm_clocks: clocks { | |
198 | #address-cells = <1>; | |
199 | #size-cells = <0>; | |
200 | }; | |
201 | ||
202 | scm_clockdomains: clockdomains { | |
203 | }; | |
204 | }; | |
205 | ||
206 | pincntl: pinmux@800 { | |
207 | compatible = "pinctrl-single"; | |
208 | reg = <0x800 0xc38>; | |
209 | #address-cells = <1>; | |
210 | #size-cells = <0>; | |
211 | pinctrl-single,register-width = <32>; | |
212 | pinctrl-single,function-mask = <0x300ff>; | |
213 | }; | |
214 | }; | |
215 | ||
216 | prcm: prcm@180000 { | |
217 | compatible = "ti,dm814-prcm", "simple-bus"; | |
218 | reg = <0x180000 0x4000>; | |
219 | ||
220 | prcm_clocks: clocks { | |
221 | #address-cells = <1>; | |
222 | #size-cells = <0>; | |
223 | }; | |
224 | ||
225 | prcm_clockdomains: clockdomains { | |
226 | }; | |
227 | }; | |
228 | ||
229 | pllss: pllss@1c5000 { | |
230 | compatible = "ti,dm814-pllss", "simple-bus"; | |
231 | reg = <0x1c5000 0x2000>; | |
232 | ||
233 | pllss_clocks: clocks { | |
234 | #address-cells = <1>; | |
235 | #size-cells = <0>; | |
236 | }; | |
237 | ||
238 | pllss_clockdomains: clockdomains { | |
239 | }; | |
240 | }; | |
241 | ||
242 | wdt1: wdt@1c7000 { | |
243 | compatible = "ti,omap3-wdt"; | |
244 | ti,hwmods = "wd_timer"; | |
245 | reg = <0x1c7000 0x1000>; | |
246 | interrupts = <91>; | |
247 | }; | |
248 | }; | |
249 | ||
250 | intc: interrupt-controller@48200000 { | |
251 | compatible = "ti,dm814-intc"; | |
252 | interrupt-controller; | |
253 | #interrupt-cells = <1>; | |
254 | reg = <0x48200000 0x1000>; | |
255 | }; | |
256 | ||
257 | edma: edma@49000000 { | |
258 | compatible = "ti,edma3"; | |
259 | ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; | |
260 | reg = <0x49000000 0x10000>, | |
261 | <0x44e10f90 0x40>; | |
262 | interrupts = <12 13 14>; | |
263 | #dma-cells = <1>; | |
264 | }; | |
265 | ||
266 | /* See TRM "Table 1-318. L4HS Instance Summary" */ | |
267 | l4hs: l4hs@4a000000 { | |
268 | compatible = "ti,dm814-l4hs", "simple-bus"; | |
269 | #address-cells = <1>; | |
270 | #size-cells = <1>; | |
271 | ranges = <0 0x4a000000 0x1b4040>; | |
272 | }; | |
273 | ||
274 | /* REVISIT: Move to live under l4hs once driver is fixed */ | |
275 | mac: ethernet@4a100000 { | |
276 | compatible = "ti,cpsw"; | |
277 | ti,hwmods = "cpgmac0"; | |
278 | clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; | |
279 | clock-names = "fck", "cpts"; | |
280 | cpdma_channels = <8>; | |
281 | ale_entries = <1024>; | |
282 | bd_ram_size = <0x2000>; | |
283 | no_bd_ram = <0>; | |
284 | rx_descs = <64>; | |
285 | mac_control = <0x20>; | |
286 | slaves = <2>; | |
287 | active_slave = <0>; | |
288 | cpts_clock_mult = <0x80000000>; | |
289 | cpts_clock_shift = <29>; | |
290 | reg = <0x4a100000 0x800 | |
291 | 0x4a100900 0x100>; | |
292 | #address-cells = <1>; | |
293 | #size-cells = <1>; | |
294 | interrupt-parent = <&intc>; | |
295 | /* | |
296 | * c0_rx_thresh_pend | |
297 | * c0_rx_pend | |
298 | * c0_tx_pend | |
299 | * c0_misc_pend | |
300 | */ | |
301 | interrupts = <40 41 42 43>; | |
302 | ranges; | |
303 | syscon = <&scm_conf>; | |
304 | ||
305 | davinci_mdio: mdio@4a100800 { | |
306 | compatible = "ti,davinci_mdio"; | |
307 | #address-cells = <1>; | |
308 | #size-cells = <0>; | |
309 | ti,hwmods = "davinci_mdio"; | |
310 | bus_freq = <1000000>; | |
311 | reg = <0x4a100800 0x100>; | |
312 | }; | |
313 | ||
314 | cpsw_emac0: slave@4a100200 { | |
315 | /* Filled in by U-Boot */ | |
316 | mac-address = [ 00 00 00 00 00 00 ]; | |
317 | }; | |
318 | ||
319 | cpsw_emac1: slave@4a100300 { | |
320 | /* Filled in by U-Boot */ | |
321 | mac-address = [ 00 00 00 00 00 00 ]; | |
322 | }; | |
323 | ||
87ee15ec | 324 | phy_sel: cpsw-phy-sel@48140650 { |
f3d953ea | 325 | compatible = "ti,am3352-cpsw-phy-sel"; |
87ee15ec | 326 | reg= <0x48140650 0x4>; |
f3d953ea TL |
327 | reg-names = "gmii-sel"; |
328 | }; | |
329 | }; | |
330 | }; | |
331 | }; | |
25515b63 TL |
332 | |
333 | #include "dm814x-clocks.dtsi" |