[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / boot / dts / at91sam9n12.dtsi

/*
 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
 *
 *  Copyright (C) 2012 Atmel,
 *                2012 Hong Xu <hong.xu@atmel.com>
 *
 * Licensed under GPLv2 or later.
 */

/include/ "skeleton.dtsi"

/ {
	model = "Atmel AT91SAM9N12 SoC";
	compatible = "atmel,at91sam9n12";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &dbgu;
		serial1 = &usart0;
		serial2 = &usart1;
		serial3 = &usart2;
		serial4 = &usart3;
		gpio0 = &pioA;
		gpio1 = &pioB;
		gpio2 = &pioC;
		gpio3 = &pioD;
		tcb0 = &tcb0;
		tcb1 = &tcb1;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		ssc0 = &ssc0;
	};
	cpus {
		cpu@0 {
			compatible = "arm,arm926ejs";
		};
	};

	memory {
		reg = <0x20000000 0x10000000>;
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			aic: interrupt-controller@fffff000 {
				#interrupt-cells = <3>;
				compatible = "atmel,at91rm9200-aic";
				interrupt-controller;
				reg = <0xfffff000 0x200>;
				atmel,external-irqs = <31>;
			};

			ramc0: ramc@ffffe800 {
				compatible = "atmel,at91sam9g45-ddramc";
				reg = <0xffffe800 0x200>;
			};

			pmc: pmc@fffffc00 {
				compatible = "atmel,at91rm9200-pmc";
				reg = <0xfffffc00 0x100>;
			};

			rstc@fffffe00 {
				compatible = "atmel,at91sam9g45-rstc";
				reg = <0xfffffe00 0x10>;
			};

			pit: timer@fffffe30 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xfffffe30 0xf>;
				interrupts = <1 4 7>;
			};

			shdwc@fffffe10 {
				compatible = "atmel,at91sam9x5-shdwc";
				reg = <0xfffffe10 0x10>;
			};

			mmc0: mmc@f0008000 {
				compatible = "atmel,hsmci";
				reg = <0xf0008000 0x600>;
				interrupts = <12 4 0>;
				dmas = <&dma 1 0>;
				dma-names = "rxtx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			tcb0: timer@f8008000 {
				compatible = "atmel,at91sam9x5-tcb";
				reg = <0xf8008000 0x100>;
				interrupts = <17 4 0>;
			};

			tcb1: timer@f800c000 {
				compatible = "atmel,at91sam9x5-tcb";
				reg = <0xf800c000 0x100>;
				interrupts = <17 4 0>;
			};

			dma: dma-controller@ffffec00 {
				compatible = "atmel,at91sam9g45-dma";
				reg = <0xffffec00 0x200>;
				interrupts = <20 4 0>;
				#dma-cells = <2>;
			};

			pinctrl@fffff400 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
				ranges = <0xfffff400 0xfffff400 0x800>;

				atmel,mux-mask = <
				      /*    A         B          C     */
				       0xffffffff 0xffe07983 0x00000000  /* pioA */
				       0x00040000 0x00047e0f 0x00000000  /* pioB */
				       0xfdffffff 0x07c00000 0xb83fffff  /* pioC */
				       0x003fffff 0x003f8000 0x00000000  /* pioD */
				      >;

				/* shared pinctrl settings */
				dbgu {
					pinctrl_dbgu: dbgu-0 {
						atmel,pins =
							<0 9 0x1 0x0	/* PA9 periph A */
							 0 10 0x1 0x1>;	/* PA10 periph with pullup */
					};
				};

				usart0 {
					pinctrl_usart0: usart0-0 {
						atmel,pins =
							<0 1 0x1 0x1	/* PA1 periph A with pullup */
							 0 0 0x1 0x0>;	/* PA0 periph A */
					};

					pinctrl_usart0_rts: usart0_rts-0 {
						atmel,pins =
							<0 2 0x1 0x0>;	/* PA2 periph A */
					};

					pinctrl_usart0_cts: usart0_cts-0 {
						atmel,pins =
							<0 3 0x1 0x0>;	/* PA3 periph A */
					};
				};

				usart1 {
					pinctrl_usart1: usart1-0 {
						atmel,pins =
							<0 6 0x1 0x1	/* PA6 periph A with pullup */
							 0 5 0x1 0x0>;	/* PA5 periph A */
					};
				};

				usart2 {
					pinctrl_usart2: usart2-0 {
						atmel,pins =
							<0 8 0x1 0x1	/* PA8 periph A with pullup */
							 0 7 0x1 0x0>;	/* PA7 periph A */
					};

					pinctrl_usart2_rts: usart2_rts-0 {
						atmel,pins =
							<1 0 0x2 0x0>;	/* PB0 periph B */
					};

					pinctrl_usart2_cts: usart2_cts-0 {
						atmel,pins =
							<1 1 0x2 0x0>;	/* PB1 periph B */
					};
				};

				usart3 {
					pinctrl_usart3: usart3-0 {
						atmel,pins =
							<2 23 0x2 0x1	/* PC23 periph B with pullup */
							 2 22 0x2 0x0>;	/* PC22 periph B */
					};

					pinctrl_usart3_rts: usart3_rts-0 {
						atmel,pins =
							<2 24 0x2 0x0>;	/* PC24 periph B */
					};

					pinctrl_usart3_cts: usart3_cts-0 {
						atmel,pins =
							<2 25 0x2 0x0>;	/* PC25 periph B */
					};
				};

				uart0 {
					pinctrl_uart0: uart0-0 {
						atmel,pins =
							<2 9 0x3 0x1	/* PC9 periph C with pullup */
							 2 8 0x3 0x0>;	/* PC8 periph C */
					};
				};

				uart1 {
					pinctrl_uart1: uart1-0 {
						atmel,pins =
							<2 16 0x3 0x1	/* PC17 periph C with pullup */
							 2 17 0x3 0x0>;	/* PC16 periph C */
					};
				};

				nand {
					pinctrl_nand: nand-0 {
						atmel,pins =
							<3 5 0x0 0x1	/* PD5 gpio RDY pin pull_up*/
							 3 4 0x0 0x1>;	/* PD4 gpio enable pin pull_up */
					};
				};

				mmc0 {
					pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
						atmel,pins =
							<0 17 0x1 0x0	/* PA17 periph A */
							 0 16 0x1 0x1	/* PA16 periph A with pullup */
							 0 15 0x1 0x1>;	/* PA15 periph A with pullup */
					};

					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
						atmel,pins =
							<0 18 0x1 0x1	/* PA18 periph A with pullup */
							 0 19 0x1 0x1	/* PA19 periph A with pullup */
							 0 20 0x1 0x1>;	/* PA20 periph A with pullup */
					};

					pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
						atmel,pins =
							<0 11 0x2 0x1	/* PA11 periph B with pullup */
							 0 12 0x2 0x1	/* PA12 periph B with pullup */
							 0 13 0x2 0x1	/* PA13 periph B with pullup */
							 0 14 0x2 0x1>;	/* PA14 periph B with pullup */
					};
				};

				ssc0 {
					pinctrl_ssc0_tx: ssc0_tx-0 {
						atmel,pins =
							<0 24 0x2 0x0	/* PA24 periph B */
							 0 25 0x2 0x0	/* PA25 periph B */
							 0 26 0x2 0x0>;	/* PA26 periph B */
					};

					pinctrl_ssc0_rx: ssc0_rx-0 {
						atmel,pins =
							<0 27 0x2 0x0	/* PA27 periph B */
							 0 28 0x2 0x0	/* PA28 periph B */
							 0 29 0x2 0x0>;	/* PA29 periph B */
					};
				};

				spi0 {
					pinctrl_spi0: spi0-0 {
						atmel,pins =
							<0 11 0x1 0x0	/* PA11 periph A SPI0_MISO pin */
							 0 12 0x1 0x0	/* PA12 periph A SPI0_MOSI pin */
							 0 13 0x1 0x0>;	/* PA13 periph A SPI0_SPCK pin */
					};
				};

				spi1 {
					pinctrl_spi1: spi1-0 {
						atmel,pins =
							<0 21 0x2 0x0	/* PA21 periph B SPI1_MISO pin */
							 0 22 0x2 0x0	/* PA22 periph B SPI1_MOSI pin */
							 0 23 0x2 0x0>;	/* PA23 periph B SPI1_SPCK pin */
					};
				};

				pioA: gpio@fffff400 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff400 0x200>;
					interrupts = <2 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioB: gpio@fffff600 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff600 0x200>;
					interrupts = <2 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioC: gpio@fffff800 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff800 0x200>;
					interrupts = <3 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioD: gpio@fffffa00 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffffa00 0x200>;
					interrupts = <3 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};
			};

			dbgu: serial@fffff200 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfffff200 0x200>;
				interrupts = <1 4 7>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_dbgu>;
				status = "disabled";
			};

			ssc0: ssc@f0010000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xf0010000 0x4000>;
				interrupts = <28 4 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
				status = "disabled";
			};

			usart0: serial@f801c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf801c000 0x4000>;
				interrupts = <5 4 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart0>;
				status = "disabled";
			};

			usart1: serial@f8020000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8020000 0x4000>;
				interrupts = <6 4 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart1>;
				status = "disabled";
			};

			usart2: serial@f8024000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8024000 0x4000>;
				interrupts = <7 4 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart2>;
				status = "disabled";
			};

			usart3: serial@f8028000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8028000 0x4000>;
				interrupts = <8 4 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart3>;
				status = "disabled";
			};

			i2c0: i2c@f8010000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8010000 0x100>;
				interrupts = <9 4 6>;
				dmas = <&dma 1 13>,
				       <&dma 1 14>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c1: i2c@f8014000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8014000 0x100>;
				interrupts = <10 4 6>;
				dmas = <&dma 1 15>,
				       <&dma 1 16>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi0: spi@f0000000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xf0000000 0x100>;
				interrupts = <13 4 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi0>;
				status = "disabled";
			};

			spi1: spi@f0004000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xf0004000 0x100>;
				interrupts = <14 4 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi1>;
				status = "disabled";
			};
		};

		nand0: nand@40000000 {
			compatible = "atmel,at91rm9200-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = < 0x40000000 0x10000000
				0xffffe000 0x00000600
				0xffffe600 0x00000200
				0x00108000 0x00018000
			       >;
			atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
			atmel,nand-addr-offset = <21>;
			atmel,nand-cmd-offset = <22>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			gpios = <&pioD 5 0
				 &pioD 4 0
				 0
				>;
			status = "disabled";
		};

		usb0: ohci@00500000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00500000 0x00100000>;
			interrupts = <22 4 2>;
			status = "disabled";
		};
	};

	i2c@0 {
		compatible = "i2c-gpio";
		gpios = <&pioA 30 0 /* sda */
			 &pioA 31 0 /* scl */
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};
};
Commit	Line	Data
cce783c6 HX	1	/*
	2	* at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
	3	*
	4	* Copyright (C) 2012 Atmel,
	5	* 2012 Hong Xu <hong.xu@atmel.com>
	6	*
	7	* Licensed under GPLv2 or later.
	8	*/
	9
	10	/include/ "skeleton.dtsi"
	11
	12	/ {
	13	model = "Atmel AT91SAM9N12 SoC";
	14	compatible = "atmel,at91sam9n12";
	15	interrupt-parent = <&aic>;
	16
	17	aliases {
	18	serial0 = &dbgu;
	19	serial1 = &usart0;
	20	serial2 = &usart1;
	21	serial3 = &usart2;
	22	serial4 = &usart3;
	23	gpio0 = &pioA;
	24	gpio1 = &pioB;
	25	gpio2 = &pioC;
	26	gpio3 = &pioD;
	27	tcb0 = &tcb0;
	28	tcb1 = &tcb1;
05dcd361 LD	29	i2c0 = &i2c0;
05dcd361 LD	30	i2c1 = &i2c1;
544ae6b2	31	ssc0 = &ssc0;
cce783c6 HX	32	};
	33	cpus {
	34	cpu@0 {
	35	compatible = "arm,arm926ejs";
	36	};
	37	};
	38
	39	memory {
	40	reg = <0x20000000 0x10000000>;
	41	};
	42
	43	ahb {
	44	compatible = "simple-bus";
	45	#address-cells = <1>;
	46	#size-cells = <1>;
	47	ranges;
	48
	49	apb {
	50	compatible = "simple-bus";
	51	#address-cells = <1>;
	52	#size-cells = <1>;
	53	ranges;
	54
	55	aic: interrupt-controller@fffff000 {
f8a073ee	56	#interrupt-cells = <3>;
cce783c6 HX	57	compatible = "atmel,at91rm9200-aic";
	58	interrupt-controller;
	59	reg = <0xfffff000 0x200>;
029efdda	60	atmel,external-irqs = <31>;
cce783c6 HX	61	};
	62
	63	ramc0: ramc@ffffe800 {
	64	compatible = "atmel,at91sam9g45-ddramc";
	65	reg = <0xffffe800 0x200>;
	66	};
	67
	68	pmc: pmc@fffffc00 {
	69	compatible = "atmel,at91rm9200-pmc";
	70	reg = <0xfffffc00 0x100>;
	71	};
	72
	73	rstc@fffffe00 {
	74	compatible = "atmel,at91sam9g45-rstc";
	75	reg = <0xfffffe00 0x10>;
	76	};
	77
	78	pit: timer@fffffe30 {
	79	compatible = "atmel,at91sam9260-pit";
	80	reg = <0xfffffe30 0xf>;
f8a073ee	81	interrupts = <1 4 7>;
cce783c6 HX	82	};
	83
	84	shdwc@fffffe10 {
	85	compatible = "atmel,at91sam9x5-shdwc";
	86	reg = <0xfffffe10 0x10>;
	87	};
	88
9873137a LD	89	mmc0: mmc@f0008000 {
	90	compatible = "atmel,hsmci";
	91	reg = <0xf0008000 0x600>;
	92	interrupts = <12 4 0>;
05c1bc97 LD	93	dmas = <&dma 1 0>;
05c1bc97 LD	94	dma-names = "rxtx";
9873137a LD	95	#address-cells = <1>;
	96	#size-cells = <0>;
	97	status = "disabled";
	98	};
	99
cce783c6 HX	100	tcb0: timer@f8008000 {
	101	compatible = "atmel,at91sam9x5-tcb";
	102	reg = <0xf8008000 0x100>;
f8a073ee	103	interrupts = <17 4 0>;
cce783c6 HX	104	};
	105
	106	tcb1: timer@f800c000 {
	107	compatible = "atmel,at91sam9x5-tcb";
	108	reg = <0xf800c000 0x100>;
f8a073ee	109	interrupts = <17 4 0>;
cce783c6 HX	110	};
	111
	112	dma: dma-controller@ffffec00 {
	113	compatible = "atmel,at91sam9g45-dma";
	114	reg = <0xffffec00 0x200>;
f8a073ee	115	interrupts = <20 4 0>;
980ce7d9	116	#dma-cells = <2>;
cce783c6 HX	117	};
cce783c6 HX	118
e4541ff2 JCPV	119	pinctrl@fffff400 {
	120	#address-cells = <1>;
	121	#size-cells = <1>;
5314ec8e	122	compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
e4541ff2 JCPV	123	ranges = <0xfffff400 0xfffff400 0x800>;
e4541ff2 JCPV	124
5314ec8e JCPV	125	atmel,mux-mask = <
	126	/* A B C */
	127	0xffffffff 0xffe07983 0x00000000 /* pioA */
	128	0x00040000 0x00047e0f 0x00000000 /* pioB */
	129	0xfdffffff 0x07c00000 0xb83fffff /* pioC */
	130	0x003fffff 0x003f8000 0x00000000 /* pioD */
	131	>;
	132
	133	/* shared pinctrl settings */
ec6754a7 JCPV	134	dbgu {
	135	pinctrl_dbgu: dbgu-0 {
	136	atmel,pins =
	137	<0 9 0x1 0x0 /* PA9 periph A */
	138	0 10 0x1 0x1>; /* PA10 periph with pullup */
	139	};
	140	};
	141
9e3129e9 JCPV	142	usart0 {
9e3129e9 JCPV	143	pinctrl_usart0: usart0-0 {
ec6754a7 JCPV	144	atmel,pins =
	145	<0 1 0x1 0x1 /* PA1 periph A with pullup */
	146	0 0 0x1 0x0>; /* PA0 periph A */
	147	};
	148
c58c0c5a	149	pinctrl_usart0_rts: usart0_rts-0 {
ec6754a7	150	atmel,pins =
c58c0c5a JCPV	151	<0 2 0x1 0x0>; /* PA2 periph A */
	152	};
	153
	154	pinctrl_usart0_cts: usart0_cts-0 {
	155	atmel,pins =
	156	<0 3 0x1 0x0>; /* PA3 periph A */
ec6754a7 JCPV	157	};
	158	};
	159
9e3129e9 JCPV	160	usart1 {
9e3129e9 JCPV	161	pinctrl_usart1: usart1-0 {
ec6754a7 JCPV	162	atmel,pins =
	163	<0 6 0x1 0x1 /* PA6 periph A with pullup */
	164	0 5 0x1 0x0>; /* PA5 periph A */
	165	};
	166	};
	167
9e3129e9 JCPV	168	usart2 {
9e3129e9 JCPV	169	pinctrl_usart2: usart2-0 {
ec6754a7 JCPV	170	atmel,pins =
	171	<0 8 0x1 0x1 /* PA8 periph A with pullup */
	172	0 7 0x1 0x0>; /* PA7 periph A */
	173	};
	174
c58c0c5a	175	pinctrl_usart2_rts: usart2_rts-0 {
ec6754a7	176	atmel,pins =
c58c0c5a JCPV	177	<1 0 0x2 0x0>; /* PB0 periph B */
	178	};
	179
	180	pinctrl_usart2_cts: usart2_cts-0 {
	181	atmel,pins =
	182	<1 1 0x2 0x0>; /* PB1 periph B */
ec6754a7 JCPV	183	};
	184	};
	185
9e3129e9 JCPV	186	usart3 {
9e3129e9 JCPV	187	pinctrl_usart3: usart3-0 {
ec6754a7 JCPV	188	atmel,pins =
	189	<2 23 0x2 0x1 /* PC23 periph B with pullup */
	190	2 22 0x2 0x0>; /* PC22 periph B */
	191	};
	192
c58c0c5a JCPV	193	pinctrl_usart3_rts: usart3_rts-0 {
	194	atmel,pins =
	195	<2 24 0x2 0x0>; /* PC24 periph B */
	196	};
	197
	198	pinctrl_usart3_cts: usart3_cts-0 {
ec6754a7	199	atmel,pins =
c58c0c5a	200	<2 25 0x2 0x0>; /* PC25 periph B */
ec6754a7 JCPV	201	};
	202	};
	203
9e3129e9 JCPV	204	uart0 {
9e3129e9 JCPV	205	pinctrl_uart0: uart0-0 {
ec6754a7 JCPV	206	atmel,pins =
	207	<2 9 0x3 0x1 /* PC9 periph C with pullup */
	208	2 8 0x3 0x0>; /* PC8 periph C */
	209	};
	210	};
	211
9e3129e9 JCPV	212	uart1 {
9e3129e9 JCPV	213	pinctrl_uart1: uart1-0 {
ec6754a7 JCPV	214	atmel,pins =
	215	<2 16 0x3 0x1 /* PC17 periph C with pullup */
	216	2 17 0x3 0x0>; /* PC16 periph C */
	217	};
	218	};
5314ec8e	219
7a38d450 JCPV	220	nand {
	221	pinctrl_nand: nand-0 {
	222	atmel,pins =
	223	<3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
	224	3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
	225	};
	226	};
	227
d4fe9ac7 JCPV	228	mmc0 {
	229	pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
	230	atmel,pins =
	231	<0 17 0x1 0x0 /* PA17 periph A */
	232	0 16 0x1 0x1 /* PA16 periph A with pullup */
	233	0 15 0x1 0x1>; /* PA15 periph A with pullup */
	234	};
	235
	236	pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
	237	atmel,pins =
	238	<0 18 0x1 0x1 /* PA18 periph A with pullup */
	239	0 19 0x1 0x1 /* PA19 periph A with pullup */
	240	0 20 0x1 0x1>; /* PA20 periph A with pullup */
	241	};
	242
	243	pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
	244	atmel,pins =
	245	<0 11 0x2 0x1 /* PA11 periph B with pullup */
	246	0 12 0x2 0x1 /* PA12 periph B with pullup */
	247	0 13 0x2 0x1 /* PA13 periph B with pullup */
	248	0 14 0x2 0x1>; /* PA14 periph B with pullup */
	249	};
	250	};
	251
544ae6b2 BS	252	ssc0 {
	253	pinctrl_ssc0_tx: ssc0_tx-0 {
	254	atmel,pins =
	255	<0 24 0x2 0x0 /* PA24 periph B */
	256	0 25 0x2 0x0 /* PA25 periph B */
	257	0 26 0x2 0x0>; /* PA26 periph B */
	258	};
	259
	260	pinctrl_ssc0_rx: ssc0_rx-0 {
	261	atmel,pins =
	262	<0 27 0x2 0x0 /* PA27 periph B */
	263	0 28 0x2 0x0 /* PA28 periph B */
	264	0 29 0x2 0x0>; /* PA29 periph B */
	265	};
	266	};
	267
a68b728f WY	268	spi0 {
	269	pinctrl_spi0: spi0-0 {
	270	atmel,pins =
	271	<0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */
	272	0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */
	273	0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
	274	};
	275	};
	276
	277	spi1 {
	278	pinctrl_spi1: spi1-0 {
	279	atmel,pins =
	280	<0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */
	281	0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */
	282	0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
	283	};
	284	};
	285
e4541ff2 JCPV	286	pioA: gpio@fffff400 {
	287	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	288	reg = <0xfffff400 0x200>;
	289	interrupts = <2 4 1>;
	290	#gpio-cells = <2>;
	291	gpio-controller;
	292	interrupt-controller;
	293	#interrupt-cells = <2>;
	294	};
	295
	296	pioB: gpio@fffff600 {
	297	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	298	reg = <0xfffff600 0x200>;
	299	interrupts = <2 4 1>;
	300	#gpio-cells = <2>;
	301	gpio-controller;
	302	interrupt-controller;
	303	#interrupt-cells = <2>;
	304	};
	305
	306	pioC: gpio@fffff800 {
	307	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	308	reg = <0xfffff800 0x200>;
	309	interrupts = <3 4 1>;
	310	#gpio-cells = <2>;
	311	gpio-controller;
	312	interrupt-controller;
	313	#interrupt-cells = <2>;
	314	};
	315
	316	pioD: gpio@fffffa00 {
	317	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	318	reg = <0xfffffa00 0x200>;
	319	interrupts = <3 4 1>;
	320	#gpio-cells = <2>;
	321	gpio-controller;
	322	interrupt-controller;
	323	#interrupt-cells = <2>;
	324	};
cce783c6 HX	325	};
	326
	327	dbgu: serial@fffff200 {
	328	compatible = "atmel,at91sam9260-usart";
	329	reg = <0xfffff200 0x200>;
f8a073ee	330	interrupts = <1 4 7>;
ec6754a7 JCPV	331	pinctrl-names = "default";
ec6754a7 JCPV	332	pinctrl-0 = <&pinctrl_dbgu>;
cce783c6 HX	333	status = "disabled";
	334	};
	335
544ae6b2 BS	336	ssc0: ssc@f0010000 {
	337	compatible = "atmel,at91sam9g45-ssc";
	338	reg = <0xf0010000 0x4000>;
	339	interrupts = <28 4 5>;
	340	pinctrl-names = "default";
	341	pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
	342	status = "disabled";
	343	};
	344
cce783c6 HX	345	usart0: serial@f801c000 {
	346	compatible = "atmel,at91sam9260-usart";
	347	reg = <0xf801c000 0x4000>;
f8a073ee	348	interrupts = <5 4 5>;
ec6754a7	349	pinctrl-names = "default";
9e3129e9	350	pinctrl-0 = <&pinctrl_usart0>;
cce783c6 HX	351	status = "disabled";
	352	};
	353
	354	usart1: serial@f8020000 {
	355	compatible = "atmel,at91sam9260-usart";
	356	reg = <0xf8020000 0x4000>;
f8a073ee	357	interrupts = <6 4 5>;
ec6754a7	358	pinctrl-names = "default";
9e3129e9	359	pinctrl-0 = <&pinctrl_usart1>;
cce783c6 HX	360	status = "disabled";
	361	};
	362
	363	usart2: serial@f8024000 {
	364	compatible = "atmel,at91sam9260-usart";
	365	reg = <0xf8024000 0x4000>;
f8a073ee	366	interrupts = <7 4 5>;
ec6754a7	367	pinctrl-names = "default";
9e3129e9	368	pinctrl-0 = <&pinctrl_usart2>;
cce783c6 HX	369	status = "disabled";
	370	};
	371
	372	usart3: serial@f8028000 {
	373	compatible = "atmel,at91sam9260-usart";
	374	reg = <0xf8028000 0x4000>;
f8a073ee	375	interrupts = <8 4 5>;
ec6754a7	376	pinctrl-names = "default";
9e3129e9	377	pinctrl-0 = <&pinctrl_usart3>;
cce783c6 HX	378	status = "disabled";
cce783c6 HX	379	};
05dcd361 LD	380
	381	i2c0: i2c@f8010000 {
	382	compatible = "atmel,at91sam9x5-i2c";
	383	reg = <0xf8010000 0x100>;
	384	interrupts = <9 4 6>;
d9a63a45 LD	385	dmas = <&dma 1 13>,
	386	<&dma 1 14>;
	387	dma-names = "tx", "rx";
05dcd361 LD	388	#address-cells = <1>;
	389	#size-cells = <0>;
	390	status = "disabled";
	391	};
	392
	393	i2c1: i2c@f8014000 {
	394	compatible = "atmel,at91sam9x5-i2c";
	395	reg = <0xf8014000 0x100>;
	396	interrupts = <10 4 6>;
d9a63a45 LD	397	dmas = <&dma 1 15>,
	398	<&dma 1 16>;
	399	dma-names = "tx", "rx";
05dcd361 LD	400	#address-cells = <1>;
	401	#size-cells = <0>;
	402	status = "disabled";
	403	};
d50f88a0 RG	404
	405	spi0: spi@f0000000 {
	406	#address-cells = <1>;
	407	#size-cells = <0>;
	408	compatible = "atmel,at91rm9200-spi";
	409	reg = <0xf0000000 0x100>;
	410	interrupts = <13 4 3>;
a68b728f WY	411	pinctrl-names = "default";
a68b728f WY	412	pinctrl-0 = <&pinctrl_spi0>;
d50f88a0 RG	413	status = "disabled";
	414	};
	415
	416	spi1: spi@f0004000 {
	417	#address-cells = <1>;
	418	#size-cells = <0>;
	419	compatible = "atmel,at91rm9200-spi";
	420	reg = <0xf0004000 0x100>;
	421	interrupts = <14 4 3>;
a68b728f WY	422	pinctrl-names = "default";
a68b728f WY	423	pinctrl-0 = <&pinctrl_spi1>;
d50f88a0 RG	424	status = "disabled";
d50f88a0 RG	425	};
cce783c6 HX	426	};
	427
	428	nand0: nand@40000000 {
	429	compatible = "atmel,at91rm9200-nand";
	430	#address-cells = <1>;
	431	#size-cells = <1>;
	432	reg = < 0x40000000 0x10000000
	433	0xffffe000 0x00000600
	434	0xffffe600 0x00000200
c18c6b29	435	0x00108000 0x00018000
cce783c6	436	>;
c18c6b29	437	atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
cce783c6 HX	438	atmel,nand-addr-offset = <21>;
cce783c6 HX	439	atmel,nand-cmd-offset = <22>;
7a38d450 JCPV	440	pinctrl-names = "default";
7a38d450 JCPV	441	pinctrl-0 = <&pinctrl_nand>;
cce783c6 HX	442	gpios = <&pioD 5 0
	443	&pioD 4 0
	444	0
	445	>;
	446	status = "disabled";
	447	};
	448
	449	usb0: ohci@00500000 {
	450	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
	451	reg = <0x00500000 0x00100000>;
f8a073ee	452	interrupts = <22 4 2>;
cce783c6 HX	453	status = "disabled";
	454	};
	455	};
	456
	457	i2c@0 {
	458	compatible = "i2c-gpio";
	459	gpios = <&pioA 30 0 /* sda */
	460	&pioA 31 0 /* scl */
	461	>;
	462	i2c-gpio,sda-open-drain;
	463	i2c-gpio,scl-open-drain;
	464	i2c-gpio,delay-us = <2>; /* ~100 kHz */
	465	#address-cells = <1>;
	466	#size-cells = <0>;
	467	status = "disabled";
	468	};
	469	};