ARM: dts: mvebu: Convert all the mvebu files to use the range property
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / boot / dts / armada-xp-openblocks-ax3-4.dts
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1/*
2 * Device Tree file for OpenBlocks AX3-4 board
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13/dts-v1/;
14/include/ "armada-xp-mv78260.dtsi"
15
16/ {
17 model = "PlatHome OpenBlocks AX3-4 board";
18 compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
19
20 chosen {
21 bootargs = "console=ttyS0,115200 earlyprintk";
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x00000000 0xC0000000>; /* 3 GB */
27 };
28
29 soc {
82a68267 30 serial@12000 {
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31 clock-frequency = <250000000>;
32 status = "okay";
33 };
82a68267 34 serial@12100 {
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35 clock-frequency = <250000000>;
36 status = "okay";
37 };
38 pinctrl {
39 led_pins: led-pins-0 {
40 marvell,pins = "mpp49", "mpp51", "mpp53";
41 marvell,function = "gpio";
42 };
43 };
44 leds {
45 compatible = "gpio-leds";
46 pinctrl-names = "default";
47 pinctrl-0 = <&led_pins>;
48
49 red_led {
50 label = "red_led";
51 gpios = <&gpio1 17 1>;
52 default-state = "off";
53 };
54
55 yellow_led {
56 label = "yellow_led";
57 gpios = <&gpio1 19 1>;
58 default-state = "off";
59 };
60
61 green_led {
62 label = "green_led";
63 gpios = <&gpio1 21 1>;
64 default-state = "off";
65 linux,default-trigger = "heartbeat";
66 };
67 };
f69c92f4 68
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69 gpio_keys {
70 compatible = "gpio-keys";
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 button@1 {
75 label = "Init Button";
76 linux,code = <116>;
77 gpios = <&gpio1 28 0>;
78 };
79 };
80
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81 mdio {
82 phy0: ethernet-phy@0 {
83 reg = <0>;
84 };
85
86 phy1: ethernet-phy@1 {
87 reg = <1>;
88 };
89
90 phy2: ethernet-phy@2 {
91 reg = <2>;
92 };
93
94 phy3: ethernet-phy@3 {
95 reg = <3>;
96 };
97 };
98
82a68267 99 ethernet@70000 {
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100 status = "okay";
101 phy = <&phy0>;
102 phy-mode = "sgmii";
103 };
82a68267 104 ethernet@74000 {
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105 status = "okay";
106 phy = <&phy1>;
107 phy-mode = "sgmii";
108 };
82a68267 109 ethernet@30000 {
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110 status = "okay";
111 phy = <&phy2>;
112 phy-mode = "sgmii";
113 };
82a68267 114 ethernet@34000 {
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115 status = "okay";
116 phy = <&phy3>;
117 phy-mode = "sgmii";
118 };
82a68267 119 i2c@11000 {
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120 status = "okay";
121 clock-frequency = <400000>;
122 };
82a68267 123 i2c@11100 {
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124 status = "okay";
125 clock-frequency = <400000>;
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126
127 s35390a: s35390a@30 {
128 compatible = "s35390a";
129 reg = <0x30>;
130 };
9eab21cf 131 };
82a68267 132 sata@a0000 {
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133 nr-ports = <2>;
134 status = "okay";
135 };
82a68267 136 usb@50000 {
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137 status = "okay";
138 };
82a68267 139 usb@51000 {
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140 status = "okay";
141 };
a7d4f818 142
82a68267 143 devbus-bootcs@10400 {
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144 status = "okay";
145 ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
146
147 /* Device Bus parameters are required */
148
149 /* Read parameters */
150 devbus,bus-width = <8>;
151 devbus,turn-off-ps = <60000>;
152 devbus,badr-skew-ps = <0>;
153 devbus,acc-first-ps = <124000>;
154 devbus,acc-next-ps = <248000>;
155 devbus,rd-setup-ps = <0>;
156 devbus,rd-hold-ps = <0>;
157
158 /* Write parameters */
159 devbus,sync-enable = <0>;
160 devbus,wr-high-ps = <60000>;
161 devbus,wr-low-ps = <60000>;
162 devbus,ale-wr-ps = <60000>;
163
164 /* NOR 128 MiB */
165 nor@0 {
166 compatible = "cfi-flash";
167 reg = <0 0x8000000>;
168 bank-width = <2>;
169 };
170 };
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171
172 pcie-controller {
173 status = "okay";
174 /* Internal mini-PCIe connector */
175 pcie@1,0 {
176 /* Port 0, Lane 0 */
177 status = "okay";
178 };
179 };
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180 };
181};