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1 | /* |
2 | * Device Tree Include file for Marvell Armada XP family SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | * | |
12 | * Contains definitions specific to the Armada XP MV78230 SoC that are not | |
13 | * common to all Armada XP SoCs. | |
14 | */ | |
15 | ||
16 | /include/ "armada-xp.dtsi" | |
17 | ||
18 | / { | |
19 | model = "Marvell Armada XP MV78230 SoC"; | |
20 | compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; | |
21 | ||
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22 | aliases { |
23 | gpio0 = &gpio0; | |
24 | gpio1 = &gpio1; | |
25 | }; | |
26 | ||
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27 | cpus { |
28 | #address-cells = <1>; | |
29 | #size-cells = <0>; | |
30 | ||
31 | cpu@0 { | |
32 | device_type = "cpu"; | |
33 | compatible = "marvell,sheeva-v7"; | |
34 | reg = <0>; | |
35 | clocks = <&cpuclk 0>; | |
36 | }; | |
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37 | |
38 | cpu@1 { | |
39 | device_type = "cpu"; | |
40 | compatible = "marvell,sheeva-v7"; | |
41 | reg = <1>; | |
42 | clocks = <&cpuclk 1>; | |
43 | }; | |
41be8dc1 | 44 | }; |
9d202783 | 45 | |
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46 | soc { |
47 | pinctrl { | |
48 | compatible = "marvell,mv78230-pinctrl"; | |
49 | reg = <0xd0018000 0x38>; | |
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50 | |
51 | sdio_pins: sdio-pins { | |
52 | marvell,pins = "mpp30", "mpp31", "mpp32", | |
53 | "mpp33", "mpp34", "mpp35"; | |
54 | marvell,function = "sd0"; | |
55 | }; | |
f3b42b7c | 56 | }; |
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57 | |
58 | gpio0: gpio@d0018100 { | |
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59 | compatible = "marvell,orion-gpio"; |
60 | reg = <0xd0018100 0x40>; | |
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61 | ngpios = <32>; |
62 | gpio-controller; | |
63 | #gpio-cells = <2>; | |
64 | interrupt-controller; | |
65 | #interrupts-cells = <2>; | |
5f79c651 | 66 | interrupts = <82>, <83>, <84>, <85>; |
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67 | }; |
68 | ||
69 | gpio1: gpio@d0018140 { | |
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70 | compatible = "marvell,orion-gpio"; |
71 | reg = <0xd0018140 0x40>; | |
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72 | ngpios = <17>; |
73 | gpio-controller; | |
74 | #gpio-cells = <2>; | |
75 | interrupt-controller; | |
76 | #interrupts-cells = <2>; | |
5f79c651 | 77 | interrupts = <87>, <88>, <89>; |
397d59f3 | 78 | }; |
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79 | |
80 | /* | |
81 | * MV78230 has 2 PCIe units Gen2.0: One unit can be | |
82 | * configured as x4 or quad x1 lanes. One unit is | |
83 | * x4/x1. | |
84 | */ | |
85 | pcie-controller { | |
86 | compatible = "marvell,armada-xp-pcie"; | |
87 | status = "disabled"; | |
88 | device_type = "pci"; | |
89 | ||
90 | #address-cells = <3>; | |
91 | #size-cells = <2>; | |
92 | ||
93 | bus-range = <0x00 0xff>; | |
94 | ||
95 | ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ | |
96 | 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ | |
97 | 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ | |
98 | 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ | |
99 | 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ | |
100 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | |
101 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | |
102 | ||
103 | pcie@1,0 { | |
104 | device_type = "pci"; | |
105 | assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; | |
106 | reg = <0x0800 0 0 0 0>; | |
107 | #address-cells = <3>; | |
108 | #size-cells = <2>; | |
109 | #interrupt-cells = <1>; | |
110 | ranges; | |
111 | interrupt-map-mask = <0 0 0 0>; | |
112 | interrupt-map = <0 0 0 0 &mpic 58>; | |
113 | marvell,pcie-port = <0>; | |
114 | marvell,pcie-lane = <0>; | |
115 | clocks = <&gateclk 5>; | |
116 | status = "disabled"; | |
117 | }; | |
118 | ||
119 | pcie@2,0 { | |
120 | device_type = "pci"; | |
121 | assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>; | |
122 | reg = <0x1000 0 0 0 0>; | |
123 | #address-cells = <3>; | |
124 | #size-cells = <2>; | |
125 | #interrupt-cells = <1>; | |
126 | ranges; | |
127 | interrupt-map-mask = <0 0 0 0>; | |
128 | interrupt-map = <0 0 0 0 &mpic 59>; | |
129 | marvell,pcie-port = <0>; | |
130 | marvell,pcie-lane = <1>; | |
131 | clocks = <&gateclk 6>; | |
132 | status = "disabled"; | |
133 | }; | |
134 | ||
135 | pcie@3,0 { | |
136 | device_type = "pci"; | |
137 | assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>; | |
138 | reg = <0x1800 0 0 0 0>; | |
139 | #address-cells = <3>; | |
140 | #size-cells = <2>; | |
141 | #interrupt-cells = <1>; | |
142 | ranges; | |
143 | interrupt-map-mask = <0 0 0 0>; | |
144 | interrupt-map = <0 0 0 0 &mpic 60>; | |
145 | marvell,pcie-port = <0>; | |
146 | marvell,pcie-lane = <2>; | |
147 | clocks = <&gateclk 7>; | |
148 | status = "disabled"; | |
149 | }; | |
150 | ||
151 | pcie@4,0 { | |
152 | device_type = "pci"; | |
153 | assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>; | |
154 | reg = <0x2000 0 0 0 0>; | |
155 | #address-cells = <3>; | |
156 | #size-cells = <2>; | |
157 | #interrupt-cells = <1>; | |
158 | ranges; | |
159 | interrupt-map-mask = <0 0 0 0>; | |
160 | interrupt-map = <0 0 0 0 &mpic 61>; | |
161 | marvell,pcie-port = <0>; | |
162 | marvell,pcie-lane = <3>; | |
163 | clocks = <&gateclk 8>; | |
164 | status = "disabled"; | |
165 | }; | |
166 | ||
167 | pcie@9,0 { | |
168 | device_type = "pci"; | |
169 | assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>; | |
170 | reg = <0x4800 0 0 0 0>; | |
171 | #address-cells = <3>; | |
172 | #size-cells = <2>; | |
173 | #interrupt-cells = <1>; | |
174 | ranges; | |
175 | interrupt-map-mask = <0 0 0 0>; | |
176 | interrupt-map = <0 0 0 0 &mpic 99>; | |
177 | marvell,pcie-port = <2>; | |
178 | marvell,pcie-lane = <0>; | |
179 | clocks = <&gateclk 26>; | |
180 | status = "disabled"; | |
181 | }; | |
182 | }; | |
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183 | }; |
184 | }; |