[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / boot / compressed / head-xscale.S

/*
 * linux/arch/arm/boot/compressed/head-xscale.S
 *
 * XScale specific tweaks.  This is merged into head.S by the linker.
 *
 */

#include <linux/linkage.h>
#include <asm/mach-types.h>

		.section        ".start", "ax"

__XScale_start:

		@ Preserve r8/r7 i.e. kernel entry values

		@ Data cache might be active.
		@ Be sure to flush kernel binary out of the cache,
		@ whatever state it is, before it is turned off.
		@ This is done by fetching through currently executed
		@ memory to be sure we hit the same cache.
		bic	r2, pc, #0x1f
		add	r3, r2, #0x10000	@ 64 kb is quite enough...
1:		ldr	r0, [r2], #32
		teq	r2, r3
		bne	1b
		mcr	p15, 0, r0, c7, c10, 4	@ drain WB
		mcr	p15, 0, r0, c7, c7, 0	@ flush I & D caches

		@ disabling MMU and caches
		mrc	p15, 0, r0, c1, c0, 0	@ read control reg
		bic	r0, r0, #0x05		@ clear DC, MMU
		bic	r0, r0, #0x1000		@ clear Icache
		mcr	p15, 0, r0, c1, c0, 0

#ifdef CONFIG_ARCH_IXP2000
		mov	r1, #-1
		mov	r0, #0xd6000000
		str	r1, [r0, #0x14]
		str	r1, [r0, #0x18]
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/boot/compressed/head-xscale.S
	3	*
	4	* XScale specific tweaks. This is merged into head.S by the linker.
	5	*
	6	*/
	7
1da177e4 LT	8	#include <linux/linkage.h>
	9	#include <asm/mach-types.h>
	10
	11	.section ".start", "ax"
	12
	13	__XScale_start:
	14
	15	@ Preserve r8/r7 i.e. kernel entry values
	16
	17	@ Data cache might be active.
	18	@ Be sure to flush kernel binary out of the cache,
	19	@ whatever state it is, before it is turned off.
	20	@ This is done by fetching through currently executed
	21	@ memory to be sure we hit the same cache.
	22	bic r2, pc, #0x1f
	23	add r3, r2, #0x10000 @ 64 kb is quite enough...
	24	1: ldr r0, [r2], #32
	25	teq r2, r3
	26	bne 1b
	27	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	28	mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
	29
	30	@ disabling MMU and caches
	31	mrc p15, 0, r0, c1, c0, 0 @ read control reg
	32	bic r0, r0, #0x05 @ clear DC, MMU
	33	bic r0, r0, #0x1000 @ clear Icache
	34	mcr p15, 0, r0, c1, c0, 0
	35
17d82fcc DS	36	#ifdef CONFIG_ARCH_IXP2000
	37	mov r1, #-1
	38	mov r0, #0xd6000000
	39	str r1, [r0, #0x14]
	40	str r1, [r0, #0x18]
	41	#endif
	42