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1162b070 VG |
1 | /* |
2 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef _ASM_ARC_IO_H | |
10 | #define _ASM_ARC_IO_H | |
11 | ||
12 | #include <linux/types.h> | |
13 | #include <asm/byteorder.h> | |
14 | #include <asm/page.h> | |
32f91e02 | 15 | #include <asm/unaligned.h> |
1162b070 | 16 | |
e5bc0478 VG |
17 | #ifdef CONFIG_ISA_ARCV2 |
18 | #include <asm/barrier.h> | |
19 | #define __iormb() rmb() | |
20 | #define __iowmb() wmb() | |
21 | #else | |
22 | #define __iormb() do { } while (0) | |
23 | #define __iowmb() do { } while (0) | |
24 | #endif | |
25 | ||
f5db19e9 VG |
26 | extern void __iomem *ioremap(phys_addr_t paddr, unsigned long size); |
27 | extern void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size, | |
4368902b | 28 | unsigned long flags); |
c1678ffc JP |
29 | static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) |
30 | { | |
31 | return (void __iomem *)port; | |
32 | } | |
33 | ||
34 | static inline void ioport_unmap(void __iomem *addr) | |
35 | { | |
36 | } | |
37 | ||
1162b070 VG |
38 | extern void iounmap(const void __iomem *addr); |
39 | ||
40 | #define ioremap_nocache(phy, sz) ioremap(phy, sz) | |
41 | #define ioremap_wc(phy, sz) ioremap(phy, sz) | |
556269c1 | 42 | #define ioremap_wt(phy, sz) ioremap(phy, sz) |
1162b070 | 43 | |
e5bc0478 VG |
44 | /* |
45 | * io{read,write}{16,32}be() macros | |
46 | */ | |
47 | #define ioread16be(p) ({ u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; }) | |
48 | #define ioread32be(p) ({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; }) | |
49 | ||
50 | #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); }) | |
51 | #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); }) | |
52 | ||
1162b070 VG |
53 | /* Change struct page to physical address */ |
54 | #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) | |
55 | ||
56 | #define __raw_readb __raw_readb | |
57 | static inline u8 __raw_readb(const volatile void __iomem *addr) | |
58 | { | |
59 | u8 b; | |
60 | ||
61 | __asm__ __volatile__( | |
62 | " ldb%U1 %0, %1 \n" | |
63 | : "=r" (b) | |
64 | : "m" (*(volatile u8 __force *)addr) | |
65 | : "memory"); | |
66 | ||
67 | return b; | |
68 | } | |
69 | ||
70 | #define __raw_readw __raw_readw | |
71 | static inline u16 __raw_readw(const volatile void __iomem *addr) | |
72 | { | |
73 | u16 s; | |
74 | ||
75 | __asm__ __volatile__( | |
76 | " ldw%U1 %0, %1 \n" | |
77 | : "=r" (s) | |
78 | : "m" (*(volatile u16 __force *)addr) | |
79 | : "memory"); | |
80 | ||
81 | return s; | |
82 | } | |
83 | ||
84 | #define __raw_readl __raw_readl | |
85 | static inline u32 __raw_readl(const volatile void __iomem *addr) | |
86 | { | |
87 | u32 w; | |
88 | ||
89 | __asm__ __volatile__( | |
90 | " ld%U1 %0, %1 \n" | |
91 | : "=r" (w) | |
92 | : "m" (*(volatile u32 __force *)addr) | |
93 | : "memory"); | |
94 | ||
95 | return w; | |
96 | } | |
97 | ||
32f91e02 JA |
98 | /* |
99 | * {read,write}s{b,w,l}() repeatedly access the same IO address in | |
100 | * native endianness in 8-, 16-, 32-bit chunks {into,from} memory, | |
101 | * @count times | |
102 | */ | |
103 | #define __raw_readsx(t,f) \ | |
104 | static inline void __raw_reads##f(const volatile void __iomem *addr, \ | |
105 | void *ptr, unsigned int count) \ | |
106 | { \ | |
107 | bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0; \ | |
108 | u##t *buf = ptr; \ | |
109 | \ | |
110 | if (!count) \ | |
111 | return; \ | |
112 | \ | |
113 | /* Some ARC CPU's don't support unaligned accesses */ \ | |
114 | if (is_aligned) { \ | |
115 | do { \ | |
116 | u##t x = __raw_read##f(addr); \ | |
117 | *buf++ = x; \ | |
118 | } while (--count); \ | |
119 | } else { \ | |
120 | do { \ | |
121 | u##t x = __raw_read##f(addr); \ | |
122 | put_unaligned(x, buf++); \ | |
123 | } while (--count); \ | |
124 | } \ | |
125 | } | |
126 | ||
127 | #define __raw_readsb __raw_readsb | |
128 | __raw_readsx(8, b) | |
129 | #define __raw_readsw __raw_readsw | |
130 | __raw_readsx(16, w) | |
131 | #define __raw_readsl __raw_readsl | |
132 | __raw_readsx(32, l) | |
133 | ||
1162b070 VG |
134 | #define __raw_writeb __raw_writeb |
135 | static inline void __raw_writeb(u8 b, volatile void __iomem *addr) | |
136 | { | |
137 | __asm__ __volatile__( | |
138 | " stb%U1 %0, %1 \n" | |
139 | : | |
140 | : "r" (b), "m" (*(volatile u8 __force *)addr) | |
141 | : "memory"); | |
142 | } | |
143 | ||
144 | #define __raw_writew __raw_writew | |
145 | static inline void __raw_writew(u16 s, volatile void __iomem *addr) | |
146 | { | |
147 | __asm__ __volatile__( | |
148 | " stw%U1 %0, %1 \n" | |
149 | : | |
150 | : "r" (s), "m" (*(volatile u16 __force *)addr) | |
151 | : "memory"); | |
152 | ||
153 | } | |
154 | ||
155 | #define __raw_writel __raw_writel | |
156 | static inline void __raw_writel(u32 w, volatile void __iomem *addr) | |
157 | { | |
158 | __asm__ __volatile__( | |
159 | " st%U1 %0, %1 \n" | |
160 | : | |
161 | : "r" (w), "m" (*(volatile u32 __force *)addr) | |
162 | : "memory"); | |
163 | ||
164 | } | |
165 | ||
32f91e02 JA |
166 | #define __raw_writesx(t,f) \ |
167 | static inline void __raw_writes##f(volatile void __iomem *addr, \ | |
168 | const void *ptr, unsigned int count) \ | |
169 | { \ | |
170 | bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0; \ | |
171 | const u##t *buf = ptr; \ | |
172 | \ | |
173 | if (!count) \ | |
174 | return; \ | |
175 | \ | |
176 | /* Some ARC CPU's don't support unaligned accesses */ \ | |
177 | if (is_aligned) { \ | |
178 | do { \ | |
179 | __raw_write##f(*buf++, addr); \ | |
180 | } while (--count); \ | |
181 | } else { \ | |
182 | do { \ | |
183 | __raw_write##f(get_unaligned(buf++), addr); \ | |
184 | } while (--count); \ | |
185 | } \ | |
186 | } | |
187 | ||
188 | #define __raw_writesb __raw_writesb | |
189 | __raw_writesx(8, b) | |
190 | #define __raw_writesw __raw_writesw | |
191 | __raw_writesx(16, w) | |
192 | #define __raw_writesl __raw_writesl | |
193 | __raw_writesx(32, l) | |
194 | ||
b8a03302 VG |
195 | /* |
196 | * MMIO can also get buffered/optimized in micro-arch, so barriers needed | |
197 | * Based on ARM model for the typical use case | |
198 | * | |
199 | * <ST [DMA buffer]> | |
200 | * <writel MMIO "go" reg> | |
201 | * or: | |
202 | * <readl MMIO "status" reg> | |
203 | * <LD [DMA buffer]> | |
204 | * | |
205 | * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com | |
206 | */ | |
207 | #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) | |
208 | #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) | |
209 | #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) | |
32f91e02 JA |
210 | #define readsb(p,d,l) ({ __raw_readsb(p,d,l); __iormb(); }) |
211 | #define readsw(p,d,l) ({ __raw_readsw(p,d,l); __iormb(); }) | |
212 | #define readsl(p,d,l) ({ __raw_readsl(p,d,l); __iormb(); }) | |
b8a03302 VG |
213 | |
214 | #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) | |
215 | #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) | |
216 | #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) | |
32f91e02 JA |
217 | #define writesb(p,d,l) ({ __iowmb(); __raw_writesb(p,d,l); }) |
218 | #define writesw(p,d,l) ({ __iowmb(); __raw_writesw(p,d,l); }) | |
219 | #define writesl(p,d,l) ({ __iowmb(); __raw_writesl(p,d,l); }) | |
b8a03302 VG |
220 | |
221 | /* | |
f778cc65 LT |
222 | * Relaxed API for drivers which can handle barrier ordering themselves |
223 | * | |
224 | * Also these are defined to perform little endian accesses. | |
225 | * To provide the typical device register semantics of fixed endian, | |
226 | * swap the byte order for Big Endian | |
227 | * | |
228 | * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de | |
b8a03302 VG |
229 | */ |
230 | #define readb_relaxed(c) __raw_readb(c) | |
f778cc65 LT |
231 | #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ |
232 | __raw_readw(c)); __r; }) | |
233 | #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ | |
234 | __raw_readl(c)); __r; }) | |
b8a03302 VG |
235 | |
236 | #define writeb_relaxed(v,c) __raw_writeb(v,c) | |
f778cc65 LT |
237 | #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) |
238 | #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) | |
6532b02f | 239 | |
1162b070 VG |
240 | #include <asm-generic/io.h> |
241 | ||
242 | #endif /* _ASM_ARC_IO_H */ |