[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / alpha / kernel / sys_dp264.c

/*
 *	linux/arch/alpha/kernel/sys_dp264.c
 *
 *	Copyright (C) 1995 David A Rusling
 *	Copyright (C) 1996, 1999 Jay A Estabrook
 *	Copyright (C) 1998, 1999 Richard Henderson
 *
 *	Modified by Christopher C. Chimelis, 2001 to
 *	add support for the addition of Shark to the
 *	Tsunami family.
 *
 * Code supporting the DP264 (EV6+TSUNAMI).
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/bitops.h>

#include <asm/ptrace.h>
#include <asm/dma.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/core_tsunami.h>
#include <asm/hwrpb.h>
#include <asm/tlbflush.h>

#include "proto.h"
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"


/* Note mask bit is true for ENABLED irqs.  */
static unsigned long cached_irq_mask;
/* dp264 boards handle at max four CPUs */
static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL };

DEFINE_SPINLOCK(dp264_irq_lock);

static void
tsunami_update_irq_hw(unsigned long mask)
{
	register tsunami_cchip *cchip = TSUNAMI_cchip;
	unsigned long isa_enable = 1UL << 55;
	register int bcpu = boot_cpuid;

#ifdef CONFIG_SMP
	volatile unsigned long *dim0, *dim1, *dim2, *dim3;
	unsigned long mask0, mask1, mask2, mask3, dummy;

	mask &= ~isa_enable;
	mask0 = mask & cpu_irq_affinity[0];
	mask1 = mask & cpu_irq_affinity[1];
	mask2 = mask & cpu_irq_affinity[2];
	mask3 = mask & cpu_irq_affinity[3];

	if (bcpu == 0) mask0 |= isa_enable;
	else if (bcpu == 1) mask1 |= isa_enable;
	else if (bcpu == 2) mask2 |= isa_enable;
	else mask3 |= isa_enable;

	dim0 = &cchip->dim0.csr;
	dim1 = &cchip->dim1.csr;
	dim2 = &cchip->dim2.csr;
	dim3 = &cchip->dim3.csr;
	if (!cpu_possible(0)) dim0 = &dummy;
	if (!cpu_possible(1)) dim1 = &dummy;
	if (!cpu_possible(2)) dim2 = &dummy;
	if (!cpu_possible(3)) dim3 = &dummy;

	*dim0 = mask0;
	*dim1 = mask1;
	*dim2 = mask2;
	*dim3 = mask3;
	mb();
	*dim0;
	*dim1;
	*dim2;
	*dim3;
#else
	volatile unsigned long *dimB;
	if (bcpu == 0) dimB = &cchip->dim0.csr;
	else if (bcpu == 1) dimB = &cchip->dim1.csr;
	else if (bcpu == 2) dimB = &cchip->dim2.csr;
	else dimB = &cchip->dim3.csr;

	*dimB = mask | isa_enable;
	mb();
	*dimB;
#endif
}

static void
dp264_enable_irq(struct irq_data *d)
{
	spin_lock(&dp264_irq_lock);
	cached_irq_mask |= 1UL << d->irq;
	tsunami_update_irq_hw(cached_irq_mask);
	spin_unlock(&dp264_irq_lock);
}

static void
dp264_disable_irq(struct irq_data *d)
{
	spin_lock(&dp264_irq_lock);
	cached_irq_mask &= ~(1UL << d->irq);
	tsunami_update_irq_hw(cached_irq_mask);
	spin_unlock(&dp264_irq_lock);
}

static void
clipper_enable_irq(struct irq_data *d)
{
	spin_lock(&dp264_irq_lock);
	cached_irq_mask |= 1UL << (d->irq - 16);
	tsunami_update_irq_hw(cached_irq_mask);
	spin_unlock(&dp264_irq_lock);
}

static void
clipper_disable_irq(struct irq_data *d)
{
	spin_lock(&dp264_irq_lock);
	cached_irq_mask &= ~(1UL << (d->irq - 16));
	tsunami_update_irq_hw(cached_irq_mask);
	spin_unlock(&dp264_irq_lock);
}

static void
cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
{
	int cpu;

	for (cpu = 0; cpu < 4; cpu++) {
		unsigned long aff = cpu_irq_affinity[cpu];
		if (cpumask_test_cpu(cpu, &affinity))
			aff |= 1UL << irq;
		else
			aff &= ~(1UL << irq);
		cpu_irq_affinity[cpu] = aff;
	}
}

static int
dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity,
		   bool force)
{
	spin_lock(&dp264_irq_lock);
	cpu_set_irq_affinity(d->irq, *affinity);
	tsunami_update_irq_hw(cached_irq_mask);
	spin_unlock(&dp264_irq_lock);

	return 0;
}

static int
clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity,
		     bool force)
{
	spin_lock(&dp264_irq_lock);
	cpu_set_irq_affinity(d->irq - 16, *affinity);
	tsunami_update_irq_hw(cached_irq_mask);
	spin_unlock(&dp264_irq_lock);

	return 0;
}

static struct irq_chip dp264_irq_type = {
	.name			= "DP264",
	.irq_unmask		= dp264_enable_irq,
	.irq_mask		= dp264_disable_irq,
	.irq_mask_ack		= dp264_disable_irq,
	.irq_set_affinity	= dp264_set_affinity,
};

static struct irq_chip clipper_irq_type = {
	.name			= "CLIPPER",
	.irq_unmask		= clipper_enable_irq,
	.irq_mask		= clipper_disable_irq,
	.irq_mask_ack		= clipper_disable_irq,
	.irq_set_affinity	= clipper_set_affinity,
};

static void
dp264_device_interrupt(unsigned long vector)
{
#if 1
	printk("dp264_device_interrupt: NOT IMPLEMENTED YET!!\n");
#else
	unsigned long pld;
	unsigned int i;

	/* Read the interrupt summary register of TSUNAMI */
	pld = TSUNAMI_cchip->dir0.csr;

	/*
	 * Now for every possible bit set, work through them and call
	 * the appropriate interrupt handler.
	 */
	while (pld) {
		i = ffz(~pld);
		pld &= pld - 1; /* clear least bit set */
		if (i == 55)
			isa_device_interrupt(vector);
		else
			handle_irq(16 + i);
#if 0
		TSUNAMI_cchip->dir0.csr = 1UL << i; mb();
		tmp = TSUNAMI_cchip->dir0.csr;
#endif
	}
#endif
}

static void 
dp264_srm_device_interrupt(unsigned long vector)
{
	int irq;

	irq = (vector - 0x800) >> 4;

	/*
	 * The SRM console reports PCI interrupts with a vector calculated by:
	 *
	 *	0x900 + (0x10 * DRIR-bit)
	 *
	 * So bit 16 shows up as IRQ 32, etc.
	 * 
	 * On DP264/BRICK/MONET, we adjust it down by 16 because at least
	 * that many of the low order bits of the DRIR are not used, and
	 * so we don't count them.
	 */
	if (irq >= 32)
		irq -= 16;

	handle_irq(irq);
}

static void 
clipper_srm_device_interrupt(unsigned long vector)
{
	int irq;

	irq = (vector - 0x800) >> 4;

/*
	 * The SRM console reports PCI interrupts with a vector calculated by:
	 *
	 *	0x900 + (0x10 * DRIR-bit)
	 *
	 * So bit 16 shows up as IRQ 32, etc.
	 * 
	 * CLIPPER uses bits 8-47 for PCI interrupts, so we do not need
	 * to scale down the vector reported, we just use it.
	 *
	 * Eg IRQ 24 is DRIR bit 8, etc, etc
	 */
	handle_irq(irq);
}

static void __init
init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
{
	long i;
	for (i = imin; i <= imax; ++i) {
		irq_set_chip_and_handler(i, ops, handle_level_irq);
		irq_set_status_flags(i, IRQ_LEVEL);
	}
}

static void __init
dp264_init_irq(void)
{
	outb(0, DMA1_RESET_REG);
	outb(0, DMA2_RESET_REG);
	outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
	outb(0, DMA2_MASK_REG);

	if (alpha_using_srm)
		alpha_mv.device_interrupt = dp264_srm_device_interrupt;

	tsunami_update_irq_hw(0);

	init_i8259a_irqs();
	init_tsunami_irqs(&dp264_irq_type, 16, 47);
}

static void __init
clipper_init_irq(void)
{
	outb(0, DMA1_RESET_REG);
	outb(0, DMA2_RESET_REG);
	outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
	outb(0, DMA2_MASK_REG);

	if (alpha_using_srm)
		alpha_mv.device_interrupt = clipper_srm_device_interrupt;

	tsunami_update_irq_hw(0);

	init_i8259a_irqs();
	init_tsunami_irqs(&clipper_irq_type, 24, 63);
}


/*
 * PCI Fixup configuration.
 *
 * Summary @ TSUNAMI_CSR_DIM0:
 * Bit      Meaning
 * 0-17     Unused
 *18        Interrupt SCSI B (Adaptec 7895 builtin)
 *19        Interrupt SCSI A (Adaptec 7895 builtin)
 *20        Interrupt Line D from slot 2 PCI0
 *21        Interrupt Line C from slot 2 PCI0
 *22        Interrupt Line B from slot 2 PCI0
 *23        Interrupt Line A from slot 2 PCI0
 *24        Interrupt Line D from slot 1 PCI0
 *25        Interrupt Line C from slot 1 PCI0
 *26        Interrupt Line B from slot 1 PCI0
 *27        Interrupt Line A from slot 1 PCI0
 *28        Interrupt Line D from slot 0 PCI0
 *29        Interrupt Line C from slot 0 PCI0
 *30        Interrupt Line B from slot 0 PCI0
 *31        Interrupt Line A from slot 0 PCI0
 *
 *32        Interrupt Line D from slot 3 PCI1
 *33        Interrupt Line C from slot 3 PCI1
 *34        Interrupt Line B from slot 3 PCI1
 *35        Interrupt Line A from slot 3 PCI1
 *36        Interrupt Line D from slot 2 PCI1
 *37        Interrupt Line C from slot 2 PCI1
 *38        Interrupt Line B from slot 2 PCI1
 *39        Interrupt Line A from slot 2 PCI1
 *40        Interrupt Line D from slot 1 PCI1
 *41        Interrupt Line C from slot 1 PCI1
 *42        Interrupt Line B from slot 1 PCI1
 *43        Interrupt Line A from slot 1 PCI1
 *44        Interrupt Line D from slot 0 PCI1
 *45        Interrupt Line C from slot 0 PCI1
 *46        Interrupt Line B from slot 0 PCI1
 *47        Interrupt Line A from slot 0 PCI1
 *48-52     Unused
 *53        PCI0 NMI (from Cypress)
 *54        PCI0 SMI INT (from Cypress)
 *55        PCI0 ISA Interrupt (from Cypress)
 *56-60     Unused
 *61        PCI1 Bus Error
 *62        PCI0 Bus Error
 *63        Reserved
 *
 * IdSel	
 *   5	 Cypress Bridge I/O
 *   6	 SCSI Adaptec builtin
 *   7	 64 bit PCI option slot 0 (all busses)
 *   8	 64 bit PCI option slot 1 (all busses)
 *   9	 64 bit PCI option slot 2 (all busses)
 *  10	 64 bit PCI option slot 3 (not bus 0)
 */

static int __init
isa_irq_fixup(const struct pci_dev *dev, int irq)
{
	u8 irq8;

	if (irq > 0)
		return irq;

	/* This interrupt is routed via ISA bridge, so we'll
	   just have to trust whatever value the console might
	   have assigned.  */
	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);

	return irq8 & 0xf;
}

static int __init
dp264_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	static char irq_tab[6][5] __initdata = {
		/*INT    INTA   INTB   INTC   INTD */
		{    -1,    -1,    -1,    -1,    -1}, /* IdSel 5 ISA Bridge */
		{ 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/
		{ 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */
		{ 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */
		{ 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */
		{ 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0}  /* IdSel 10 slot 3 */
	};
	const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
	struct pci_controller *hose = dev->sysdata;
	int irq = COMMON_TABLE_LOOKUP;

	if (irq > 0)
		irq += 16 * hose->index;

	return isa_irq_fixup(dev, irq);
}

static int __init
monet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	static char irq_tab[13][5] __initdata = {
		/*INT    INTA   INTB   INTC   INTD */
		{    45,    45,    45,    45,    45}, /* IdSel 3 21143 PCI1 */
		{    -1,    -1,    -1,    -1,    -1}, /* IdSel 4 unused */
		{    -1,    -1,    -1,    -1,    -1}, /* IdSel 5 unused */
		{    47,    47,    47,    47,    47}, /* IdSel 6 SCSI PCI1 */
		{    -1,    -1,    -1,    -1,    -1}, /* IdSel 7 ISA Bridge */
		{    -1,    -1,    -1,    -1,    -1}, /* IdSel 8 P2P PCI1 */
#if 1
		{    28,    28,    29,    30,    31}, /* IdSel 14 slot 4 PCI2*/
		{    24,    24,    25,    26,    27}, /* IdSel 15 slot 5 PCI2*/
#else
		{    -1,    -1,    -1,    -1,    -1}, /* IdSel 9 unused */
		{    -1,    -1,    -1,    -1,    -1}, /* IdSel 10 unused */
#endif
		{    40,    40,    41,    42,    43}, /* IdSel 11 slot 1 PCI0*/
		{    36,    36,    37,    38,    39}, /* IdSel 12 slot 2 PCI0*/
		{    32,    32,    33,    34,    35}, /* IdSel 13 slot 3 PCI0*/
		{    28,    28,    29,    30,    31}, /* IdSel 14 slot 4 PCI2*/
		{    24,    24,    25,    26,    27}  /* IdSel 15 slot 5 PCI2*/
	};
	const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;

	return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
}

static u8 __init
monet_swizzle(struct pci_dev *dev, u8 *pinp)
{
	struct pci_controller *hose = dev->sysdata;
	int slot, pin = *pinp;

	if (!dev->bus->parent) {
		slot = PCI_SLOT(dev->devfn);
	}
	/* Check for the built-in bridge on hose 1. */
	else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) {
		slot = PCI_SLOT(dev->devfn);
	} else {
		/* Must be a card-based bridge.  */
		do {
			/* Check for built-in bridge on hose 1. */
			if (hose->index == 1 &&
			    PCI_SLOT(dev->bus->self->devfn) == 8) {
				slot = PCI_SLOT(dev->devfn);
				break;
			}
			pin = pci_swizzle_interrupt_pin(dev, pin);

			/* Move up the chain of bridges.  */
			dev = dev->bus->self;
			/* Slot of the next bridge.  */
			slot = PCI_SLOT(dev->devfn);
		} while (dev->bus->self);
	}
	*pinp = pin;
	return slot;
}

static int __init
webbrick_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	static char irq_tab[13][5] __initdata = {
		/*INT    INTA   INTB   INTC   INTD */
		{    -1,    -1,    -1,    -1,    -1}, /* IdSel 7 ISA Bridge */
		{    -1,    -1,    -1,    -1,    -1}, /* IdSel 8 unused */
		{    29,    29,    29,    29,    29}, /* IdSel 9 21143 #1 */
		{    -1,    -1,    -1,    -1,    -1}, /* IdSel 10 unused */
		{    30,    30,    30,    30,    30}, /* IdSel 11 21143 #2 */
		{    -1,    -1,    -1,    -1,    -1}, /* IdSel 12 unused */
		{    -1,    -1,    -1,    -1,    -1}, /* IdSel 13 unused */
		{    35,    35,    34,    33,    32}, /* IdSel 14 slot 0 */
		{    39,    39,    38,    37,    36}, /* IdSel 15 slot 1 */
		{    43,    43,    42,    41,    40}, /* IdSel 16 slot 2 */
		{    47,    47,    46,    45,    44}, /* IdSel 17 slot 3 */
	};
	const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;

	return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
}

static int __init
clipper_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	static char irq_tab[7][5] __initdata = {
		/*INT    INTA   INTB   INTC   INTD */
		{ 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */
		{ 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */
		{ 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */
		{ 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */
		{ 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */
		{ 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */
		{    -1,    -1,    -1,    -1,    -1}  /* IdSel 7 ISA Bridge */
	};
	const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
	struct pci_controller *hose = dev->sysdata;
	int irq = COMMON_TABLE_LOOKUP;

	if (irq > 0)
		irq += 16 * hose->index;

	return isa_irq_fixup(dev, irq);
}

static void __init
dp264_init_pci(void)
{
	common_init_pci();
	SMC669_Init(0);
	locate_and_init_vga(NULL);
}

static void __init
monet_init_pci(void)
{
	common_init_pci();
	SMC669_Init(1);
	es1888_init();
	locate_and_init_vga(NULL);
}

static void __init
clipper_init_pci(void)
{
	common_init_pci();
	locate_and_init_vga(NULL);
}

static void __init
webbrick_init_arch(void)
{
	tsunami_init_arch();

	/* Tsunami caches 4 PTEs at a time; DS10 has only 1 hose. */
	hose_head->sg_isa->align_entry = 4;
	hose_head->sg_pci->align_entry = 4;
}


/*
 * The System Vectors
 */

struct alpha_machine_vector dp264_mv __initmv = {
	.vector_name		= "DP264",
	DO_EV6_MMU,
	DO_DEFAULT_RTC,
	DO_TSUNAMI_IO,
	.machine_check		= tsunami_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= DEFAULT_MEM_BASE,
	.pci_dac_offset		= TSUNAMI_DAC_OFFSET,

	.nr_irqs		= 64,
	.device_interrupt	= dp264_device_interrupt,

	.init_arch		= tsunami_init_arch,
	.init_irq		= dp264_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= dp264_init_pci,
	.kill_arch		= tsunami_kill_arch,
	.pci_map_irq		= dp264_map_irq,
	.pci_swizzle		= common_swizzle,
};
ALIAS_MV(dp264)

struct alpha_machine_vector monet_mv __initmv = {
	.vector_name		= "Monet",
	DO_EV6_MMU,
	DO_DEFAULT_RTC,
	DO_TSUNAMI_IO,
	.machine_check		= tsunami_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= DEFAULT_MEM_BASE,
	.pci_dac_offset		= TSUNAMI_DAC_OFFSET,

	.nr_irqs		= 64,
	.device_interrupt	= dp264_device_interrupt,

	.init_arch		= tsunami_init_arch,
	.init_irq		= dp264_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= monet_init_pci,
	.kill_arch		= tsunami_kill_arch,
	.pci_map_irq		= monet_map_irq,
	.pci_swizzle		= monet_swizzle,
};

struct alpha_machine_vector webbrick_mv __initmv = {
	.vector_name		= "Webbrick",
	DO_EV6_MMU,
	DO_DEFAULT_RTC,
	DO_TSUNAMI_IO,
	.machine_check		= tsunami_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= DEFAULT_MEM_BASE,
	.pci_dac_offset		= TSUNAMI_DAC_OFFSET,

	.nr_irqs		= 64,
	.device_interrupt	= dp264_device_interrupt,

	.init_arch		= webbrick_init_arch,
	.init_irq		= dp264_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= common_init_pci,
	.kill_arch		= tsunami_kill_arch,
	.pci_map_irq		= webbrick_map_irq,
	.pci_swizzle		= common_swizzle,
};

struct alpha_machine_vector clipper_mv __initmv = {
	.vector_name		= "Clipper",
	DO_EV6_MMU,
	DO_DEFAULT_RTC,
	DO_TSUNAMI_IO,
	.machine_check		= tsunami_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= DEFAULT_MEM_BASE,
	.pci_dac_offset		= TSUNAMI_DAC_OFFSET,

	.nr_irqs		= 64,
	.device_interrupt	= dp264_device_interrupt,

	.init_arch		= tsunami_init_arch,
	.init_irq		= clipper_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= clipper_init_pci,
	.kill_arch		= tsunami_kill_arch,
	.pci_map_irq		= clipper_map_irq,
	.pci_swizzle		= common_swizzle,
};

/* Sharks strongly resemble Clipper, at least as far
 * as interrupt routing, etc, so we're using the
 * same functions as Clipper does
 */

struct alpha_machine_vector shark_mv __initmv = {
	.vector_name		= "Shark",
	DO_EV6_MMU,
	DO_DEFAULT_RTC,
	DO_TSUNAMI_IO,
	.machine_check		= tsunami_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= DEFAULT_MEM_BASE,
	.pci_dac_offset		= TSUNAMI_DAC_OFFSET,

	.nr_irqs		= 64,
	.device_interrupt	= dp264_device_interrupt,

	.init_arch		= tsunami_init_arch,
	.init_irq		= clipper_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= common_init_pci,
	.kill_arch		= tsunami_kill_arch,
	.pci_map_irq		= clipper_map_irq,
	.pci_swizzle		= common_swizzle,
};

/* No alpha_mv alias for webbrick/monet/clipper, since we compile them
   in unconditionally with DP264; setup_arch knows how to cope.  */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/alpha/kernel/sys_dp264.c
	3	*
	4	* Copyright (C) 1995 David A Rusling
	5	* Copyright (C) 1996, 1999 Jay A Estabrook
	6	* Copyright (C) 1998, 1999 Richard Henderson
	7	*
	8	* Modified by Christopher C. Chimelis, 2001 to
	9	* add support for the addition of Shark to the
	10	* Tsunami family.
	11	*
	12	* Code supporting the DP264 (EV6+TSUNAMI).
	13	*/
	14
1da177e4 LT	15	#include <linux/kernel.h>
	16	#include <linux/types.h>
	17	#include <linux/mm.h>
	18	#include <linux/sched.h>
	19	#include <linux/pci.h>
	20	#include <linux/init.h>
	21	#include <linux/bitops.h>
	22
	23	#include <asm/ptrace.h>
1da177e4 LT	24	#include <asm/dma.h>
	25	#include <asm/irq.h>
	26	#include <asm/mmu_context.h>
	27	#include <asm/io.h>
	28	#include <asm/pgtable.h>
	29	#include <asm/core_tsunami.h>
	30	#include <asm/hwrpb.h>
	31	#include <asm/tlbflush.h>
	32
	33	#include "proto.h"
	34	#include "irq_impl.h"
	35	#include "pci_impl.h"
	36	#include "machvec_impl.h"
	37
	38
	39	/* Note mask bit is true for ENABLED irqs. */
	40	static unsigned long cached_irq_mask;
	41	/* dp264 boards handle at max four CPUs */
	42	static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL };
	43
	44	DEFINE_SPINLOCK(dp264_irq_lock);
	45
	46	static void
	47	tsunami_update_irq_hw(unsigned long mask)
	48	{
	49	register tsunami_cchip *cchip = TSUNAMI_cchip;
	50	unsigned long isa_enable = 1UL << 55;
	51	register int bcpu = boot_cpuid;
	52
	53	#ifdef CONFIG_SMP
	54	volatile unsigned long dim0, dim1, dim2, dim3;
	55	unsigned long mask0, mask1, mask2, mask3, dummy;
	56
	57	mask &= ~isa_enable;
	58	mask0 = mask & cpu_irq_affinity[0];
	59	mask1 = mask & cpu_irq_affinity[1];
	60	mask2 = mask & cpu_irq_affinity[2];
	61	mask3 = mask & cpu_irq_affinity[3];
	62
	63	if (bcpu == 0) mask0 \|= isa_enable;
	64	else if (bcpu == 1) mask1 \|= isa_enable;
	65	else if (bcpu == 2) mask2 \|= isa_enable;
	66	else mask3 \|= isa_enable;
	67
	68	dim0 = &cchip->dim0.csr;
	69	dim1 = &cchip->dim1.csr;
	70	dim2 = &cchip->dim2.csr;
	71	dim3 = &cchip->dim3.csr;
	72	if (!cpu_possible(0)) dim0 = &dummy;
	73	if (!cpu_possible(1)) dim1 = &dummy;
	74	if (!cpu_possible(2)) dim2 = &dummy;
	75	if (!cpu_possible(3)) dim3 = &dummy;
	76
	77	*dim0 = mask0;
	78	*dim1 = mask1;
	79	*dim2 = mask2;
	80	*dim3 = mask3;
	81	mb();
	82	*dim0;
	83	*dim1;
	84	*dim2;
	85	*dim3;
	86	#else
	87	volatile unsigned long *dimB;
88	if (bcpu == 0) dimB = &cchip->dim0.csr;
89	else if (bcpu == 1) dimB = &cchip->dim1.csr;
90	else if (bcpu == 2) dimB = &cchip->dim2.csr;
91	else dimB = &cchip->dim3.csr;
92
93	*dimB = mask \| isa_enable;
94	mb();
95	*dimB;
96	#endif
97	}
98
99	static void
d677f450	100	dp264_enable_irq(struct irq_data *d)
1da177e4 LT	101	{
1da177e4 LT	102	spin_lock(&dp264_irq_lock);
d677f450	103	cached_irq_mask \|= 1UL << d->irq;
1da177e4 LT	104	tsunami_update_irq_hw(cached_irq_mask);
	105	spin_unlock(&dp264_irq_lock);
	106	}
	107
	108	static void
d677f450	109	dp264_disable_irq(struct irq_data *d)
1da177e4 LT	110	{
1da177e4 LT	111	spin_lock(&dp264_irq_lock);
d677f450	112	cached_irq_mask &= ~(1UL << d->irq);
1da177e4 LT	113	tsunami_update_irq_hw(cached_irq_mask);
	114	spin_unlock(&dp264_irq_lock);
	115	}
	116
1da177e4	117	static void
d677f450	118	clipper_enable_irq(struct irq_data *d)
1da177e4 LT	119	{
1da177e4 LT	120	spin_lock(&dp264_irq_lock);
d677f450	121	cached_irq_mask \|= 1UL << (d->irq - 16);
1da177e4 LT	122	tsunami_update_irq_hw(cached_irq_mask);
	123	spin_unlock(&dp264_irq_lock);
	124	}
	125
	126	static void
d677f450	127	clipper_disable_irq(struct irq_data *d)
1da177e4 LT	128	{
1da177e4 LT	129	spin_lock(&dp264_irq_lock);
d677f450	130	cached_irq_mask &= ~(1UL << (d->irq - 16));
1da177e4 LT	131	tsunami_update_irq_hw(cached_irq_mask);
	132	spin_unlock(&dp264_irq_lock);
	133	}
	134
1da177e4 LT	135	static void
	136	cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
	137	{
	138	int cpu;
	139
	140	for (cpu = 0; cpu < 4; cpu++) {
	141	unsigned long aff = cpu_irq_affinity[cpu];
81740fc6	142	if (cpumask_test_cpu(cpu, &affinity))
1da177e4 LT	143	aff \|= 1UL << irq;
	144	else
	145	aff &= ~(1UL << irq);
	146	cpu_irq_affinity[cpu] = aff;
	147	}
	148	}
	149
d5dedd45	150	static int
d677f450 TG	151	dp264_set_affinity(struct irq_data d, const struct cpumask affinity,
	152	bool force)
	153	{
1da177e4	154	spin_lock(&dp264_irq_lock);
d677f450	155	cpu_set_irq_affinity(d->irq, *affinity);
1da177e4 LT	156	tsunami_update_irq_hw(cached_irq_mask);
1da177e4 LT	157	spin_unlock(&dp264_irq_lock);
d5dedd45 YL	158
d5dedd45 YL	159	return 0;
1da177e4 LT	160	}
1da177e4 LT	161
d5dedd45	162	static int
d677f450 TG	163	clipper_set_affinity(struct irq_data d, const struct cpumask affinity,
	164	bool force)
	165	{
1da177e4	166	spin_lock(&dp264_irq_lock);
d677f450	167	cpu_set_irq_affinity(d->irq - 16, *affinity);
1da177e4 LT	168	tsunami_update_irq_hw(cached_irq_mask);
1da177e4 LT	169	spin_unlock(&dp264_irq_lock);
d5dedd45 YL	170
d5dedd45 YL	171	return 0;
1da177e4 LT	172	}
1da177e4 LT	173
44377f62	174	static struct irq_chip dp264_irq_type = {
d677f450 TG	175	.name = "DP264",
	176	.irq_unmask = dp264_enable_irq,
	177	.irq_mask = dp264_disable_irq,
	178	.irq_mask_ack = dp264_disable_irq,
	179	.irq_set_affinity = dp264_set_affinity,
1da177e4 LT	180	};
1da177e4 LT	181
44377f62	182	static struct irq_chip clipper_irq_type = {
d677f450 TG	183	.name = "CLIPPER",
	184	.irq_unmask = clipper_enable_irq,
	185	.irq_mask = clipper_disable_irq,
	186	.irq_mask_ack = clipper_disable_irq,
	187	.irq_set_affinity = clipper_set_affinity,
1da177e4 LT	188	};
	189
	190	static void
7ca56053	191	dp264_device_interrupt(unsigned long vector)
1da177e4 LT	192	{
1da177e4 LT	193	#if 1
7f2d889c	194	printk("dp264_device_interrupt: NOT IMPLEMENTED YET!!\n");
1da177e4 LT	195	#else
	196	unsigned long pld;
	197	unsigned int i;
	198
	199	/* Read the interrupt summary register of TSUNAMI */
	200	pld = TSUNAMI_cchip->dir0.csr;
	201
	202	/*
	203	* Now for every possible bit set, work through them and call
	204	* the appropriate interrupt handler.
	205	*/
	206	while (pld) {
	207	i = ffz(~pld);
	208	pld &= pld - 1; /* clear least bit set */
	209	if (i == 55)
7ca56053	210	isa_device_interrupt(vector);
1da177e4	211	else
3dbb8c62	212	handle_irq(16 + i);
1da177e4 LT	213	#if 0
	214	TSUNAMI_cchip->dir0.csr = 1UL << i; mb();
	215	tmp = TSUNAMI_cchip->dir0.csr;
	216	#endif
	217	}
	218	#endif
	219	}
	220
	221	static void
7ca56053	222	dp264_srm_device_interrupt(unsigned long vector)
1da177e4 LT	223	{
	224	int irq;
	225
	226	irq = (vector - 0x800) >> 4;
	227
	228	/*
	229	* The SRM console reports PCI interrupts with a vector calculated by:
	230	*
	231	* 0x900 + (0x10 * DRIR-bit)
	232	*
	233	* So bit 16 shows up as IRQ 32, etc.
	234	*
	235	* On DP264/BRICK/MONET, we adjust it down by 16 because at least
	236	* that many of the low order bits of the DRIR are not used, and
	237	* so we don't count them.
	238	*/
	239	if (irq >= 32)
	240	irq -= 16;
	241
3dbb8c62	242	handle_irq(irq);
1da177e4 LT	243	}
	244
	245	static void
7ca56053	246	clipper_srm_device_interrupt(unsigned long vector)
1da177e4 LT	247	{
	248	int irq;
	249
	250	irq = (vector - 0x800) >> 4;
	251
	252	/*
	253	* The SRM console reports PCI interrupts with a vector calculated by:
	254	*
	255	* 0x900 + (0x10 * DRIR-bit)
	256	*
	257	* So bit 16 shows up as IRQ 32, etc.
	258	*
	259	* CLIPPER uses bits 8-47 for PCI interrupts, so we do not need
	260	* to scale down the vector reported, we just use it.
	261	*
	262	* Eg IRQ 24 is DRIR bit 8, etc, etc
	263	*/
3dbb8c62	264	handle_irq(irq);
1da177e4 LT	265	}
	266
	267	static void __init
44377f62	268	init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
1da177e4 LT	269	{
	270	long i;
	271	for (i = imin; i <= imax; ++i) {
a9eb076b	272	irq_set_chip_and_handler(i, ops, handle_level_irq);
d677f450	273	irq_set_status_flags(i, IRQ_LEVEL);
1da177e4 LT	274	}
	275	}
	276
	277	static void __init
	278	dp264_init_irq(void)
	279	{
	280	outb(0, DMA1_RESET_REG);
	281	outb(0, DMA2_RESET_REG);
	282	outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
	283	outb(0, DMA2_MASK_REG);
	284
	285	if (alpha_using_srm)
	286	alpha_mv.device_interrupt = dp264_srm_device_interrupt;
	287
	288	tsunami_update_irq_hw(0);
	289
	290	init_i8259a_irqs();
	291	init_tsunami_irqs(&dp264_irq_type, 16, 47);
	292	}
	293
	294	static void __init
	295	clipper_init_irq(void)
	296	{
	297	outb(0, DMA1_RESET_REG);
	298	outb(0, DMA2_RESET_REG);
	299	outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
	300	outb(0, DMA2_MASK_REG);
	301
	302	if (alpha_using_srm)
	303	alpha_mv.device_interrupt = clipper_srm_device_interrupt;
	304
	305	tsunami_update_irq_hw(0);
	306
	307	init_i8259a_irqs();
	308	init_tsunami_irqs(&clipper_irq_type, 24, 63);
	309	}
	310
	311
	312	/*
	313	* PCI Fixup configuration.
	314	*
	315	* Summary @ TSUNAMI_CSR_DIM0:
	316	* Bit Meaning
	317	* 0-17 Unused
	318	*18 Interrupt SCSI B (Adaptec 7895 builtin)
	319	*19 Interrupt SCSI A (Adaptec 7895 builtin)
	320	*20 Interrupt Line D from slot 2 PCI0
	321	*21 Interrupt Line C from slot 2 PCI0
	322	*22 Interrupt Line B from slot 2 PCI0
	323	*23 Interrupt Line A from slot 2 PCI0
	324	*24 Interrupt Line D from slot 1 PCI0
	325	*25 Interrupt Line C from slot 1 PCI0
	326	*26 Interrupt Line B from slot 1 PCI0
	327	*27 Interrupt Line A from slot 1 PCI0
	328	*28 Interrupt Line D from slot 0 PCI0
	329	*29 Interrupt Line C from slot 0 PCI0
	330	*30 Interrupt Line B from slot 0 PCI0
	331	*31 Interrupt Line A from slot 0 PCI0
	332	*
	333	*32 Interrupt Line D from slot 3 PCI1
	334	*33 Interrupt Line C from slot 3 PCI1
	335	*34 Interrupt Line B from slot 3 PCI1
	336	*35 Interrupt Line A from slot 3 PCI1
	337	*36 Interrupt Line D from slot 2 PCI1
338	*37 Interrupt Line C from slot 2 PCI1
339	*38 Interrupt Line B from slot 2 PCI1
340	*39 Interrupt Line A from slot 2 PCI1
341	*40 Interrupt Line D from slot 1 PCI1
342	*41 Interrupt Line C from slot 1 PCI1
343	*42 Interrupt Line B from slot 1 PCI1
344	*43 Interrupt Line A from slot 1 PCI1
345	*44 Interrupt Line D from slot 0 PCI1
346	*45 Interrupt Line C from slot 0 PCI1
347	*46 Interrupt Line B from slot 0 PCI1
348	*47 Interrupt Line A from slot 0 PCI1
349	*48-52 Unused
350	*53 PCI0 NMI (from Cypress)
351	*54 PCI0 SMI INT (from Cypress)
352	*55 PCI0 ISA Interrupt (from Cypress)
353	*56-60 Unused
354	*61 PCI1 Bus Error
355	*62 PCI0 Bus Error
356	*63 Reserved
357	*
358	* IdSel
359	* 5 Cypress Bridge I/O
360	* 6 SCSI Adaptec builtin
361	* 7 64 bit PCI option slot 0 (all busses)
362	* 8 64 bit PCI option slot 1 (all busses)
363	* 9 64 bit PCI option slot 2 (all busses)
364	* 10 64 bit PCI option slot 3 (not bus 0)
365	*/
366
997a51ae	367	static int __init
bf362f75	368	isa_irq_fixup(const struct pci_dev *dev, int irq)
997a51ae IK	369	{
	370	u8 irq8;
	371
	372	if (irq > 0)
	373	return irq;
	374
	375	/* This interrupt is routed via ISA bridge, so we'll
	376	just have to trust whatever value the console might
	377	have assigned. */
	378	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
	379
	380	return irq8 & 0xf;
	381	}
	382
1da177e4	383	static int __init
d5341942	384	dp264_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1da177e4 LT	385	{
	386	static char irq_tab[6][5] __initdata = {
	387	/INT INTA INTB INTC INTD /
	388	{ -1, -1, -1, -1, -1}, /* IdSel 5 ISA Bridge */
	389	{ 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/
	390	{ 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */
	391	{ 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */
	392	{ 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */
	393	{ 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */
	394	};
	395	const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
1da177e4 LT	396	struct pci_controller *hose = dev->sysdata;
	397	int irq = COMMON_TABLE_LOOKUP;
	398
997a51ae	399	if (irq > 0)
1da177e4	400	irq += 16 * hose->index;
1da177e4	401
997a51ae	402	return isa_irq_fixup(dev, irq);
1da177e4 LT	403	}
	404
	405	static int __init
d5341942	406	monet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1da177e4 LT	407	{
	408	static char irq_tab[13][5] __initdata = {
	409	/INT INTA INTB INTC INTD /
	410	{ 45, 45, 45, 45, 45}, /* IdSel 3 21143 PCI1 */
	411	{ -1, -1, -1, -1, -1}, /* IdSel 4 unused */
	412	{ -1, -1, -1, -1, -1}, /* IdSel 5 unused */
	413	{ 47, 47, 47, 47, 47}, /* IdSel 6 SCSI PCI1 */
	414	{ -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
	415	{ -1, -1, -1, -1, -1}, /* IdSel 8 P2P PCI1 */
	416	#if 1
	417	{ 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
	418	{ 24, 24, 25, 26, 27}, /* IdSel 15 slot 5 PCI2*/
	419	#else
	420	{ -1, -1, -1, -1, -1}, /* IdSel 9 unused */
	421	{ -1, -1, -1, -1, -1}, /* IdSel 10 unused */
	422	#endif
	423	{ 40, 40, 41, 42, 43}, /* IdSel 11 slot 1 PCI0*/
	424	{ 36, 36, 37, 38, 39}, /* IdSel 12 slot 2 PCI0*/
	425	{ 32, 32, 33, 34, 35}, /* IdSel 13 slot 3 PCI0*/
	426	{ 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
	427	{ 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/
	428	};
	429	const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
997a51ae IK	430
997a51ae IK	431	return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
1da177e4 LT	432	}
	433
	434	static u8 __init
	435	monet_swizzle(struct pci_dev dev, u8 pinp)
	436	{
	437	struct pci_controller *hose = dev->sysdata;
	438	int slot, pin = *pinp;
	439
	440	if (!dev->bus->parent) {
	441	slot = PCI_SLOT(dev->devfn);
	442	}
	443	/* Check for the built-in bridge on hose 1. */
	444	else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) {
	445	slot = PCI_SLOT(dev->devfn);
	446	} else {
	447	/* Must be a card-based bridge. */
	448	do {
	449	/* Check for built-in bridge on hose 1. */
	450	if (hose->index == 1 &&
	451	PCI_SLOT(dev->bus->self->devfn) == 8) {
	452	slot = PCI_SLOT(dev->devfn);
	453	break;
	454	}
1be9baa0	455	pin = pci_swizzle_interrupt_pin(dev, pin);
1da177e4 LT	456
	457	/* Move up the chain of bridges. */
	458	dev = dev->bus->self;
	459	/* Slot of the next bridge. */
	460	slot = PCI_SLOT(dev->devfn);
	461	} while (dev->bus->self);
	462	}
	463	*pinp = pin;
	464	return slot;
	465	}
	466
	467	static int __init
d5341942	468	webbrick_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1da177e4 LT	469	{
	470	static char irq_tab[13][5] __initdata = {
	471	/INT INTA INTB INTC INTD /
	472	{ -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
	473	{ -1, -1, -1, -1, -1}, /* IdSel 8 unused */
	474	{ 29, 29, 29, 29, 29}, /* IdSel 9 21143 #1 */
	475	{ -1, -1, -1, -1, -1}, /* IdSel 10 unused */
	476	{ 30, 30, 30, 30, 30}, /* IdSel 11 21143 #2 */
	477	{ -1, -1, -1, -1, -1}, /* IdSel 12 unused */
	478	{ -1, -1, -1, -1, -1}, /* IdSel 13 unused */
	479	{ 35, 35, 34, 33, 32}, /* IdSel 14 slot 0 */
	480	{ 39, 39, 38, 37, 36}, /* IdSel 15 slot 1 */
	481	{ 43, 43, 42, 41, 40}, /* IdSel 16 slot 2 */
	482	{ 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */
	483	};
	484	const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
997a51ae IK	485
997a51ae IK	486	return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
1da177e4 LT	487	}
	488
	489	static int __init
d5341942	490	clipper_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1da177e4 LT	491	{
	492	static char irq_tab[7][5] __initdata = {
	493	/INT INTA INTB INTC INTD /
	494	{ 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */
	495	{ 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */
	496	{ 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */
	497	{ 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */
	498	{ 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */
	499	{ 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */
	500	{ -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */
	501	};
	502	const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
1da177e4 LT	503	struct pci_controller *hose = dev->sysdata;
	504	int irq = COMMON_TABLE_LOOKUP;
	505
	506	if (irq > 0)
	507	irq += 16 * hose->index;
	508
997a51ae	509	return isa_irq_fixup(dev, irq);
1da177e4 LT	510	}
	511
	512	static void __init
	513	dp264_init_pci(void)
	514	{
	515	common_init_pci();
	516	SMC669_Init(0);
025a2215	517	locate_and_init_vga(NULL);
1da177e4 LT	518	}
	519
	520	static void __init
	521	monet_init_pci(void)
	522	{
	523	common_init_pci();
	524	SMC669_Init(1);
	525	es1888_init();
025a2215 JE	526	locate_and_init_vga(NULL);
	527	}
	528
	529	static void __init
	530	clipper_init_pci(void)
	531	{
	532	common_init_pci();
	533	locate_and_init_vga(NULL);
1da177e4 LT	534	}
	535
	536	static void __init
	537	webbrick_init_arch(void)
	538	{
	539	tsunami_init_arch();
	540
	541	/* Tsunami caches 4 PTEs at a time; DS10 has only 1 hose. */
	542	hose_head->sg_isa->align_entry = 4;
	543	hose_head->sg_pci->align_entry = 4;
	544	}
	545
	546
	547	/*
	548	* The System Vectors
	549	*/
	550
	551	struct alpha_machine_vector dp264_mv __initmv = {
	552	.vector_name = "DP264",
	553	DO_EV6_MMU,
	554	DO_DEFAULT_RTC,
	555	DO_TSUNAMI_IO,
	556	.machine_check = tsunami_machine_check,
	557	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
	558	.min_io_address = DEFAULT_IO_BASE,
	559	.min_mem_address = DEFAULT_MEM_BASE,
	560	.pci_dac_offset = TSUNAMI_DAC_OFFSET,
	561
	562	.nr_irqs = 64,
	563	.device_interrupt = dp264_device_interrupt,
	564
	565	.init_arch = tsunami_init_arch,
	566	.init_irq = dp264_init_irq,
	567	.init_rtc = common_init_rtc,
	568	.init_pci = dp264_init_pci,
	569	.kill_arch = tsunami_kill_arch,
	570	.pci_map_irq = dp264_map_irq,
	571	.pci_swizzle = common_swizzle,
	572	};
	573	ALIAS_MV(dp264)
	574
	575	struct alpha_machine_vector monet_mv __initmv = {
	576	.vector_name = "Monet",
	577	DO_EV6_MMU,
	578	DO_DEFAULT_RTC,
	579	DO_TSUNAMI_IO,
	580	.machine_check = tsunami_machine_check,
	581	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
	582	.min_io_address = DEFAULT_IO_BASE,
	583	.min_mem_address = DEFAULT_MEM_BASE,
	584	.pci_dac_offset = TSUNAMI_DAC_OFFSET,
	585
	586	.nr_irqs = 64,
	587	.device_interrupt = dp264_device_interrupt,
	588
	589	.init_arch = tsunami_init_arch,
	590	.init_irq = dp264_init_irq,
	591	.init_rtc = common_init_rtc,
	592	.init_pci = monet_init_pci,
	593	.kill_arch = tsunami_kill_arch,
	594	.pci_map_irq = monet_map_irq,
	595	.pci_swizzle = monet_swizzle,
	596	};
	597
598	struct alpha_machine_vector webbrick_mv __initmv = {
599	.vector_name = "Webbrick",
600	DO_EV6_MMU,
601	DO_DEFAULT_RTC,
602	DO_TSUNAMI_IO,
603	.machine_check = tsunami_machine_check,
604	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
605	.min_io_address = DEFAULT_IO_BASE,
606	.min_mem_address = DEFAULT_MEM_BASE,
607	.pci_dac_offset = TSUNAMI_DAC_OFFSET,
608
609	.nr_irqs = 64,
610	.device_interrupt = dp264_device_interrupt,
611
612	.init_arch = webbrick_init_arch,
613	.init_irq = dp264_init_irq,
614	.init_rtc = common_init_rtc,
615	.init_pci = common_init_pci,
616	.kill_arch = tsunami_kill_arch,
617	.pci_map_irq = webbrick_map_irq,
618	.pci_swizzle = common_swizzle,
619	};
620
621	struct alpha_machine_vector clipper_mv __initmv = {
622	.vector_name = "Clipper",
623	DO_EV6_MMU,
624	DO_DEFAULT_RTC,
625	DO_TSUNAMI_IO,
626	.machine_check = tsunami_machine_check,
627	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
628	.min_io_address = DEFAULT_IO_BASE,
629	.min_mem_address = DEFAULT_MEM_BASE,
630	.pci_dac_offset = TSUNAMI_DAC_OFFSET,
631
632	.nr_irqs = 64,
633	.device_interrupt = dp264_device_interrupt,
634
635	.init_arch = tsunami_init_arch,
636	.init_irq = clipper_init_irq,
637	.init_rtc = common_init_rtc,
025a2215	638	.init_pci = clipper_init_pci,
1da177e4 LT	639	.kill_arch = tsunami_kill_arch,
	640	.pci_map_irq = clipper_map_irq,
	641	.pci_swizzle = common_swizzle,
	642	};
	643
	644	/* Sharks strongly resemble Clipper, at least as far
	645	* as interrupt routing, etc, so we're using the
	646	* same functions as Clipper does
	647	*/
	648
	649	struct alpha_machine_vector shark_mv __initmv = {
	650	.vector_name = "Shark",
	651	DO_EV6_MMU,
	652	DO_DEFAULT_RTC,
	653	DO_TSUNAMI_IO,
	654	.machine_check = tsunami_machine_check,
	655	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
	656	.min_io_address = DEFAULT_IO_BASE,
	657	.min_mem_address = DEFAULT_MEM_BASE,
	658	.pci_dac_offset = TSUNAMI_DAC_OFFSET,
	659
	660	.nr_irqs = 64,
	661	.device_interrupt = dp264_device_interrupt,
	662
	663	.init_arch = tsunami_init_arch,
	664	.init_irq = clipper_init_irq,
	665	.init_rtc = common_init_rtc,
	666	.init_pci = common_init_pci,
	667	.kill_arch = tsunami_kill_arch,
	668	.pci_map_irq = clipper_map_irq,
	669	.pci_swizzle = common_swizzle,
	670	};
	671
	672	/* No alpha_mv alias for webbrick/monet/clipper, since we compile them
	673	in unconditionally with DP264; setup_arch knows how to cope. */