[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / alpha / kernel / pci.c

/*
 *	linux/arch/alpha/kernel/pci.c
 *
 * Extruded from code written by
 *	Dave Rusling (david.rusling@reo.mts.dec.com)
 *	David Mosberger (davidm@cs.arizona.edu)
 */

/* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     PCI-PCI bridges cleanup
 */
#include <linux/string.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/bootmem.h>
#include <linux/module.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include <asm/machvec.h>

#include "proto.h"
#include "pci_impl.h"


/*
 * Some string constants used by the various core logics. 
 */

const char *const pci_io_names[] = {
  "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
  "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
};

const char *const pci_mem_names[] = {
  "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
  "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
};

const char pci_hae0_name[] = "HAE0";

/*
 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
 * assignments.
 */

/*
 * The PCI controller list.
 */

struct pci_controller *hose_head, **hose_tail = &hose_head;
struct pci_controller *pci_isa_hose;

/*
 * Quirks.
 */

static void quirk_isa_bridge(struct pci_dev *dev)
{
	dev->class = PCI_CLASS_BRIDGE_ISA << 8;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);

static void quirk_cypress(struct pci_dev *dev)
{
	/* The Notorious Cy82C693 chip.  */

	/* The generic legacy mode IDE fixup in drivers/pci/probe.c
	   doesn't work correctly with the Cypress IDE controller as
	   it has non-standard register layout.  Fix that.  */
	if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
		dev->resource[2].start = dev->resource[3].start = 0;
		dev->resource[2].end = dev->resource[3].end = 0;
		dev->resource[2].flags = dev->resource[3].flags = 0;
		if (PCI_FUNC(dev->devfn) == 2) {
			dev->resource[0].start = 0x170;
			dev->resource[0].end = 0x177;
			dev->resource[1].start = 0x376;
			dev->resource[1].end = 0x376;
		}
	}

	/* The Cypress bridge responds on the PCI bus in the address range
	   0xffff0000-0xffffffff (conventional x86 BIOS ROM).  There is no
	   way to turn this off.  The bridge also supports several extended
	   BIOS ranges (disabled after power-up), and some consoles do turn
	   them on.  So if we use a large direct-map window, or a large SG
	   window, we must avoid the entire 0xfff00000-0xffffffff region.  */
	if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
		if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
			__direct_map_size = 0xfff00000UL - __direct_map_base;
		else {
			struct pci_controller *hose = dev->sysdata;
			struct pci_iommu_arena *pci = hose->sg_pci;
			if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
				pci->size = 0xfff00000UL - pci->dma_base;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);

/* Called for each device after PCI setup is done. */
static void pcibios_fixup_final(struct pci_dev *dev)
{
	unsigned int class = dev->class >> 8;

	if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
		dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
		isa_bridge = dev;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);

/* Just declaring that the power-of-ten prefixes are actually the
   power-of-two ones doesn't make it true :) */
#define KB			1024
#define MB			(1024*KB)
#define GB			(1024*MB)

resource_size_t
pcibios_align_resource(void *data, const struct resource *res,
		       resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	struct pci_controller *hose = dev->sysdata;
	unsigned long alignto;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		/* Make sure we start at our min on all hoses */
		if (start - hose->io_space->start < PCIBIOS_MIN_IO)
			start = PCIBIOS_MIN_IO + hose->io_space->start;

		/*
		 * Put everything into 0x00-0xff region modulo 0x400
		 */
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	}
	else if	(res->flags & IORESOURCE_MEM) {
		/* Make sure we start at our min on all hoses */
		if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
			start = PCIBIOS_MIN_MEM + hose->mem_space->start;

		/*
		 * The following holds at least for the Low Cost
		 * Alpha implementation of the PCI interface:
		 *
		 * In sparse memory address space, the first
		 * octant (16MB) of every 128MB segment is
		 * aliased to the very first 16 MB of the
		 * address space (i.e., it aliases the ISA
		 * memory address space).  Thus, we try to
		 * avoid allocating PCI devices in that range.
		 * Can be allocated in 2nd-7th octant only.
		 * Devices that need more than 112MB of
		 * address space must be accessed through
		 * dense memory space only!
		 */

		/* Align to multiple of size of minimum base.  */
		alignto = max_t(resource_size_t, 0x1000, align);
		start = ALIGN(start, alignto);
		if (hose->sparse_mem_base && size <= 7 * 16*MB) {
			if (((start / (16*MB)) & 0x7) == 0) {
				start &= ~(128*MB - 1);
				start += 16*MB;
				start  = ALIGN(start, alignto);
			}
			if (start/(128*MB) != (start + size - 1)/(128*MB)) {
				start &= ~(128*MB - 1);
				start += (128 + 16)*MB;
				start  = ALIGN(start, alignto);
			}
		}
	}

	return start;
}
#undef KB
#undef MB
#undef GB

static int __init
pcibios_init(void)
{
	if (alpha_mv.init_pci)
		alpha_mv.init_pci();
	return 0;
}

subsys_initcall(pcibios_init);

#ifdef ALPHA_RESTORE_SRM_SETUP
static struct pdev_srm_saved_conf *srm_saved_configs;

void pdev_save_srm_config(struct pci_dev *dev)
{
	struct pdev_srm_saved_conf *tmp;
	static int printed = 0;

	if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
		return;

	if (!printed) {
		printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
		printed = 1;
	}

	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
	if (!tmp) {
		printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
		return;
	}
	tmp->next = srm_saved_configs;
	tmp->dev = dev;

	pci_save_state(dev);

	srm_saved_configs = tmp;
}

void
pci_restore_srm_config(void)
{
	struct pdev_srm_saved_conf *tmp;

	/* No need to restore if probed only. */
	if (pci_has_flag(PCI_PROBE_ONLY))
		return;

	/* Restore SRM config. */
	for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
		pci_restore_state(tmp->dev);
	}
}
#endif

void pcibios_fixup_bus(struct pci_bus *bus)
{
	struct pci_dev *dev = bus->self;

	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
 		   (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 		pci_read_bridge_bases(bus);
	} 

	list_for_each_entry(dev, &bus->devices, bus_list) {
		pdev_save_srm_config(dev);
	}
}

int
pcibios_enable_device(struct pci_dev *dev, int mask)
{
	return pci_enable_resources(dev, mask);
}

/*
 *  If we set up a device for bus mastering, we need to check the latency
 *  timer as certain firmware forgets to set it properly, as seen
 *  on SX164 and LX164 with SRM.
 */
void
pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat >= 16) return;
	printk("PCI: Setting latency timer of device %s to 64\n",
							pci_name(dev));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
}

void __init
pcibios_claim_one_bus(struct pci_bus *b)
{
	struct pci_dev *dev;
	struct pci_bus *child_bus;

	list_for_each_entry(dev, &b->devices, bus_list) {
		int i;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			struct resource *r = &dev->resource[i];

			if (r->parent || !r->start || !r->flags)
				continue;
			if (pci_has_flag(PCI_PROBE_ONLY) ||
			    (r->flags & IORESOURCE_PCI_FIXED))
				pci_claim_resource(dev, i);
		}
	}

	list_for_each_entry(child_bus, &b->children, node)
		pcibios_claim_one_bus(child_bus);
}

static void __init
pcibios_claim_console_setup(void)
{
	struct pci_bus *b;

	list_for_each_entry(b, &pci_root_buses, node)
		pcibios_claim_one_bus(b);
}

void __init
common_init_pci(void)
{
	struct pci_controller *hose;
	struct list_head resources;
	struct pci_bus *bus;
	int next_busno;
	int need_domain_info = 0;
	u32 pci_mem_end;
	u32 sg_base;
	unsigned long end;

	/* Scan all of the recorded PCI controllers.  */
	for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
		sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;

		/* Adjust hose mem_space limit to prevent PCI allocations
		   in the iommu windows. */
		pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
		end = hose->mem_space->start + pci_mem_end;
		if (hose->mem_space->end > end)
			hose->mem_space->end = end;

		INIT_LIST_HEAD(&resources);
		pci_add_resource_offset(&resources, hose->io_space,
					hose->io_space->start);
		pci_add_resource_offset(&resources, hose->mem_space,
					hose->mem_space->start);

		bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops,
					hose, &resources);
		hose->bus = bus;
		hose->need_domain_info = need_domain_info;
		next_busno = bus->busn_res.end + 1;
		/* Don't allow 8-bit bus number overflow inside the hose -
		   reserve some space for bridges. */ 
		if (next_busno > 224) {
			next_busno = 0;
			need_domain_info = 1;
		}
	}

	pcibios_claim_console_setup();

	pci_assign_unassigned_resources();
	pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
}


struct pci_controller * __init
alloc_pci_controller(void)
{
	struct pci_controller *hose;

	hose = alloc_bootmem(sizeof(*hose));

	*hose_tail = hose;
	hose_tail = &hose->next;

	return hose;
}

struct resource * __init
alloc_resource(void)
{
	struct resource *res;

	res = alloc_bootmem(sizeof(*res));

	return res;
}


/* Provide information on locations of various I/O regions in physical
   memory.  Do this on a per-card basis so that we choose the right hose.  */

asmlinkage long
sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
{
	struct pci_controller *hose;
	struct pci_dev *dev;

	/* from hose or from bus.devfn */
	if (which & IOBASE_FROM_HOSE) {
		for(hose = hose_head; hose; hose = hose->next) 
			if (hose->index == bus) break;
		if (!hose) return -ENODEV;
	} else {
		/* Special hook for ISA access.  */
		if (bus == 0 && dfn == 0) {
			hose = pci_isa_hose;
		} else {
			dev = pci_get_bus_and_slot(bus, dfn);
			if (!dev)
				return -ENODEV;
			hose = dev->sysdata;
			pci_dev_put(dev);
		}
	}

	switch (which & ~IOBASE_FROM_HOSE) {
	case IOBASE_HOSE:
		return hose->index;
	case IOBASE_SPARSE_MEM:
		return hose->sparse_mem_base;
	case IOBASE_DENSE_MEM:
		return hose->dense_mem_base;
	case IOBASE_SPARSE_IO:
		return hose->sparse_io_base;
	case IOBASE_DENSE_IO:
		return hose->dense_io_base;
	case IOBASE_ROOT_BUS:
		return hose->bus->number;
	}

	return -EOPNOTSUPP;
}

/* Destroy an __iomem token.  Not copied from lib/iomap.c.  */

void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
{
	if (__is_mmio(addr))
		iounmap(addr);
}

EXPORT_SYMBOL(pci_iounmap);

/* FIXME: Some boxes have multiple ISA bridges! */
struct pci_dev *isa_bridge;
EXPORT_SYMBOL(isa_bridge);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/alpha/kernel/pci.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling (david.rusling@reo.mts.dec.com)
	6	* David Mosberger (davidm@cs.arizona.edu)
	7	*/
	8
	9	/* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
	10
	11	/*
	12	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	13	* PCI-PCI bridges cleanup
	14	*/
1da177e4 LT	15	#include <linux/string.h>
	16	#include <linux/pci.h>
	17	#include <linux/init.h>
	18	#include <linux/ioport.h>
	19	#include <linux/kernel.h>
	20	#include <linux/bootmem.h>
	21	#include <linux/module.h>
	22	#include <linux/cache.h>
	23	#include <linux/slab.h>
	24	#include <asm/machvec.h>
	25
	26	#include "proto.h"
	27	#include "pci_impl.h"
	28
	29
	30	/*
	31	* Some string constants used by the various core logics.
	32	*/
	33
	34	const char *const pci_io_names[] = {
	35	"PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
	36	"PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
	37	};
	38
	39	const char *const pci_mem_names[] = {
	40	"PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
	41	"PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
	42	};
	43
	44	const char pci_hae0_name[] = "HAE0";
	45
1da177e4	46	/*
151d16d5 BH	47	* If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
151d16d5 BH	48	* assignments.
1da177e4	49	*/
1da177e4 LT	50
	51	/*
	52	* The PCI controller list.
	53	*/
	54
	55	struct pci_controller hose_head, *hose_tail = &hose_head;
	56	struct pci_controller *pci_isa_hose;
	57
	58	/*
	59	* Quirks.
	60	*/
	61
f8d6c8d9	62	static void quirk_isa_bridge(struct pci_dev *dev)
1da177e4 LT	63	{
	64	dev->class = PCI_CLASS_BRIDGE_ISA << 8;
	65	}
	66	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
	67
f8d6c8d9	68	static void quirk_cypress(struct pci_dev *dev)
1da177e4	69	{
a744e016 IK	70	/* The Notorious Cy82C693 chip. */
	71
	72	/* The generic legacy mode IDE fixup in drivers/pci/probe.c
	73	doesn't work correctly with the Cypress IDE controller as
	74	it has non-standard register layout. Fix that. */
	75	if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
	76	dev->resource[2].start = dev->resource[3].start = 0;
	77	dev->resource[2].end = dev->resource[3].end = 0;
	78	dev->resource[2].flags = dev->resource[3].flags = 0;
	79	if (PCI_FUNC(dev->devfn) == 2) {
	80	dev->resource[0].start = 0x170;
	81	dev->resource[0].end = 0x177;
	82	dev->resource[1].start = 0x376;
	83	dev->resource[1].end = 0x376;
	84	}
	85	}
	86
1da177e4 LT	87	/* The Cypress bridge responds on the PCI bus in the address range
	88	0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
	89	way to turn this off. The bridge also supports several extended
	90	BIOS ranges (disabled after power-up), and some consoles do turn
	91	them on. So if we use a large direct-map window, or a large SG
	92	window, we must avoid the entire 0xfff00000-0xffffffff region. */
72cff123	93	if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
1da177e4 LT	94	if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
	95	__direct_map_size = 0xfff00000UL - __direct_map_base;
	96	else {
	97	struct pci_controller *hose = dev->sysdata;
	98	struct pci_iommu_arena *pci = hose->sg_pci;
	99	if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
	100	pci->size = 0xfff00000UL - pci->dma_base;
	101	}
	102	}
	103	}
	104	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
	105
	106	/* Called for each device after PCI setup is done. */
f8d6c8d9	107	static void pcibios_fixup_final(struct pci_dev *dev)
1da177e4 LT	108	{
	109	unsigned int class = dev->class >> 8;
	110
	111	if (class == PCI_CLASS_BRIDGE_ISA \|\| class == PCI_CLASS_BRIDGE_EISA) {
	112	dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
	113	isa_bridge = dev;
	114	}
	115	}
	116	DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
	117
	118	/* Just declaring that the power-of-ten prefixes are actually the
	119	power-of-two ones doesn't make it true :) */
	120	#define KB 1024
	121	#define MB (1024*KB)
	122	#define GB (1024*MB)
	123
b26b2d49	124	resource_size_t
3b7a17fc	125	pcibios_align_resource(void data, const struct resource res,
e31dd6e4	126	resource_size_t size, resource_size_t align)
1da177e4 LT	127	{
	128	struct pci_dev *dev = data;
	129	struct pci_controller *hose = dev->sysdata;
	130	unsigned long alignto;
e31dd6e4	131	resource_size_t start = res->start;
1da177e4 LT	132
	133	if (res->flags & IORESOURCE_IO) {
	134	/* Make sure we start at our min on all hoses */
	135	if (start - hose->io_space->start < PCIBIOS_MIN_IO)
	136	start = PCIBIOS_MIN_IO + hose->io_space->start;
	137
	138	/*
	139	* Put everything into 0x00-0xff region modulo 0x400
	140	*/
	141	if (start & 0x300)
	142	start = (start + 0x3ff) & ~0x3ff;
	143	}
	144	else if (res->flags & IORESOURCE_MEM) {
	145	/* Make sure we start at our min on all hoses */
	146	if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
	147	start = PCIBIOS_MIN_MEM + hose->mem_space->start;
	148
	149	/*
	150	* The following holds at least for the Low Cost
	151	* Alpha implementation of the PCI interface:
	152	*
	153	* In sparse memory address space, the first
	154	* octant (16MB) of every 128MB segment is
	155	* aliased to the very first 16 MB of the
	156	* address space (i.e., it aliases the ISA
	157	* memory address space). Thus, we try to
	158	* avoid allocating PCI devices in that range.
	159	* Can be allocated in 2nd-7th octant only.
	160	* Devices that need more than 112MB of
	161	* address space must be accessed through
	162	* dense memory space only!
	163	*/
	164
	165	/* Align to multiple of size of minimum base. */
5f0e3da6	166	alignto = max_t(resource_size_t, 0x1000, align);
1da177e4 LT	167	start = ALIGN(start, alignto);
	168	if (hose->sparse_mem_base && size <= 7 * 16*MB) {
	169	if (((start / (16*MB)) & 0x7) == 0) {
	170	start &= ~(128*MB - 1);
	171	start += 16*MB;
	172	start = ALIGN(start, alignto);
	173	}
	174	if (start/(128MB) != (start + size - 1)/(128MB)) {
	175	start &= ~(128*MB - 1);
	176	start += (128 + 16)*MB;
	177	start = ALIGN(start, alignto);
	178	}
	179	}
	180	}
	181
b26b2d49	182	return start;
1da177e4 LT	183	}
	184	#undef KB
	185	#undef MB
	186	#undef GB
	187
	188	static int __init
	189	pcibios_init(void)
	190	{
	191	if (alpha_mv.init_pci)
	192	alpha_mv.init_pci();
	193	return 0;
	194	}
	195
	196	subsys_initcall(pcibios_init);
	197
1da177e4 LT	198	#ifdef ALPHA_RESTORE_SRM_SETUP
	199	static struct pdev_srm_saved_conf *srm_saved_configs;
	200
f8d6c8d9	201	void pdev_save_srm_config(struct pci_dev *dev)
1da177e4 LT	202	{
	203	struct pdev_srm_saved_conf *tmp;
	204	static int printed = 0;
	205
151d16d5	206	if (!alpha_using_srm \|\| pci_has_flag(PCI_PROBE_ONLY))
1da177e4 LT	207	return;
	208
	209	if (!printed) {
	210	printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
	211	printed = 1;
	212	}
	213
	214	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
	215	if (!tmp) {
bbb8d343	216	printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
1da177e4 LT	217	return;
	218	}
	219	tmp->next = srm_saved_configs;
	220	tmp->dev = dev;
	221
	222	pci_save_state(dev);
	223
	224	srm_saved_configs = tmp;
	225	}
	226
	227	void
	228	pci_restore_srm_config(void)
	229	{
	230	struct pdev_srm_saved_conf *tmp;
	231
	232	/* No need to restore if probed only. */
151d16d5	233	if (pci_has_flag(PCI_PROBE_ONLY))
1da177e4 LT	234	return;
	235
	236	/* Restore SRM config. */
	237	for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
	238	pci_restore_state(tmp->dev);
	239	}
	240	}
	241	#endif
	242
f8d6c8d9	243	void pcibios_fixup_bus(struct pci_bus *bus)
1da177e4	244	{
1da177e4 LT	245	struct pci_dev *dev = bus->self;
1da177e4 LT	246
151d16d5	247	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
1da177e4 LT	248	(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1da177e4 LT	249	pci_read_bridge_bases(bus);
1da177e4 LT	250	}
	251
	252	list_for_each_entry(dev, &bus->devices, bus_list) {
	253	pdev_save_srm_config(dev);
1da177e4 LT	254	}
	255	}
	256
1da177e4 LT	257	int
	258	pcibios_enable_device(struct pci_dev *dev, int mask)
	259	{
10f000a2	260	return pci_enable_resources(dev, mask);
1da177e4 LT	261	}
	262
	263	/*
	264	* If we set up a device for bus mastering, we need to check the latency
	265	* timer as certain firmware forgets to set it properly, as seen
	266	* on SX164 and LX164 with SRM.
	267	*/
	268	void
	269	pcibios_set_master(struct pci_dev *dev)
	270	{
	271	u8 lat;
	272	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	273	if (lat >= 16) return;
	274	printk("PCI: Setting latency timer of device %s to 64\n",
	275	pci_name(dev));
	276	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	277	}
	278
72cff123	279	void __init
1da177e4 LT	280	pcibios_claim_one_bus(struct pci_bus *b)
	281	{
	282	struct pci_dev *dev;
	283	struct pci_bus *child_bus;
	284
	285	list_for_each_entry(dev, &b->devices, bus_list) {
	286	int i;
	287
	288	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	289	struct resource *r = &dev->resource[i];
	290
	291	if (r->parent \|\| !r->start \|\| !r->flags)
	292	continue;
151d16d5 BH	293	if (pci_has_flag(PCI_PROBE_ONLY) \|\|
151d16d5 BH	294	(r->flags & IORESOURCE_PCI_FIXED))
72cff123	295	pci_claim_resource(dev, i);
1da177e4 LT	296	}
	297	}
	298
	299	list_for_each_entry(child_bus, &b->children, node)
	300	pcibios_claim_one_bus(child_bus);
	301	}
	302
	303	static void __init
	304	pcibios_claim_console_setup(void)
	305	{
	306	struct pci_bus *b;
	307
	308	list_for_each_entry(b, &pci_root_buses, node)
	309	pcibios_claim_one_bus(b);
	310	}
	311
	312	void __init
	313	common_init_pci(void)
	314	{
	315	struct pci_controller *hose;
a2f33da1	316	struct list_head resources;
1da177e4 LT	317	struct pci_bus *bus;
	318	int next_busno;
	319	int need_domain_info = 0;
a2f33da1 BH	320	u32 pci_mem_end;
	321	u32 sg_base;
	322	unsigned long end;
1da177e4 LT	323
	324	/* Scan all of the recorded PCI controllers. */
	325	for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
a2f33da1 BH	326	sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
	327
	328	/* Adjust hose mem_space limit to prevent PCI allocations
	329	in the iommu windows. */
	330	pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
	331	end = hose->mem_space->start + pci_mem_end;
	332	if (hose->mem_space->end > end)
	333	hose->mem_space->end = end;
	334
	335	INIT_LIST_HEAD(&resources);
c04d9e35 BH	336	pci_add_resource_offset(&resources, hose->io_space,
	337	hose->io_space->start);
	338	pci_add_resource_offset(&resources, hose->mem_space,
	339	hose->mem_space->start);
a2f33da1 BH	340
	341	bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops,
	342	hose, &resources);
1da177e4 LT	343	hose->bus = bus;
1da177e4 LT	344	hose->need_domain_info = need_domain_info;
b918c62e	345	next_busno = bus->busn_res.end + 1;
1da177e4 LT	346	/* Don't allow 8-bit bus number overflow inside the hose -
	347	reserve some space for bridges. */
	348	if (next_busno > 224) {
	349	next_busno = 0;
	350	need_domain_info = 1;
	351	}
	352	}
	353
72cff123	354	pcibios_claim_console_setup();
1da177e4 LT	355
	356	pci_assign_unassigned_resources();
	357	pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
	358	}
	359
	360
	361	struct pci_controller * __init
	362	alloc_pci_controller(void)
	363	{
	364	struct pci_controller *hose;
	365
	366	hose = alloc_bootmem(sizeof(*hose));
	367
	368	*hose_tail = hose;
	369	hose_tail = &hose->next;
	370
	371	return hose;
	372	}
	373
	374	struct resource * __init
	375	alloc_resource(void)
	376	{
	377	struct resource *res;
	378
	379	res = alloc_bootmem(sizeof(*res));
	380
	381	return res;
	382	}
	383
	384
	385	/* Provide information on locations of various I/O regions in physical
	386	memory. Do this on a per-card basis so that we choose the right hose. */
	387
	388	asmlinkage long
	389	sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
	390	{
	391	struct pci_controller *hose;
	392	struct pci_dev *dev;
	393
	394	/* from hose or from bus.devfn */
	395	if (which & IOBASE_FROM_HOSE) {
	396	for(hose = hose_head; hose; hose = hose->next)
	397	if (hose->index == bus) break;
	398	if (!hose) return -ENODEV;
	399	} else {
	400	/* Special hook for ISA access. */
	401	if (bus == 0 && dfn == 0) {
	402	hose = pci_isa_hose;
	403	} else {
074cec54	404	dev = pci_get_bus_and_slot(bus, dfn);
1da177e4 LT	405	if (!dev)
	406	return -ENODEV;
	407	hose = dev->sysdata;
074cec54	408	pci_dev_put(dev);
1da177e4 LT	409	}
	410	}
	411
	412	switch (which & ~IOBASE_FROM_HOSE) {
	413	case IOBASE_HOSE:
	414	return hose->index;
	415	case IOBASE_SPARSE_MEM:
	416	return hose->sparse_mem_base;
	417	case IOBASE_DENSE_MEM:
	418	return hose->dense_mem_base;
	419	case IOBASE_SPARSE_IO:
	420	return hose->sparse_io_base;
	421	case IOBASE_DENSE_IO:
	422	return hose->dense_io_base;
	423	case IOBASE_ROOT_BUS:
	424	return hose->bus->number;
	425	}
	426
	427	return -EOPNOTSUPP;
	428	}
	429
f2971c4c	430	/* Destroy an __iomem token. Not copied from lib/iomap.c. */
1da177e4 LT	431
	432	void pci_iounmap(struct pci_dev dev, void __iomem addr)
	433	{
	434	if (__is_mmio(addr))
	435	iounmap(addr);
	436	}
	437
1da177e4	438	EXPORT_SYMBOL(pci_iounmap);
8255cf35 AB	439
	440	/* FIXME: Some boxes have multiple ISA bridges! */
	441	struct pci_dev *isa_bridge;
	442	EXPORT_SYMBOL(isa_bridge);