projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / blame
| Commit | Line | Data |
|---|---|---|
| 61ab1a90 JI |
1 | * UART (Universal Asynchronous Receiver/Transmitter) |
| 2 | ||
| 3 | Required properties: | |
| 4 | - compatible : one of: | |
| 5 | - "ns8250" | |
| 6 | - "ns16450" | |
| 7 | - "ns16550a" | |
| 8 | - "ns16550" | |
| 9 | - "ns16750" | |
| 10 | - "ns16850" | |
| 193c9d23 PW |
11 | - For Tegra20, must contain "nvidia,tegra20-uart" |
| 12 | - For other Tegra, must contain '"nvidia,<chip>-uart", | |
| 13 | "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124, | |
| 14 | tegra132, or tegra210. | |
| e4305f0c | 15 | - "nxp,lpc3220-uart" |
| a7ae7f82 | 16 | - "ralink,rt2880-uart" |
| 785704d2 SW |
17 | - For MediaTek BTIF, must contain '"mediatek,<chip>-btif", |
| 18 | "mediatek,mtk-btif"' where <chip> is mt7622, mt7623. | |
| e06c93ca LFT |
19 | - "altr,16550-FIFO32" |
| 20 | - "altr,16550-FIFO64" | |
| 21 | - "altr,16550-FIFO128" | |
| 7d480ef7 | 22 | - "fsl,16550-FIFO64" |
| ce4ee580 | 23 | - "fsl,ns16550" |
| b2ae93e0 | 24 | - "ti,da830-uart" |
| 7fbcf3af JK |
25 | - "aspeed,ast2400-vuart" |
| 26 | - "aspeed,ast2500-vuart" | |
| cbf733ca | 27 | - "nuvoton,npcm750-uart" |
| 61ab1a90 JI |
28 | - "serial" if the port type is unknown. |
| 29 | - reg : offset and length of the register set for the device. | |
| 30 | - interrupts : should contain uart interrupt. | |
| ab72fa55 MK |
31 | - clock-frequency : the input clock frequency for the UART |
| 32 | or | |
| 33 | clocks phandle to refer to the clk used as per Documentation/devicetree | |
| 34 | /bindings/clock/clock-bindings.txt | |
| 61ab1a90 JI |
35 | |
| 36 | Optional properties: | |
| 37 | - current-speed : the current active speed of the UART. | |
| 38 | - reg-offset : offset to apply to the mapbase from the start of the registers. | |
| 39 | - reg-shift : quantity to shift the register offsets by. | |
| 7423734e JI |
40 | - reg-io-width : the size (in bytes) of the IO accesses that should be |
| 41 | performed on the device. There are some systems that require 32-bit | |
| 42 | accesses to the UART (e.g. TI davinci). | |
| 61ab1a90 JI |
43 | - used-by-rtas : set to indicate that the port is in use by the OpenFirmware |
| 44 | RTAS and should not be registered. | |
| fde8be29 GJ |
45 | - no-loopback-test: set to indicate that the port does not implements loopback |
| 46 | test mode | |
| 9f1ca068 | 47 | - fifo-size: the fifo size of the UART. |
| b0b8c84c HK |
48 | - auto-flow-control: one way to enable automatic flow control support. The |
| 49 | driver is allowed to detect support for the capability even without this | |
| 50 | property. | |
| 51311eaa TT |
51 | - tx-threshold: Specify the TX FIFO low water indication for parts with |
| 52 | programmable TX FIFO thresholds. | |
| e2860e1f | 53 | - resets : phandle + reset specifier pairs |
| 61ab1a90 | 54 | |
| ce4ee580 BS |
55 | Note: |
| 56 | * fsl,ns16550: | |
| 57 | ------------ | |
| 58 | Freescale DUART is very similar to the PC16552D (and to a | |
| 59 | pair of NS16550A), albeit with some nonstandard behavior such as | |
| 60 | erratum A-004737 (relating to incorrect BRK handling). | |
| 61 | ||
| 62 | Represents a single port that is compatible with the DUART found | |
| 63 | on many Freescale chips (examples include mpc8349, mpc8548, | |
| 64 | mpc8641d, p4080 and ls2085a). | |
| 65 | ||
| 61ab1a90 JI |
66 | Example: |
| 67 | ||
| 68 | uart@80230000 { | |
| 69 | compatible = "ns8250"; | |
| 70 | reg = <0x80230000 0x100>; | |
| 71 | clock-frequency = <3686400>; | |
| 72 | interrupts = <10>; | |
| 73 | reg-shift = <2>; | |
| 74 | }; |