Commit | Line | Data |
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c156633f SS |
1 | * Renesas Electronics Ethernet AVB |
2 | ||
3 | This file provides information on what the device node for the Ethernet AVB | |
4 | interface contains. | |
5 | ||
6 | Required properties: | |
b3a703c7 BD |
7 | - compatible: Must contain one or more of the following: |
8 | - "renesas,etheravb-r8a7743" for the R8A7743 SoC. | |
22cb7a3a | 9 | - "renesas,etheravb-r8a7745" for the R8A7745 SoC. |
b3a703c7 BD |
10 | - "renesas,etheravb-r8a7790" for the R8A7790 SoC. |
11 | - "renesas,etheravb-r8a7791" for the R8A7791 SoC. | |
12 | - "renesas,etheravb-r8a7792" for the R8A7792 SoC. | |
13 | - "renesas,etheravb-r8a7793" for the R8A7793 SoC. | |
14 | - "renesas,etheravb-r8a7794" for the R8A7794 SoC. | |
15 | - "renesas,etheravb-rcar-gen2" as a fallback for the above | |
16 | R-Car Gen2 and RZ/G1 devices. | |
0e874361 | 17 | |
b3a703c7 BD |
18 | - "renesas,etheravb-r8a7795" for the R8A7795 SoC. |
19 | - "renesas,etheravb-r8a7796" for the R8A7796 SoC. | |
20 | - "renesas,etheravb-rcar-gen3" as a fallback for the above | |
21 | R-Car Gen3 devices. | |
22 | ||
23 | When compatible with the generic version, nodes must list the | |
24 | SoC-specific version corresponding to the platform first followed by | |
25 | the generic version. | |
0e874361 | 26 | |
c156633f | 27 | - reg: offset and length of (1) the register block and (2) the stream buffer. |
619f3bd2 KM |
28 | - interrupts: A list of interrupt-specifiers, one for each entry in |
29 | interrupt-names. | |
30 | If interrupt-names is not present, an interrupt specifier | |
31 | for a single muxed interrupt. | |
c156633f SS |
32 | - phy-mode: see ethernet.txt file in the same directory. |
33 | - phy-handle: see ethernet.txt file in the same directory. | |
34 | - #address-cells: number of address cells for the MDIO bus, must be equal to 1. | |
35 | - #size-cells: number of size cells on the MDIO bus, must be equal to 0. | |
36 | - clocks: clock phandle and specifier pair. | |
37 | - pinctrl-0: phandle, referring to a default pin configuration node. | |
38 | ||
39 | Optional properties: | |
40 | - interrupt-parent: the phandle for the interrupt controller that services | |
41 | interrupts for this device. | |
619f3bd2 | 42 | - interrupt-names: A list of interrupt names. |
ed2eb0fb | 43 | For the R8A779[56] SoCs this property is mandatory; |
619f3bd2 KM |
44 | it should include one entry per channel, named "ch%u", |
45 | where %u is the channel number ranging from 0 to 24. | |
46 | For other SoCs this property is optional; if present | |
47 | it should contain "mux" for a single muxed interrupt. | |
c156633f SS |
48 | - pinctrl-names: pin configuration state name ("default"). |
49 | - renesas,no-ether-link: boolean, specify when a board does not provide a proper | |
50 | AVB_LINK signal. | |
51 | - renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is | |
52 | active-low instead of normal active-high. | |
53 | ||
54 | Example: | |
55 | ||
56 | ethernet@e6800000 { | |
0e874361 | 57 | compatible = "renesas,etheravb-r8a7795", "renesas,etheravb-rcar-gen3"; |
619f3bd2 | 58 | reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; |
c156633f | 59 | interrupt-parent = <&gic>; |
619f3bd2 KM |
60 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
61 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
62 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
63 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
64 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | |
65 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
66 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
67 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | |
68 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
69 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
70 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
71 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | |
72 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
73 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
74 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
75 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
76 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
77 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
78 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
79 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
80 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
81 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
82 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, | |
83 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, | |
84 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
85 | interrupt-names = "ch0", "ch1", "ch2", "ch3", | |
86 | "ch4", "ch5", "ch6", "ch7", | |
87 | "ch8", "ch9", "ch10", "ch11", | |
88 | "ch12", "ch13", "ch14", "ch15", | |
89 | "ch16", "ch17", "ch18", "ch19", | |
90 | "ch20", "ch21", "ch22", "ch23", | |
91 | "ch24"; | |
705bcdda GU |
92 | clocks = <&cpg CPG_MOD 812>; |
93 | power-domains = <&cpg>; | |
619f3bd2 | 94 | phy-mode = "rgmii-id"; |
c156633f | 95 | phy-handle = <&phy0>; |
619f3bd2 | 96 | |
c156633f SS |
97 | pinctrl-0 = <ðer_pins>; |
98 | pinctrl-names = "default"; | |
99 | renesas,no-ether-link; | |
100 | #address-cells = <1>; | |
101 | #size-cells = <0>; | |
102 | ||
103 | phy0: ethernet-phy@0 { | |
619f3bd2 KM |
104 | rxc-skew-ps = <900>; |
105 | rxdv-skew-ps = <0>; | |
106 | rxd0-skew-ps = <0>; | |
107 | rxd1-skew-ps = <0>; | |
108 | rxd2-skew-ps = <0>; | |
109 | rxd3-skew-ps = <0>; | |
110 | txc-skew-ps = <900>; | |
111 | txen-skew-ps = <0>; | |
112 | txd0-skew-ps = <0>; | |
113 | txd1-skew-ps = <0>; | |
114 | txd2-skew-ps = <0>; | |
115 | txd3-skew-ps = <0>; | |
c156633f SS |
116 | reg = <0>; |
117 | interrupt-parent = <&gpio2>; | |
619f3bd2 | 118 | interrupts = <11 IRQ_TYPE_LEVEL_LOW>; |
c156633f SS |
119 | }; |
120 | }; |