[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / Documentation / devicetree / bindings / gpio / gpio-mvebu.txt

* Marvell EBU GPIO controller

Required properties:

- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
  370. "marvell,mv78200-gpio" should be used for the Discovery
  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
  SoCs (MV78230, MV78260, MV78460).

- reg: Address and length of the register set for the device. Only one
  entry is expected, except for the "marvell,armadaxp-gpio" variant
  for which two entries are expected: one for the general registers,
  one for the per-cpu registers.

- interrupts: The list of interrupts that are used for all the pins
  managed by this GPIO bank. There can be more than one interrupt
  (example: 1 interrupt per 8 pins on Armada XP, which means 4
  interrupts per bank of 32 GPIOs).

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: specifies the number of cells needed to encode an
  interrupt source. Should be two.
  The first cell is the GPIO number.
  The second cell is used to specify flags:
    bits[3:0] trigger type and level flags:
      1 = low-to-high edge triggered.
      2 = high-to-low edge triggered.
      4 = active high level-sensitive.
      8 = active low level-sensitive.

- gpio-controller: marks the device node as a gpio controller

- ngpios: number of GPIOs this controller has

- #gpio-cells: Should be two. The first cell is the pin number. The
  second cell is reserved for flags, unused at the moment.

Optional properties:

In order to use the GPIO lines in PWM mode, some additional optional
properties are required.

- compatible: Must contain "marvell,armada-370-gpio"

- reg: an additional register set is needed, for the GPIO Blink
  Counter on/off registers.

- reg-names: Must contain an entry "pwm" corresponding to the
  additional register range needed for PWM operation.

- #pwm-cells: Should be two. The first cell is the GPIO line number. The
  second cell is the period in nanoseconds.

- clocks: Must be a phandle to the clock for the GPIO controller.

Example:

		gpio0: gpio@d0018100 {
			compatible = "marvell,armadaxp-gpio";
			reg = <0xd0018100 0x40>,
			    <0xd0018800 0x30>;
			ngpios = <32>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <16>, <17>, <18>, <19>;
		};

		gpio1: gpio@18140 {
			compatible = "marvell,armada-370-gpio";
			reg = <0x18140 0x40>, <0x181c8 0x08>;
			reg-names = "gpio", "pwm";
			ngpios = <17>;
			gpio-controller;
			#gpio-cells = <2>;
			#pwm-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <87>, <88>, <89>;
			clocks = <&coreclk 0>;
		};
Commit	Line	Data
3619ac02 TP	1	* Marvell EBU GPIO controller
	2
	3	Required properties:
	4
	5	- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
	6	or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
	7	Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
	8	370. "marvell,mv78200-gpio" should be used for the Discovery
	9	MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
	10	SoCs (MV78230, MV78260, MV78460).
	11
	12	- reg: Address and length of the register set for the device. Only one
	13	entry is expected, except for the "marvell,armadaxp-gpio" variant
	14	for which two entries are expected: one for the general registers,
	15	one for the per-cpu registers.
	16
	17	- interrupts: The list of interrupts that are used for all the pins
	18	managed by this GPIO bank. There can be more than one interrupt
	19	(example: 1 interrupt per 8 pins on Armada XP, which means 4
	20	interrupts per bank of 32 GPIOs).
	21
	22	- interrupt-controller: identifies the node as an interrupt controller
	23
	24	- #interrupt-cells: specifies the number of cells needed to encode an
	25	interrupt source. Should be two.
	26	The first cell is the GPIO number.
	27	The second cell is used to specify flags:
	28	bits[3:0] trigger type and level flags:
	29	1 = low-to-high edge triggered.
	30	2 = high-to-low edge triggered.
	31	4 = active high level-sensitive.
	32	8 = active low level-sensitive.
	33
	34	- gpio-controller: marks the device node as a gpio controller
	35
	36	- ngpios: number of GPIOs this controller has
	37
	38	- #gpio-cells: Should be two. The first cell is the pin number. The
	39	second cell is reserved for flags, unused at the moment.
	40
757642f9 AL	41	Optional properties:
	42
	43	In order to use the GPIO lines in PWM mode, some additional optional
6c7515c6	44	properties are required.
757642f9	45
6c7515c6	46	- compatible: Must contain "marvell,armada-370-gpio"
757642f9 AL	47
	48	- reg: an additional register set is needed, for the GPIO Blink
	49	Counter on/off registers.
	50
	51	- reg-names: Must contain an entry "pwm" corresponding to the
	52	additional register range needed for PWM operation.
	53
	54	- #pwm-cells: Should be two. The first cell is the GPIO line number. The
	55	second cell is the period in nanoseconds.
	56
	57	- clocks: Must be a phandle to the clock for the GPIO controller.
	58
3619ac02 TP	59	Example:
	60
	61	gpio0: gpio@d0018100 {
	62	compatible = "marvell,armadaxp-gpio";
	63	reg = <0xd0018100 0x40>,
	64	<0xd0018800 0x30>;
	65	ngpios = <32>;
	66	gpio-controller;
	67	#gpio-cells = <2>;
	68	interrupt-controller;
	69	#interrupt-cells = <2>;
	70	interrupts = <16>, <17>, <18>, <19>;
	71	};
757642f9 AL	72
757642f9 AL	73	gpio1: gpio@18140 {
6c7515c6	74	compatible = "marvell,armada-370-gpio";
757642f9 AL	75	reg = <0x18140 0x40>, <0x181c8 0x08>;
	76	reg-names = "gpio", "pwm";
	77	ngpios = <17>;
	78	gpio-controller;
	79	#gpio-cells = <2>;
	80	#pwm-cells = <2>;
	81	interrupt-controller;
	82	#interrupt-cells = <2>;
	83	interrupts = <87>, <88>, <89>;
	84	clocks = <&coreclk 0>;
	85	};