[GitHub/mt8127/android_kernel_alcatel_ttab.git] / Documentation / arm / Samsung-S3C24XX / CPUfreq.txt

		S3C24XX CPUfreq support
		=======================

Introduction
------------

 The S3C24XX series support a number of power saving systems, such as
 the ability to change the core, memory and peripheral operating
 frequencies. The core control is exported via the CPUFreq driver
 which has a number of different manual or automatic controls over the
 rate the core is running at.

 There are two forms of the driver depending on the specific CPU and
 how the clocks are arranged. The first implementation used as single
 PLL to feed the ARM, memory and peripherals via a series of dividers
 and muxes and this is the implementation that is documented here. A
 newer version where there is a separate PLL and clock divider for the
 ARM core is available as a separate driver.


Layout
------

 The code core manages the CPU specific drivers, any data that they
 need to register and the interface to the generic drivers/cpufreq
 system. Each CPU registers a driver to control the PLL, clock dividers
 and anything else associated with it. Any board that wants to use this
 framework needs to supply at least basic details of what is required.

 The core registers with drivers/cpufreq at init time if all the data
 necessary has been supplied.


CPU support
-----------

 The support for each CPU depends on the facilities provided by the
 SoC and the driver as each device has different PLL and clock chains
 associated with it.


Slow Mode
---------

 The SLOW mode where the PLL is turned off altogether and the
 system is fed by the external crystal input is currently not
 supported.


sysfs
-----

 The core code exports extra information via sysfs in the directory
 devices/system/cpu/cpu0/arch-freq.


Board Support
-------------

 Each board that wants to use the cpufreq code must register some basic
 information with the core driver to provide information about what the
 board requires and any restrictions being placed on it.

 The board needs to supply information about whether it needs the IO bank
 timings changing, any maximum frequency limits and information about the
 SDRAM refresh rate.


Document Author
---------------

Ben Dooks, Copyright 2009 Simtec Electronics
Licensed under GPLv2
Commit	Line	Data
dfff4e95 BD	1	S3C24XX CPUfreq support
	2	=======================
	3
	4	Introduction
	5	------------
	6
	7	The S3C24XX series support a number of power saving systems, such as
	8	the ability to change the core, memory and peripheral operating
	9	frequencies. The core control is exported via the CPUFreq driver
	10	which has a number of different manual or automatic controls over the
	11	rate the core is running at.
	12
	13	There are two forms of the driver depending on the specific CPU and
	14	how the clocks are arranged. The first implementation used as single
	15	PLL to feed the ARM, memory and peripherals via a series of dividers
	16	and muxes and this is the implementation that is documented here. A
3ad2f3fb DM	17	newer version where there is a separate PLL and clock divider for the
3ad2f3fb DM	18	ARM core is available as a separate driver.
dfff4e95 BD	19
	20
	21	Layout
	22	------
	23
	24	The code core manages the CPU specific drivers, any data that they
	25	need to register and the interface to the generic drivers/cpufreq
	26	system. Each CPU registers a driver to control the PLL, clock dividers
	27	and anything else associated with it. Any board that wants to use this
	28	framework needs to supply at least basic details of what is required.
	29
	30	The core registers with drivers/cpufreq at init time if all the data
	31	necessary has been supplied.
	32
	33
	34	CPU support
	35	-----------
	36
	37	The support for each CPU depends on the facilities provided by the
	38	SoC and the driver as each device has different PLL and clock chains
	39	associated with it.
	40
	41
	42	Slow Mode
	43	---------
	44
	45	The SLOW mode where the PLL is turned off altogether and the
	46	system is fed by the external crystal input is currently not
	47	supported.
	48
	49
	50	sysfs
	51	-----
	52
	53	The core code exports extra information via sysfs in the directory
	54	devices/system/cpu/cpu0/arch-freq.
	55
	56
	57	Board Support
	58	-------------
	59
	60	Each board that wants to use the cpufreq code must register some basic
	61	information with the core driver to provide information about what the
	62	board requires and any restrictions being placed on it.
	63
	64	The board needs to supply information about whether it needs the IO bank
	65	timings changing, any maximum frequency limits and information about the
	66	SDRAM refresh rate.
	67
	68
	69
	70
	71	Document Author
	72	---------------
	73
	74	Ben Dooks, Copyright 2009 Simtec Electronics
	75	Licensed under GPLv2