spi/mcspi: allow configuration of pin directions
authorDaniel Mack <zonque@gmail.com>
Sun, 7 Oct 2012 16:19:44 +0000 (18:19 +0200)
committerMark Brown <broonie@opensource.wolfsonmicro.com>
Wed, 17 Oct 2012 07:26:51 +0000 (16:26 +0900)
Allow D0 to be an input and D1 to be an output, configurable via
platform data and a new DT property.

Based on a patch from  Matus Ujhelyi <matus.ujhelyi@streamunlimited.com>

Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Documentation/devicetree/bindings/spi/omap-spi.txt
drivers/spi/spi-omap2-mcspi.c
include/linux/platform_data/spi-omap2-mcspi.h

index 81df374adbb97f53a8c7b8d56cb21e70e5d39cb3..2ef0a6b85653c4dc0ddbd18aac6c958c839f5004 100644 (file)
@@ -6,7 +6,9 @@ Required properties:
   - "ti,omap4-spi" for OMAP4+.
 - ti,spi-num-cs : Number of chipselect supported  by the instance.
 - ti,hwmods: Name of the hwmod associated to the McSPI
-
+- ti,pindir-d0-in-d1-out: Select the D0 pin as input and D1 as
+                         output. The default is D0 as output and
+                         D1 as input.
 
 Example:
 
index 3542fdc664b11abcaecd579b8743b52346453354..51046332677cfe247a476ee4568392a7dbd4d175 100644 (file)
@@ -130,6 +130,7 @@ struct omap2_mcspi {
        struct omap2_mcspi_dma  *dma_channels;
        struct device           *dev;
        struct omap2_mcspi_regs ctx;
+       unsigned int            pin_dir:1;
 };
 
 struct omap2_mcspi_cs {
@@ -765,8 +766,15 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
        /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
         * REVISIT: this controller could support SPI_3WIRE mode.
         */
-       l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
-       l |= OMAP2_MCSPI_CHCONF_DPE0;
+       if (mcspi->pin_dir == MCSPI_PINDIR_D0_OUT_D1_IN) {
+               l &= ~OMAP2_MCSPI_CHCONF_IS;
+               l &= ~OMAP2_MCSPI_CHCONF_DPE1;
+               l |= OMAP2_MCSPI_CHCONF_DPE0;
+       } else {
+               l |= OMAP2_MCSPI_CHCONF_IS;
+               l |= OMAP2_MCSPI_CHCONF_DPE1;
+               l &= ~OMAP2_MCSPI_CHCONF_DPE0;
+       }
 
        /* wordlength */
        l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
@@ -1167,6 +1175,11 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
        master->cleanup = omap2_mcspi_cleanup;
        master->dev.of_node = node;
 
+       dev_set_drvdata(&pdev->dev, master);
+
+       mcspi = spi_master_get_devdata(master);
+       mcspi->master = master;
+
        match = of_match_device(omap_mcspi_of_match, &pdev->dev);
        if (match) {
                u32 num_cs = 1; /* default number of chipselect */
@@ -1175,19 +1188,17 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
                of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
                master->num_chipselect = num_cs;
                master->bus_num = bus_num++;
+               if (of_get_property(node, "ti,pindir-d0-in-d1-out", NULL))
+                       mcspi->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
        } else {
                pdata = pdev->dev.platform_data;
                master->num_chipselect = pdata->num_cs;
                if (pdev->id != -1)
                        master->bus_num = pdev->id;
+               mcspi->pin_dir = pdata->pin_dir;
        }
        regs_offset = pdata->regs_offset;
 
-       dev_set_drvdata(&pdev->dev, master);
-
-       mcspi = spi_master_get_devdata(master);
-       mcspi->master = master;
-
        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (r == NULL) {
                status = -ENODEV;
index a357eb26bd258dfd6a969bf218da86d322f41ba1..ce70f7b5a8e1a0c77fb10b232c10fd405a5a48f1 100644 (file)
@@ -7,9 +7,13 @@
 
 #define OMAP4_MCSPI_REG_OFFSET 0x100
 
+#define MCSPI_PINDIR_D0_OUT_D1_IN      0
+#define MCSPI_PINDIR_D0_IN_D1_OUT      1
+
 struct omap2_mcspi_platform_config {
        unsigned short  num_cs;
        unsigned int regs_offset;
+       unsigned int pin_dir:1;
 };
 
 struct omap2_mcspi_dev_attr {