MIPS: Add support for the 1074K core.
authorSteven J. Hill <sjhill@mips.com>
Tue, 26 Jun 2012 04:11:03 +0000 (04:11 +0000)
committerSteven J. Hill <sjhill@mips.com>
Thu, 13 Sep 2012 20:21:47 +0000 (15:21 -0500)
Signed-off-by: Steven J. Hill <sjhill@mips.com>
arch/mips/include/asm/cpu.h
arch/mips/include/asm/mipsregs.h
arch/mips/kernel/cpu-probe.c
arch/mips/mm/c-r4k.c

index f21b7c04e95a2f70073e087e69d384e53d11862f..20c27501b2a870e768b69744420a5f44d38ab64a 100644 (file)
@@ -94,6 +94,7 @@
 #define PRID_IMP_24KE          0x9600
 #define PRID_IMP_74K           0x9700
 #define PRID_IMP_1004K         0x9900
+#define PRID_IMP_1074K         0x9a00
 #define PRID_IMP_M14KC         0x9c00
 
 /*
index 7f87d824eeb089ca3be7aa4f56efa889ec98c40d..60731ff40f4166ab9f04561e33b36c7cddd7d8d6 100644 (file)
 #define MIPS_CONF4_MMUEXTDEF   (_ULCAST_(3) << 14)
 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 
+#define MIPS_CONF6_SYND                (_ULCAST_(1) << 13)
+
 #define MIPS_CONF7_WII         (_ULCAST_(1) << 31)
 
 #define MIPS_CONF7_RPS         (_ULCAST_(1) << 2)
index 1b51046191e85a77dfb56aa284b96e66b035b083..ed3eaf6409b45ef4d2c46cac0a621e26960ba5a3 100644 (file)
@@ -857,6 +857,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                c->cputype = CPU_1004K;
                __cpu_name[cpu] = "MIPS 1004Kc";
                break;
+       case PRID_IMP_1074K:
+               c->cputype = CPU_74K;
+               __cpu_name[cpu] = "MIPS 1074Kc";
+               break;
        }
 
        spram_config();
index f092c265dc6360a89403ac62c184b7f4ab417437..4c32ede464b555defb4c2ecfce4441b54cda39a3 100644 (file)
@@ -786,6 +786,25 @@ static inline void rm7k_erratum31(void)
        }
 }
 
+static inline void alias_74k_erratum(struct cpuinfo_mips *c)
+{
+       /*
+        * Early versions of the 74K do not update the cache tags on a
+        * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
+        * aliases. In this case it is better to treat the cache as always
+        * having aliases.
+        */
+       if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
+               c->dcache.flags |= MIPS_CACHE_VTAG;
+       if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
+               write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+       if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
+           ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
+               c->dcache.flags |= MIPS_CACHE_VTAG;
+               write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+       }
+}
+
 static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
        "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 };
@@ -1056,6 +1075,8 @@ static void __cpuinit probe_pcache(void)
        case CPU_34K:
        case CPU_74K:
        case CPU_1004K:
+               if (c->cputype == CPU_74K)
+                       alias_74k_erratum(c);
                if ((read_c0_config7() & (1 << 16))) {
                        /* effectively physically indexed dcache,
                           thus no virtual aliases. */