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[PATCH] au1xxx: oss sound support for au1200
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / oss / au1550_ac97.c
CommitLineData
1da177e4
LT		 1/*
2 * au1550_ac97.c -- Sound driver for Alchemy Au1550 MIPS Internet Edge
3 * Processor.
4 *
5 * Copyright 2004 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * Mostly copied from the au1000.c driver and some from the
9 * PowerMac dbdma driver.
10 * We assume the processor can do memory coherent DMA.
11 *
12 * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
22 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 */
35
36#undef DEBUG
37
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/string.h>
40#include <linux/ioport.h>
41#include <linux/sched.h>
42#include <linux/delay.h>
43#include <linux/sound.h>
44#include <linux/slab.h>
45#include <linux/soundcard.h>
46#include <linux/init.h>
47#include <linux/interrupt.h>
48#include <linux/kernel.h>
49#include <linux/poll.h>
50#include <linux/pci.h>
51#include <linux/bitops.h>
52#include <linux/spinlock.h>
53#include <linux/smp_lock.h>
54#include <linux/ac97_codec.h>
910f5d20
IM		 55#include <linux/mutex.h>
56
1da177e4
LT		 57#include <asm/io.h>
58#include <asm/uaccess.h>
59#include <asm/hardirq.h>
1da177e4
LT		 60#include <asm/mach-au1x00/au1xxx_psc.h>
61#include <asm/mach-au1x00/au1xxx_dbdma.h>
f2c780c1 62#include <asm/mach-au1x00/au1xxx.h>
1da177e4
LT		 63
64#undef OSS_DOCUMENTED_MIXER_SEMANTICS
65
66/* misc stuff */
67#define POLL_COUNT 0x50000
68#define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
69
70/* The number of DBDMA ring descriptors to allocate. No sense making
71 * this too large....if you can't keep up with a few you aren't likely
72 * to be able to with lots of them, either.
73 */
74#define NUM_DBDMA_DESCRIPTORS 4
75
76#define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
77
78/* Boot options
79 * 0 = no VRA, 1 = use VRA if codec supports it
80 */
81static int vra = 1;
8d3b33f6 82module_param(vra, bool, 0);
1da177e4
LT		 83MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
84
85static struct au1550_state {
86 /* soundcore stuff */
87 int dev_audio;
88
89 struct ac97_codec *codec;
90 unsigned codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
91 unsigned codec_ext_caps; /* AC'97 reg 28h, "Extended Audio ID" */
92 int no_vra; /* do not use VRA */
93
94 spinlock_t lock;
910f5d20
IM		 95 struct mutex open_mutex;
96 struct mutex sem;
1da177e4
LT		 97 mode_t open_mode;
98 wait_queue_head_t open_wait;
99
100 struct dmabuf {
101 u32 dmanr;
102 unsigned sample_rate;
103 unsigned src_factor;
104 unsigned sample_size;
105 int num_channels;
106 int dma_bytes_per_sample;
107 int user_bytes_per_sample;
108 int cnt_factor;
109
110 void *rawbuf;
111 unsigned buforder;
112 unsigned numfrag;
113 unsigned fragshift;
114 void *nextIn;
115 void *nextOut;
116 int count;
117 unsigned total_bytes;
118 unsigned error;
119 wait_queue_head_t wait;
120
121 /* redundant, but makes calculations easier */
122 unsigned fragsize;
123 unsigned dma_fragsize;
124 unsigned dmasize;
125 unsigned dma_qcount;
126
127 /* OSS stuff */
128 unsigned mapped:1;
129 unsigned ready:1;
130 unsigned stopped:1;
131 unsigned ossfragshift;
132 int ossmaxfrags;
133 unsigned subdivision;
134 } dma_dac, dma_adc;
135} au1550_state;
136
137static unsigned
138ld2(unsigned int x)
139{
140 unsigned r = 0;
141
142 if (x >= 0x10000) {
143 x >>= 16;
144 r += 16;
145 }
146 if (x >= 0x100) {
147 x >>= 8;
148 r += 8;
149 }
150 if (x >= 0x10) {
151 x >>= 4;
152 r += 4;
153 }
154 if (x >= 4) {
155 x >>= 2;
156 r += 2;
157 }
158 if (x >= 2)
159 r++;
160 return r;
161}
162
163static void
164au1550_delay(int msec)
165{
166 unsigned long tmo;
167 signed long tmo2;
168
169 if (in_interrupt())
170 return;
171
172 tmo = jiffies + (msec * HZ) / 1000;
173 for (;;) {
174 tmo2 = tmo - jiffies;
175 if (tmo2 <= 0)
176 break;
177 schedule_timeout(tmo2);
178 }
179}
180
181static u16
182rdcodec(struct ac97_codec *codec, u8 addr)
183{
184 struct au1550_state *s = (struct au1550_state *)codec->private_data;
185 unsigned long flags;
186 u32 cmd, val;
187 u16 data;
188 int i;
189
190 spin_lock_irqsave(&s->lock, flags);
191
192 for (i = 0; i < POLL_COUNT; i++) {
193 val = au_readl(PSC_AC97STAT);
194 au_sync();
195 if (!(val & PSC_AC97STAT_CP))
196 break;
197 }
198 if (i == POLL_COUNT)
199 err("rdcodec: codec cmd pending expired!");
200
201 cmd = (u32)PSC_AC97CDC_INDX(addr);
202 cmd |= PSC_AC97CDC_RD; /* read command */
203 au_writel(cmd, PSC_AC97CDC);
204 au_sync();
205
206 /* now wait for the data
207 */
208 for (i = 0; i < POLL_COUNT; i++) {
209 val = au_readl(PSC_AC97STAT);
210 au_sync();
211 if (!(val & PSC_AC97STAT_CP))
212 break;
213 }
214 if (i == POLL_COUNT) {
215 err("rdcodec: read poll expired!");
5e37ed37
DP		 216 data = 0;
217 goto out;
1da177e4
LT		 218 }
219
220 /* wait for command done?
221 */
222 for (i = 0; i < POLL_COUNT; i++) {
223 val = au_readl(PSC_AC97EVNT);
224 au_sync();
225 if (val & PSC_AC97EVNT_CD)
226 break;
227 }
228 if (i == POLL_COUNT) {
229 err("rdcodec: read cmdwait expired!");
5e37ed37
DP		 230 data = 0;
231 goto out;
1da177e4
LT		 232 }
233
234 data = au_readl(PSC_AC97CDC) & 0xffff;
235 au_sync();
236
237 /* Clear command done event.
238 */
239 au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
240 au_sync();
241
5e37ed37 242 out:
1da177e4
LT		 243 spin_unlock_irqrestore(&s->lock, flags);
244
245 return data;
246}
247
248
249static void
250wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
251{
252 struct au1550_state *s = (struct au1550_state *)codec->private_data;
253 unsigned long flags;
254 u32 cmd, val;
255 int i;
256
257 spin_lock_irqsave(&s->lock, flags);
258
259 for (i = 0; i < POLL_COUNT; i++) {
260 val = au_readl(PSC_AC97STAT);
261 au_sync();
262 if (!(val & PSC_AC97STAT_CP))
263 break;
264 }
265 if (i == POLL_COUNT)
266 err("wrcodec: codec cmd pending expired!");
267
268 cmd = (u32)PSC_AC97CDC_INDX(addr);
269 cmd |= (u32)data;
270 au_writel(cmd, PSC_AC97CDC);
271 au_sync();
272
273 for (i = 0; i < POLL_COUNT; i++) {
274 val = au_readl(PSC_AC97STAT);
275 au_sync();
276 if (!(val & PSC_AC97STAT_CP))
277 break;
278 }
279 if (i == POLL_COUNT)
280 err("wrcodec: codec cmd pending expired!");
281
282 for (i = 0; i < POLL_COUNT; i++) {
283 val = au_readl(PSC_AC97EVNT);
284 au_sync();
285 if (val & PSC_AC97EVNT_CD)
286 break;
287 }
288 if (i == POLL_COUNT)
289 err("wrcodec: read cmdwait expired!");
290
291 /* Clear command done event.
292 */
293 au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
294 au_sync();
295
296 spin_unlock_irqrestore(&s->lock, flags);
297}
298
299static void
300waitcodec(struct ac97_codec *codec)
301{
302 u16 temp;
303 u32 val;
304 int i;
305
306 /* codec_wait is used to wait for a ready state after
307 * an AC97C_RESET.
308 */
309 au1550_delay(10);
310
311 /* first poll the CODEC_READY tag bit
312 */
313 for (i = 0; i < POLL_COUNT; i++) {
314 val = au_readl(PSC_AC97STAT);
315 au_sync();
316 if (val & PSC_AC97STAT_CR)
317 break;
318 }
319 if (i == POLL_COUNT) {
320 err("waitcodec: CODEC_READY poll expired!");
321 return;
322 }
323
324 /* get AC'97 powerdown control/status register
325 */
326 temp = rdcodec(codec, AC97_POWER_CONTROL);
327
328 /* If anything is powered down, power'em up
329 */
330 if (temp & 0x7f00) {
331 /* Power on
332 */
333 wrcodec(codec, AC97_POWER_CONTROL, 0);
334 au1550_delay(100);
335
336 /* Reread
337 */
338 temp = rdcodec(codec, AC97_POWER_CONTROL);
339 }
340
341 /* Check if Codec REF,ANL,DAC,ADC ready
342 */
343 if ((temp & 0x7f0f) != 0x000f)
344 err("codec reg 26 status (0x%x) not ready!!", temp);
345}
346
347/* stop the ADC before calling */
348static void
349set_adc_rate(struct au1550_state *s, unsigned rate)
350{
351 struct dmabuf *adc = &s->dma_adc;
352 struct dmabuf *dac = &s->dma_dac;
353 unsigned adc_rate, dac_rate;
354 u16 ac97_extstat;
355
356 if (s->no_vra) {
357 /* calc SRC factor
358 */
359 adc->src_factor = ((96000 / rate) + 1) >> 1;
360 adc->sample_rate = 48000 / adc->src_factor;
361 return;
362 }
363
364 adc->src_factor = 1;
365
366 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
367
368 rate = rate > 48000 ? 48000 : rate;
369
370 /* enable VRA
371 */
372 wrcodec(s->codec, AC97_EXTENDED_STATUS,
373 ac97_extstat | AC97_EXTSTAT_VRA);
374
375 /* now write the sample rate
376 */
377 wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
378
379 /* read it back for actual supported rate
380 */
381 adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
382
383 pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
384
385 /* some codec's don't allow unequal DAC and ADC rates, in which case
386 * writing one rate reg actually changes both.
387 */
388 dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
389 if (dac->num_channels > 2)
390 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
391 if (dac->num_channels > 4)
392 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
393
394 adc->sample_rate = adc_rate;
395 dac->sample_rate = dac_rate;
396}
397
398/* stop the DAC before calling */
399static void
400set_dac_rate(struct au1550_state *s, unsigned rate)
401{
402 struct dmabuf *dac = &s->dma_dac;
403 struct dmabuf *adc = &s->dma_adc;
404 unsigned adc_rate, dac_rate;
405 u16 ac97_extstat;
406
407 if (s->no_vra) {
408 /* calc SRC factor
409 */
410 dac->src_factor = ((96000 / rate) + 1) >> 1;
411 dac->sample_rate = 48000 / dac->src_factor;
412 return;
413 }
414
415 dac->src_factor = 1;
416
417 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
418
419 rate = rate > 48000 ? 48000 : rate;
420
421 /* enable VRA
422 */
423 wrcodec(s->codec, AC97_EXTENDED_STATUS,
424 ac97_extstat | AC97_EXTSTAT_VRA);
425
426 /* now write the sample rate
427 */
428 wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
429
430 /* I don't support different sample rates for multichannel,
431 * so make these channels the same.
432 */
433 if (dac->num_channels > 2)
434 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
435 if (dac->num_channels > 4)
436 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
437 /* read it back for actual supported rate
438 */
439 dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
440
441 pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
442
443 /* some codec's don't allow unequal DAC and ADC rates, in which case
444 * writing one rate reg actually changes both.
445 */
446 adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
447
448 dac->sample_rate = dac_rate;
449 adc->sample_rate = adc_rate;
450}
451
452static void
453stop_dac(struct au1550_state *s)
454{
455 struct dmabuf *db = &s->dma_dac;
456 u32 stat;
457 unsigned long flags;
458
459 if (db->stopped)
460 return;
461
462 spin_lock_irqsave(&s->lock, flags);
463
464 au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
465 au_sync();
466
467 /* Wait for Transmit Busy to show disabled.
468 */
469 do {
05090fc9 470 stat = au_readl(PSC_AC97STAT);
1da177e4
LT		 471 au_sync();
472 } while ((stat & PSC_AC97STAT_TB) != 0);
473
474 au1xxx_dbdma_reset(db->dmanr);
475
476 db->stopped = 1;
477
478 spin_unlock_irqrestore(&s->lock, flags);
479}
480
481static void
482stop_adc(struct au1550_state *s)
483{
484 struct dmabuf *db = &s->dma_adc;
485 unsigned long flags;
486 u32 stat;
487
488 if (db->stopped)
489 return;
490
491 spin_lock_irqsave(&s->lock, flags);
492
493 au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
494 au_sync();
495
496 /* Wait for Receive Busy to show disabled.
497 */
498 do {
05090fc9 499 stat = au_readl(PSC_AC97STAT);
1da177e4
LT		 500 au_sync();
501 } while ((stat & PSC_AC97STAT_RB) != 0);
502
503 au1xxx_dbdma_reset(db->dmanr);
504
505 db->stopped = 1;
506
507 spin_unlock_irqrestore(&s->lock, flags);
508}
509
510
511static void
512set_xmit_slots(int num_channels)
513{
514 u32 ac97_config, stat;
515
516 ac97_config = au_readl(PSC_AC97CFG);
517 au_sync();
518 ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
519 au_writel(ac97_config, PSC_AC97CFG);
520 au_sync();
521
522 switch (num_channels) {
523 case 6: /* stereo with surround and center/LFE,
524 * slots 3,4,6,7,8,9
525 */
526 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
527 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
528
529 case 4: /* stereo with surround, slots 3,4,7,8 */
530 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
531 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
532
533 case 2: /* stereo, slots 3,4 */
534 case 1: /* mono */
535 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
536 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
537 }
538
539 au_writel(ac97_config, PSC_AC97CFG);
540 au_sync();
541
542 ac97_config |= PSC_AC97CFG_DE_ENABLE;
543 au_writel(ac97_config, PSC_AC97CFG);
544 au_sync();
545
546 /* Wait for Device ready.
547 */
548 do {
05090fc9 549 stat = au_readl(PSC_AC97STAT);
1da177e4
LT		 550 au_sync();
551 } while ((stat & PSC_AC97STAT_DR) == 0);
552}
553
554static void
555set_recv_slots(int num_channels)
556{
557 u32 ac97_config, stat;
558
559 ac97_config = au_readl(PSC_AC97CFG);
560 au_sync();
561 ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
562 au_writel(ac97_config, PSC_AC97CFG);
563 au_sync();
564
565 /* Always enable slots 3 and 4 (stereo). Slot 6 is
566 * optional Mic ADC, which we don't support yet.
567 */
568 ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
569 ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
570
571 au_writel(ac97_config, PSC_AC97CFG);
572 au_sync();
573
574 ac97_config |= PSC_AC97CFG_DE_ENABLE;
575 au_writel(ac97_config, PSC_AC97CFG);
576 au_sync();
577
578 /* Wait for Device ready.
579 */
580 do {
05090fc9 581 stat = au_readl(PSC_AC97STAT);
1da177e4
LT		 582 au_sync();
583 } while ((stat & PSC_AC97STAT_DR) == 0);
584}
585
7b666653 586/* Hold spinlock for both start_dac() and start_adc() calls */
1da177e4
LT		 587static void
588start_dac(struct au1550_state *s)
589{
590 struct dmabuf *db = &s->dma_dac;
1da177e4
LT		 591
592 if (!db->stopped)
593 return;
594
1da177e4
LT		 595 set_xmit_slots(db->num_channels);
596 au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
597 au_sync();
598 au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
599 au_sync();
600
601 au1xxx_dbdma_start(db->dmanr);
602
603 db->stopped = 0;
1da177e4
LT		 604}
605
606static void
607start_adc(struct au1550_state *s)
608{
609 struct dmabuf *db = &s->dma_adc;
610 int i;
611
612 if (!db->stopped)
613 return;
614
615 /* Put two buffers on the ring to get things started.
616 */
617 for (i=0; i<2; i++) {
618 au1xxx_dbdma_put_dest(db->dmanr, db->nextIn, db->dma_fragsize);
619
620 db->nextIn += db->dma_fragsize;
621 if (db->nextIn >= db->rawbuf + db->dmasize)
622 db->nextIn -= db->dmasize;
623 }
624
625 set_recv_slots(db->num_channels);
626 au1xxx_dbdma_start(db->dmanr);
627 au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
628 au_sync();
629 au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
630 au_sync();
631
632 db->stopped = 0;
633}
634
635static int
636prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
637{
638 unsigned user_bytes_per_sec;
639 unsigned bufs;
640 unsigned rate = db->sample_rate;
641
642 if (!db->rawbuf) {
643 db->ready = db->mapped = 0;
644 db->buforder = 5; /* 32 * PAGE_SIZE */
645 db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
646 if (!db->rawbuf)
647 return -ENOMEM;
648 }
649
650 db->cnt_factor = 1;
651 if (db->sample_size == 8)
652 db->cnt_factor *= 2;
653 if (db->num_channels == 1)
654 db->cnt_factor *= 2;
655 db->cnt_factor *= db->src_factor;
656
657 db->count = 0;
658 db->dma_qcount = 0;
659 db->nextIn = db->nextOut = db->rawbuf;
660
661 db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
662 db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
663 2 : db->num_channels);
664
665 user_bytes_per_sec = rate * db->user_bytes_per_sample;
666 bufs = PAGE_SIZE << db->buforder;
667 if (db->ossfragshift) {
668 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
669 db->fragshift = ld2(user_bytes_per_sec/1000);
670 else
671 db->fragshift = db->ossfragshift;
672 } else {
673 db->fragshift = ld2(user_bytes_per_sec / 100 /
674 (db->subdivision ? db->subdivision : 1));
675 if (db->fragshift < 3)
676 db->fragshift = 3;
677 }
678
679 db->fragsize = 1 << db->fragshift;
680 db->dma_fragsize = db->fragsize * db->cnt_factor;
681 db->numfrag = bufs / db->dma_fragsize;
682
683 while (db->numfrag < 4 && db->fragshift > 3) {
684 db->fragshift--;
685 db->fragsize = 1 << db->fragshift;
686 db->dma_fragsize = db->fragsize * db->cnt_factor;
687 db->numfrag = bufs / db->dma_fragsize;
688 }
689
690 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
691 db->numfrag = db->ossmaxfrags;
692
693 db->dmasize = db->dma_fragsize * db->numfrag;
694 memset(db->rawbuf, 0, bufs);
695
696 pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
697 rate, db->sample_size, db->num_channels);
698 pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
699 db->fragsize, db->cnt_factor, db->dma_fragsize);
700 pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
701
702 db->ready = 1;
703 return 0;
704}
705
706static int
707prog_dmabuf_adc(struct au1550_state *s)
708{
709 stop_adc(s);
710 return prog_dmabuf(s, &s->dma_adc);
711
712}
713
714static int
715prog_dmabuf_dac(struct au1550_state *s)
716{
717 stop_dac(s);
718 return prog_dmabuf(s, &s->dma_dac);
719}
720
721
1da177e4
LT		 722static void
723dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
724{
725 struct au1550_state *s = (struct au1550_state *) dev_id;
726 struct dmabuf *db = &s->dma_dac;
727 u32 ac97c_stat;
728
7b666653
SS		 729 spin_lock(&s->lock);
730
1da177e4
LT		 731 ac97c_stat = au_readl(PSC_AC97STAT);
732 if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
733 pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
734 db->dma_qcount--;
735
736 if (db->count >= db->fragsize) {
737 if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
738 db->fragsize) == 0) {
739 err("qcount < 2 and no ring room!");
740 }
741 db->nextOut += db->fragsize;
742 if (db->nextOut >= db->rawbuf + db->dmasize)
743 db->nextOut -= db->dmasize;
744 db->count -= db->fragsize;
745 db->total_bytes += db->dma_fragsize;
746 db->dma_qcount++;
747 }
748
749 /* wake up anybody listening */
750 if (waitqueue_active(&db->wait))
751 wake_up(&db->wait);
7b666653
SS		 752
753 spin_unlock(&s->lock);
1da177e4
LT		 754}
755
756
757static void
758adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
759{
760 struct au1550_state *s = (struct au1550_state *)dev_id;
761 struct dmabuf *dp = &s->dma_adc;
762 u32 obytes;
763 char *obuf;
764
7b666653
SS		 765 spin_lock(&s->lock);
766
1da177e4
LT		 767 /* Pull the buffer from the dma queue.
768 */
769 au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
770
771 if ((dp->count + obytes) > dp->dmasize) {
772 /* Overrun. Stop ADC and log the error
773 */
7b666653 774 spin_unlock(&s->lock);
1da177e4
LT		 775 stop_adc(s);
776 dp->error++;
777 err("adc overrun");
778 return;
779 }
780
781 /* Put a new empty buffer on the destination DMA.
782 */
783 au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn, dp->dma_fragsize);
784
785 dp->nextIn += dp->dma_fragsize;
786 if (dp->nextIn >= dp->rawbuf + dp->dmasize)
787 dp->nextIn -= dp->dmasize;
788
789 dp->count += obytes;
790 dp->total_bytes += obytes;
791
792 /* wake up anybody listening
793 */
794 if (waitqueue_active(&dp->wait))
795 wake_up(&dp->wait);
796
7b666653 797 spin_unlock(&s->lock);
1da177e4
LT		 798}
799
800static loff_t
801au1550_llseek(struct file *file, loff_t offset, int origin)
802{
803 return -ESPIPE;
804}
805
806
807static int
808au1550_open_mixdev(struct inode *inode, struct file *file)
809{
810 file->private_data = &au1550_state;
811 return 0;
812}
813
814static int
815au1550_release_mixdev(struct inode *inode, struct file *file)
816{
817 return 0;
818}
819
820static int
821mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
822 unsigned long arg)
823{
824 return codec->mixer_ioctl(codec, cmd, arg);
825}
826
827static int
828au1550_ioctl_mixdev(struct inode *inode, struct file *file,
829 unsigned int cmd, unsigned long arg)
830{
831 struct au1550_state *s = (struct au1550_state *)file->private_data;
832 struct ac97_codec *codec = s->codec;
833
834 return mixdev_ioctl(codec, cmd, arg);
835}
836
837static /*const */ struct file_operations au1550_mixer_fops = {
838 owner:THIS_MODULE,
839 llseek:au1550_llseek,
840 ioctl:au1550_ioctl_mixdev,
841 open:au1550_open_mixdev,
842 release:au1550_release_mixdev,
843};
844
845static int
846drain_dac(struct au1550_state *s, int nonblock)
847{
848 unsigned long flags;
849 int count, tmo;
850
851 if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
852 return 0;
853
854 for (;;) {
855 spin_lock_irqsave(&s->lock, flags);
856 count = s->dma_dac.count;
857 spin_unlock_irqrestore(&s->lock, flags);
858 if (count <= s->dma_dac.fragsize)
859 break;
860 if (signal_pending(current))
861 break;
862 if (nonblock)
863 return -EBUSY;
864 tmo = 1000 * count / (s->no_vra ?
865 48000 : s->dma_dac.sample_rate);
866 tmo /= s->dma_dac.dma_bytes_per_sample;
867 au1550_delay(tmo);
868 }
869 if (signal_pending(current))
870 return -ERESTARTSYS;
871 return 0;
872}
873
874static inline u8 S16_TO_U8(s16 ch)
875{
876 return (u8) (ch >> 8) + 0x80;
877}
878static inline s16 U8_TO_S16(u8 ch)
879{
880 return (s16) (ch - 0x80) << 8;
881}
882
883/*
884 * Translates user samples to dma buffer suitable for AC'97 DAC data:
885 * If mono, copy left channel to right channel in dma buffer.
886 * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
887 * If interpolating (no VRA), duplicate every audio frame src_factor times.
888 */
889static int
890translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
891 int dmacount)
892{
893 int sample, i;
894 int interp_bytes_per_sample;
895 int num_samples;
896 int mono = (db->num_channels == 1);
897 char usersample[12];
898 s16 ch, dmasample[6];
899
900 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
901 /* no translation necessary, just copy
902 */
903 if (copy_from_user(dmabuf, userbuf, dmacount))
904 return -EFAULT;
905 return dmacount;
906 }
907
908 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
909 num_samples = dmacount / interp_bytes_per_sample;
910
911 for (sample = 0; sample < num_samples; sample++) {
912 if (copy_from_user(usersample, userbuf,
913 db->user_bytes_per_sample)) {
914 return -EFAULT;
915 }
916
917 for (i = 0; i < db->num_channels; i++) {
918 if (db->sample_size == 8)
919 ch = U8_TO_S16(usersample[i]);
920 else
921 ch = *((s16 *) (&usersample[i * 2]));
922 dmasample[i] = ch;
923 if (mono)
924 dmasample[i + 1] = ch; /* right channel */
925 }
926
927 /* duplicate every audio frame src_factor times
928 */
929 for (i = 0; i < db->src_factor; i++)
930 memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
931
932 userbuf += db->user_bytes_per_sample;
933 dmabuf += interp_bytes_per_sample;
934 }
935
936 return num_samples * interp_bytes_per_sample;
937}
938
939/*
940 * Translates AC'97 ADC samples to user buffer:
941 * If mono, send only left channel to user buffer.
942 * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
943 * If decimating (no VRA), skip over src_factor audio frames.
944 */
945static int
946translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
947 int dmacount)
948{
949 int sample, i;
950 int interp_bytes_per_sample;
951 int num_samples;
952 int mono = (db->num_channels == 1);
953 char usersample[12];
954
955 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
956 /* no translation necessary, just copy
957 */
958 if (copy_to_user(userbuf, dmabuf, dmacount))
959 return -EFAULT;
960 return dmacount;
961 }
962
963 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
964 num_samples = dmacount / interp_bytes_per_sample;
965
966 for (sample = 0; sample < num_samples; sample++) {
967 for (i = 0; i < db->num_channels; i++) {
968 if (db->sample_size == 8)
969 usersample[i] =
970 S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
971 else
972 *((s16 *) (&usersample[i * 2])) =
973 *((s16 *) (&dmabuf[i * 2]));
974 }
975
976 if (copy_to_user(userbuf, usersample,
977 db->user_bytes_per_sample)) {
978 return -EFAULT;
979 }
980
981 userbuf += db->user_bytes_per_sample;
982 dmabuf += interp_bytes_per_sample;
983 }
984
985 return num_samples * interp_bytes_per_sample;
986}
987
988/*
989 * Copy audio data to/from user buffer from/to dma buffer, taking care
990 * that we wrap when reading/writing the dma buffer. Returns actual byte
991 * count written to or read from the dma buffer.
992 */
993static int
994copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
995{
996 char *bufptr = to_user ? db->nextOut : db->nextIn;
997 char *bufend = db->rawbuf + db->dmasize;
998 int cnt, ret;
999
1000 if (bufptr + count > bufend) {
1001 int partial = (int) (bufend - bufptr);
1002 if (to_user) {
1003 if ((cnt = translate_to_user(db, userbuf,
1004 bufptr, partial)) < 0)
1005 return cnt;
1006 ret = cnt;
1007 if ((cnt = translate_to_user(db, userbuf + partial,
1008 db->rawbuf,
1009 count - partial)) < 0)
1010 return cnt;
1011 ret += cnt;
1012 } else {
1013 if ((cnt = translate_from_user(db, bufptr, userbuf,
1014 partial)) < 0)
1015 return cnt;
1016 ret = cnt;
1017 if ((cnt = translate_from_user(db, db->rawbuf,
1018 userbuf + partial,
1019 count - partial)) < 0)
1020 return cnt;
1021 ret += cnt;
1022 }
1023 } else {
1024 if (to_user)
1025 ret = translate_to_user(db, userbuf, bufptr, count);
1026 else
1027 ret = translate_from_user(db, bufptr, userbuf, count);
1028 }
1029
1030 return ret;
1031}
1032
1033
1034static ssize_t
1035au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1036{
1037 struct au1550_state *s = (struct au1550_state *)file->private_data;
1038 struct dmabuf *db = &s->dma_adc;
1039 DECLARE_WAITQUEUE(wait, current);
1040 ssize_t ret;
1041 unsigned long flags;
1042 int cnt, usercnt, avail;
1043
1044 if (db->mapped)
1045 return -ENXIO;
1046 if (!access_ok(VERIFY_WRITE, buffer, count))
1047 return -EFAULT;
1048 ret = 0;
1049
1050 count *= db->cnt_factor;
1051
910f5d20 1052 mutex_lock(&s->sem);
1da177e4
LT		 1053 add_wait_queue(&db->wait, &wait);
1054
1055 while (count > 0) {
1056 /* wait for samples in ADC dma buffer
1057 */
1058 do {
7b666653 1059 spin_lock_irqsave(&s->lock, flags);
1da177e4
LT		 1060 if (db->stopped)
1061 start_adc(s);
1da177e4
LT		 1062 avail = db->count;
1063 if (avail <= 0)
1064 __set_current_state(TASK_INTERRUPTIBLE);
1065 spin_unlock_irqrestore(&s->lock, flags);
1066 if (avail <= 0) {
1067 if (file->f_flags & O_NONBLOCK) {
1068 if (!ret)
1069 ret = -EAGAIN;
1070 goto out;
1071 }
910f5d20 1072 mutex_unlock(&s->sem);
1da177e4
LT		 1073 schedule();
1074 if (signal_pending(current)) {
1075 if (!ret)
1076 ret = -ERESTARTSYS;
1077 goto out2;
1078 }
910f5d20 1079 mutex_lock(&s->sem);
1da177e4
LT		 1080 }
1081 } while (avail <= 0);
1082
1083 /* copy from nextOut to user
1084 */
1085 if ((cnt = copy_dmabuf_user(db, buffer,
1086 count > avail ?
1087 avail : count, 1)) < 0) {
1088 if (!ret)
1089 ret = -EFAULT;
1090 goto out;
1091 }
1092
1093 spin_lock_irqsave(&s->lock, flags);
1094 db->count -= cnt;
1095 db->nextOut += cnt;
1096 if (db->nextOut >= db->rawbuf + db->dmasize)
1097 db->nextOut -= db->dmasize;
1098 spin_unlock_irqrestore(&s->lock, flags);
1099
1100 count -= cnt;
1101 usercnt = cnt / db->cnt_factor;
1102 buffer += usercnt;
1103 ret += usercnt;
1104 } /* while (count > 0) */
1105
1106out:
910f5d20 1107 mutex_unlock(&s->sem);
1da177e4
LT		 1108out2:
1109 remove_wait_queue(&db->wait, &wait);
1110 set_current_state(TASK_RUNNING);
1111 return ret;
1112}
1113
1114static ssize_t
1115au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
1116{
1117 struct au1550_state *s = (struct au1550_state *)file->private_data;
1118 struct dmabuf *db = &s->dma_dac;
1119 DECLARE_WAITQUEUE(wait, current);
1120 ssize_t ret = 0;
1121 unsigned long flags;
1122 int cnt, usercnt, avail;
1123
1124 pr_debug("write: count=%d\n", count);
1125
1126 if (db->mapped)
1127 return -ENXIO;
1128 if (!access_ok(VERIFY_READ, buffer, count))
1129 return -EFAULT;
1130
1131 count *= db->cnt_factor;
1132
910f5d20 1133 mutex_lock(&s->sem);
1da177e4
LT		 1134 add_wait_queue(&db->wait, &wait);
1135
1136 while (count > 0) {
1137 /* wait for space in playback buffer
1138 */
1139 do {
1140 spin_lock_irqsave(&s->lock, flags);
1141 avail = (int) db->dmasize - db->count;
1142 if (avail <= 0)
1143 __set_current_state(TASK_INTERRUPTIBLE);
1144 spin_unlock_irqrestore(&s->lock, flags);
1145 if (avail <= 0) {
1146 if (file->f_flags & O_NONBLOCK) {
1147 if (!ret)
1148 ret = -EAGAIN;
1149 goto out;
1150 }
910f5d20 1151 mutex_unlock(&s->sem);
1da177e4
LT		 1152 schedule();
1153 if (signal_pending(current)) {
1154 if (!ret)
1155 ret = -ERESTARTSYS;
1156 goto out2;
1157 }
910f5d20 1158 mutex_lock(&s->sem);
1da177e4
LT		 1159 }
1160 } while (avail <= 0);
1161
1162 /* copy from user to nextIn
1163 */
1164 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1165 count > avail ?
1166 avail : count, 0)) < 0) {
1167 if (!ret)
1168 ret = -EFAULT;
1169 goto out;
1170 }
1171
1172 spin_lock_irqsave(&s->lock, flags);
1173 db->count += cnt;
1174 db->nextIn += cnt;
1175 if (db->nextIn >= db->rawbuf + db->dmasize)
1176 db->nextIn -= db->dmasize;
1177
1178 /* If the data is available, we want to keep two buffers
1179 * on the dma queue. If the queue count reaches zero,
1180 * we know the dma has stopped.
1181 */
1182 while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
1183 if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
1184 db->fragsize) == 0) {
1185 err("qcount < 2 and no ring room!");
1186 }
1187 db->nextOut += db->fragsize;
1188 if (db->nextOut >= db->rawbuf + db->dmasize)
1189 db->nextOut -= db->dmasize;
1190 db->total_bytes += db->dma_fragsize;
1191 if (db->dma_qcount == 0)
1192 start_dac(s);
1193 db->dma_qcount++;
1194 }
1195 spin_unlock_irqrestore(&s->lock, flags);
1196
1197 count -= cnt;
1198 usercnt = cnt / db->cnt_factor;
1199 buffer += usercnt;
1200 ret += usercnt;
1201 } /* while (count > 0) */
1202
1203out:
910f5d20 1204 mutex_unlock(&s->sem);
1da177e4
LT		 1205out2:
1206 remove_wait_queue(&db->wait, &wait);
1207 set_current_state(TASK_RUNNING);
1208 return ret;
1209}
1210
1211
1212/* No kernel lock - we have our own spinlock */
1213static unsigned int
1214au1550_poll(struct file *file, struct poll_table_struct *wait)
1215{
1216 struct au1550_state *s = (struct au1550_state *)file->private_data;
1217 unsigned long flags;
1218 unsigned int mask = 0;
1219
1220 if (file->f_mode & FMODE_WRITE) {
1221 if (!s->dma_dac.ready)
1222 return 0;
1223 poll_wait(file, &s->dma_dac.wait, wait);
1224 }
1225 if (file->f_mode & FMODE_READ) {
1226 if (!s->dma_adc.ready)
1227 return 0;
1228 poll_wait(file, &s->dma_adc.wait, wait);
1229 }
1230
1231 spin_lock_irqsave(&s->lock, flags);
1232
1233 if (file->f_mode & FMODE_READ) {
1234 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1235 mask |= POLLIN | POLLRDNORM;
1236 }
1237 if (file->f_mode & FMODE_WRITE) {
1238 if (s->dma_dac.mapped) {
1239 if (s->dma_dac.count >=
1240 (signed)s->dma_dac.dma_fragsize)
1241 mask |= POLLOUT | POLLWRNORM;
1242 } else {
1243 if ((signed) s->dma_dac.dmasize >=
1244 s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1245 mask |= POLLOUT | POLLWRNORM;
1246 }
1247 }
1248 spin_unlock_irqrestore(&s->lock, flags);
1249 return mask;
1250}
1251
1252static int
1253au1550_mmap(struct file *file, struct vm_area_struct *vma)
1254{
1255 struct au1550_state *s = (struct au1550_state *)file->private_data;
1256 struct dmabuf *db;
1257 unsigned long size;
1258 int ret = 0;
1259
1260 lock_kernel();
910f5d20 1261 mutex_lock(&s->sem);
1da177e4
LT		 1262 if (vma->vm_flags & VM_WRITE)
1263 db = &s->dma_dac;
1264 else if (vma->vm_flags & VM_READ)
1265 db = &s->dma_adc;
1266 else {
1267 ret = -EINVAL;
1268 goto out;
1269 }
1270 if (vma->vm_pgoff != 0) {
1271 ret = -EINVAL;
1272 goto out;
1273 }
1274 size = vma->vm_end - vma->vm_start;
1275 if (size > (PAGE_SIZE << db->buforder)) {
1276 ret = -EINVAL;
1277 goto out;
1278 }
1279 if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
1280 size, vma->vm_page_prot)) {
1281 ret = -EAGAIN;
1282 goto out;
1283 }
1284 vma->vm_flags &= ~VM_IO;
1285 db->mapped = 1;
1286out:
910f5d20 1287 mutex_unlock(&s->sem);
1da177e4
LT		 1288 unlock_kernel();
1289 return ret;
1290}
1291
1292#ifdef DEBUG
1293static struct ioctl_str_t {
1294 unsigned int cmd;
1295 const char *str;
1296} ioctl_str[] = {
1297 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1298 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1299 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1300 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1301 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1302 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1303 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1304 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1305 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1306 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1307 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1308 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1309 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1310 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1311 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1312 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1313 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1314 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1315 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1316 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1317 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1318 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1319 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1320 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1321 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1322 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1323 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1324 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1325 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1326 {OSS_GETVERSION, "OSS_GETVERSION"},
1327 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1328 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1329 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1330 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1331};
1332#endif
1333
1334static int
1335dma_count_done(struct dmabuf *db)
1336{
1337 if (db->stopped)
1338 return 0;
1339
1340 return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
1341}
1342
1343
1344static int
1345au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
1346 unsigned long arg)
1347{
1348 struct au1550_state *s = (struct au1550_state *)file->private_data;
1349 unsigned long flags;
1350 audio_buf_info abinfo;
1351 count_info cinfo;
1352 int count;
1353 int val, mapped, ret, diff;
1354
1355 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1356 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1357
1358#ifdef DEBUG
1359 for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
1360 if (ioctl_str[count].cmd == cmd)
1361 break;
1362 }
1363 if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
1364 pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
1365 else
1366 pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
1367#endif
1368
1369 switch (cmd) {
1370 case OSS_GETVERSION:
1371 return put_user(SOUND_VERSION, (int *) arg);
1372
1373 case SNDCTL_DSP_SYNC:
1374 if (file->f_mode & FMODE_WRITE)
1375 return drain_dac(s, file->f_flags & O_NONBLOCK);
1376 return 0;
1377
1378 case SNDCTL_DSP_SETDUPLEX:
1379 return 0;
1380
1381 case SNDCTL_DSP_GETCAPS:
1382 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1383 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1384
1385 case SNDCTL_DSP_RESET:
1386 if (file->f_mode & FMODE_WRITE) {
1387 stop_dac(s);
1388 synchronize_irq();
1389 s->dma_dac.count = s->dma_dac.total_bytes = 0;
1390 s->dma_dac.nextIn = s->dma_dac.nextOut =
1391 s->dma_dac.rawbuf;
1392 }
1393 if (file->f_mode & FMODE_READ) {
1394 stop_adc(s);
1395 synchronize_irq();
1396 s->dma_adc.count = s->dma_adc.total_bytes = 0;
1397 s->dma_adc.nextIn = s->dma_adc.nextOut =
1398 s->dma_adc.rawbuf;
1399 }
1400 return 0;
1401
1402 case SNDCTL_DSP_SPEED:
1403 if (get_user(val, (int *) arg))
1404 return -EFAULT;
1405 if (val >= 0) {
1406 if (file->f_mode & FMODE_READ) {
1407 stop_adc(s);
1408 set_adc_rate(s, val);
1409 }
1410 if (file->f_mode & FMODE_WRITE) {
1411 stop_dac(s);
1412 set_dac_rate(s, val);
1413 }
1414 if (s->open_mode & FMODE_READ)
1415 if ((ret = prog_dmabuf_adc(s)))
1416 return ret;
1417 if (s->open_mode & FMODE_WRITE)
1418 if ((ret = prog_dmabuf_dac(s)))
1419 return ret;
1420 }
1421 return put_user((file->f_mode & FMODE_READ) ?
1422 s->dma_adc.sample_rate :
1423 s->dma_dac.sample_rate,
1424 (int *)arg);
1425
1426 case SNDCTL_DSP_STEREO:
1427 if (get_user(val, (int *) arg))
1428 return -EFAULT;
1429 if (file->f_mode & FMODE_READ) {
1430 stop_adc(s);
1431 s->dma_adc.num_channels = val ? 2 : 1;
1432 if ((ret = prog_dmabuf_adc(s)))
1433 return ret;
1434 }
1435 if (file->f_mode & FMODE_WRITE) {
1436 stop_dac(s);
1437 s->dma_dac.num_channels = val ? 2 : 1;
1438 if (s->codec_ext_caps & AC97_EXT_DACS) {
1439 /* disable surround and center/lfe in AC'97
1440 */
1441 u16 ext_stat = rdcodec(s->codec,
1442 AC97_EXTENDED_STATUS);
1443 wrcodec(s->codec, AC97_EXTENDED_STATUS,
1444 ext_stat | (AC97_EXTSTAT_PRI |
1445 AC97_EXTSTAT_PRJ |
1446 AC97_EXTSTAT_PRK));
1447 }
1448 if ((ret = prog_dmabuf_dac(s)))
1449 return ret;
1450 }
1451 return 0;
1452
1453 case SNDCTL_DSP_CHANNELS:
1454 if (get_user(val, (int *) arg))
1455 return -EFAULT;
1456 if (val != 0) {
1457 if (file->f_mode & FMODE_READ) {
1458 if (val < 0 || val > 2)
1459 return -EINVAL;
1460 stop_adc(s);
1461 s->dma_adc.num_channels = val;
1462 if ((ret = prog_dmabuf_adc(s)))
1463 return ret;
1464 }
1465 if (file->f_mode & FMODE_WRITE) {
1466 switch (val) {
1467 case 1:
1468 case 2:
1469 break;
1470 case 3:
1471 case 5:
1472 return -EINVAL;
1473 case 4:
1474 if (!(s->codec_ext_caps &
1475 AC97_EXTID_SDAC))
1476 return -EINVAL;
1477 break;
1478 case 6:
1479 if ((s->codec_ext_caps &
1480 AC97_EXT_DACS) != AC97_EXT_DACS)
1481 return -EINVAL;
1482 break;
1483 default:
1484 return -EINVAL;
1485 }
1486
1487 stop_dac(s);
1488 if (val <= 2 &&
1489 (s->codec_ext_caps & AC97_EXT_DACS)) {
1490 /* disable surround and center/lfe
1491 * channels in AC'97
1492 */
1493 u16 ext_stat =
1494 rdcodec(s->codec,
1495 AC97_EXTENDED_STATUS);
1496 wrcodec(s->codec,
1497 AC97_EXTENDED_STATUS,
1498 ext_stat | (AC97_EXTSTAT_PRI |
1499 AC97_EXTSTAT_PRJ |
1500 AC97_EXTSTAT_PRK));
1501 } else if (val >= 4) {
1502 /* enable surround, center/lfe
1503 * channels in AC'97
1504 */
1505 u16 ext_stat =
1506 rdcodec(s->codec,
1507 AC97_EXTENDED_STATUS);
1508 ext_stat &= ~AC97_EXTSTAT_PRJ;
1509 if (val == 6)
1510 ext_stat &=
1511 ~(AC97_EXTSTAT_PRI |
1512 AC97_EXTSTAT_PRK);
1513 wrcodec(s->codec,
1514 AC97_EXTENDED_STATUS,
1515 ext_stat);
1516 }
1517
1518 s->dma_dac.num_channels = val;
1519 if ((ret = prog_dmabuf_dac(s)))
1520 return ret;
1521 }
1522 }
1523 return put_user(val, (int *) arg);
1524
1525 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1526 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1527
1528 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
1529 if (get_user(val, (int *) arg))
1530 return -EFAULT;
1531 if (val != AFMT_QUERY) {
1532 if (file->f_mode & FMODE_READ) {
1533 stop_adc(s);
1534 if (val == AFMT_S16_LE)
1535 s->dma_adc.sample_size = 16;
1536 else {
1537 val = AFMT_U8;
1538 s->dma_adc.sample_size = 8;
1539 }
1540 if ((ret = prog_dmabuf_adc(s)))
1541 return ret;
1542 }
1543 if (file->f_mode & FMODE_WRITE) {
1544 stop_dac(s);
1545 if (val == AFMT_S16_LE)
1546 s->dma_dac.sample_size = 16;
1547 else {
1548 val = AFMT_U8;
1549 s->dma_dac.sample_size = 8;
1550 }
1551 if ((ret = prog_dmabuf_dac(s)))
1552 return ret;
1553 }
1554 } else {
1555 if (file->f_mode & FMODE_READ)
1556 val = (s->dma_adc.sample_size == 16) ?
1557 AFMT_S16_LE : AFMT_U8;
1558 else
1559 val = (s->dma_dac.sample_size == 16) ?
1560 AFMT_S16_LE : AFMT_U8;
1561 }
1562 return put_user(val, (int *) arg);
1563
1564 case SNDCTL_DSP_POST:
1565 return 0;
1566
1567 case SNDCTL_DSP_GETTRIGGER:
1568 val = 0;
1569 spin_lock_irqsave(&s->lock, flags);
1570 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1571 val |= PCM_ENABLE_INPUT;
1572 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1573 val |= PCM_ENABLE_OUTPUT;
1574 spin_unlock_irqrestore(&s->lock, flags);
1575 return put_user(val, (int *) arg);
1576
1577 case SNDCTL_DSP_SETTRIGGER:
1578 if (get_user(val, (int *) arg))
1579 return -EFAULT;
1580 if (file->f_mode & FMODE_READ) {
7b666653
SS		 1581 if (val & PCM_ENABLE_INPUT) {
1582 spin_lock_irqsave(&s->lock, flags);
1da177e4 1583 start_adc(s);
7b666653
SS		 1584 spin_unlock_irqrestore(&s->lock, flags);
1585 } else
1da177e4
LT		 1586 stop_adc(s);
1587 }
1588 if (file->f_mode & FMODE_WRITE) {
7b666653
SS		 1589 if (val & PCM_ENABLE_OUTPUT) {
1590 spin_lock_irqsave(&s->lock, flags);
1da177e4 1591 start_dac(s);
7b666653
SS		 1592 spin_unlock_irqrestore(&s->lock, flags);
1593 } else
1da177e4
LT		 1594 stop_dac(s);
1595 }
1596 return 0;
1597
1598 case SNDCTL_DSP_GETOSPACE:
1599 if (!(file->f_mode & FMODE_WRITE))
1600 return -EINVAL;
1601 abinfo.fragsize = s->dma_dac.fragsize;
1602 spin_lock_irqsave(&s->lock, flags);
1603 count = s->dma_dac.count;
1604 count -= dma_count_done(&s->dma_dac);
1605 spin_unlock_irqrestore(&s->lock, flags);
1606 if (count < 0)
1607 count = 0;
1608 abinfo.bytes = (s->dma_dac.dmasize - count) /
1609 s->dma_dac.cnt_factor;
1610 abinfo.fragstotal = s->dma_dac.numfrag;
1611 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1612 pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
1613 return copy_to_user((void *) arg, &abinfo,
1614 sizeof(abinfo)) ? -EFAULT : 0;
1615
1616 case SNDCTL_DSP_GETISPACE:
1617 if (!(file->f_mode & FMODE_READ))
1618 return -EINVAL;
1619 abinfo.fragsize = s->dma_adc.fragsize;
1620 spin_lock_irqsave(&s->lock, flags);
1621 count = s->dma_adc.count;
1622 count += dma_count_done(&s->dma_adc);
1623 spin_unlock_irqrestore(&s->lock, flags);
1624 if (count < 0)
1625 count = 0;
1626 abinfo.bytes = count / s->dma_adc.cnt_factor;
1627 abinfo.fragstotal = s->dma_adc.numfrag;
1628 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1629 return copy_to_user((void *) arg, &abinfo,
1630 sizeof(abinfo)) ? -EFAULT : 0;
1631
1632 case SNDCTL_DSP_NONBLOCK:
1633 file->f_flags |= O_NONBLOCK;
1634 return 0;
1635
1636 case SNDCTL_DSP_GETODELAY:
1637 if (!(file->f_mode & FMODE_WRITE))
1638 return -EINVAL;
1639 spin_lock_irqsave(&s->lock, flags);
1640 count = s->dma_dac.count;
1641 count -= dma_count_done(&s->dma_dac);
1642 spin_unlock_irqrestore(&s->lock, flags);
1643 if (count < 0)
1644 count = 0;
1645 count /= s->dma_dac.cnt_factor;
1646 return put_user(count, (int *) arg);
1647
1648 case SNDCTL_DSP_GETIPTR:
1649 if (!(file->f_mode & FMODE_READ))
1650 return -EINVAL;
1651 spin_lock_irqsave(&s->lock, flags);
1652 cinfo.bytes = s->dma_adc.total_bytes;
1653 count = s->dma_adc.count;
1654 if (!s->dma_adc.stopped) {
1655 diff = dma_count_done(&s->dma_adc);
1656 count += diff;
1657 cinfo.bytes += diff;
1658 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
1659 virt_to_phys(s->dma_adc.rawbuf);
1660 } else
1661 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1662 virt_to_phys(s->dma_adc.rawbuf);
1663 if (s->dma_adc.mapped)
1664 s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1665 spin_unlock_irqrestore(&s->lock, flags);
1666 if (count < 0)
1667 count = 0;
1668 cinfo.blocks = count >> s->dma_adc.fragshift;
1669 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1670
1671 case SNDCTL_DSP_GETOPTR:
1672 if (!(file->f_mode & FMODE_READ))
1673 return -EINVAL;
1674 spin_lock_irqsave(&s->lock, flags);
1675 cinfo.bytes = s->dma_dac.total_bytes;
1676 count = s->dma_dac.count;
1677 if (!s->dma_dac.stopped) {
1678 diff = dma_count_done(&s->dma_dac);
1679 count -= diff;
1680 cinfo.bytes += diff;
1681 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1682 virt_to_phys(s->dma_dac.rawbuf);
1683 } else
1684 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1685 virt_to_phys(s->dma_dac.rawbuf);
1686 if (s->dma_dac.mapped)
1687 s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1688 spin_unlock_irqrestore(&s->lock, flags);
1689 if (count < 0)
1690 count = 0;
1691 cinfo.blocks = count >> s->dma_dac.fragshift;
1692 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1693
1694 case SNDCTL_DSP_GETBLKSIZE:
1695 if (file->f_mode & FMODE_WRITE)
1696 return put_user(s->dma_dac.fragsize, (int *) arg);
1697 else
1698 return put_user(s->dma_adc.fragsize, (int *) arg);
1699
1700 case SNDCTL_DSP_SETFRAGMENT:
1701 if (get_user(val, (int *) arg))
1702 return -EFAULT;
1703 if (file->f_mode & FMODE_READ) {
1704 stop_adc(s);
1705 s->dma_adc.ossfragshift = val & 0xffff;
1706 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1707 if (s->dma_adc.ossfragshift < 4)
1708 s->dma_adc.ossfragshift = 4;
1709 if (s->dma_adc.ossfragshift > 15)
1710 s->dma_adc.ossfragshift = 15;
1711 if (s->dma_adc.ossmaxfrags < 4)
1712 s->dma_adc.ossmaxfrags = 4;
1713 if ((ret = prog_dmabuf_adc(s)))
1714 return ret;
1715 }
1716 if (file->f_mode & FMODE_WRITE) {
1717 stop_dac(s);
1718 s->dma_dac.ossfragshift = val & 0xffff;
1719 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1720 if (s->dma_dac.ossfragshift < 4)
1721 s->dma_dac.ossfragshift = 4;
1722 if (s->dma_dac.ossfragshift > 15)
1723 s->dma_dac.ossfragshift = 15;
1724 if (s->dma_dac.ossmaxfrags < 4)
1725 s->dma_dac.ossmaxfrags = 4;
1726 if ((ret = prog_dmabuf_dac(s)))
1727 return ret;
1728 }
1729 return 0;
1730
1731 case SNDCTL_DSP_SUBDIVIDE:
1732 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1733 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1734 return -EINVAL;
1735 if (get_user(val, (int *) arg))
1736 return -EFAULT;
1737 if (val != 1 && val != 2 && val != 4)
1738 return -EINVAL;
1739 if (file->f_mode & FMODE_READ) {
1740 stop_adc(s);
1741 s->dma_adc.subdivision = val;
1742 if ((ret = prog_dmabuf_adc(s)))
1743 return ret;
1744 }
1745 if (file->f_mode & FMODE_WRITE) {
1746 stop_dac(s);
1747 s->dma_dac.subdivision = val;
1748 if ((ret = prog_dmabuf_dac(s)))
1749 return ret;
1750 }
1751 return 0;
1752
1753 case SOUND_PCM_READ_RATE:
1754 return put_user((file->f_mode & FMODE_READ) ?
1755 s->dma_adc.sample_rate :
1756 s->dma_dac.sample_rate,
1757 (int *)arg);
1758
1759 case SOUND_PCM_READ_CHANNELS:
1760 if (file->f_mode & FMODE_READ)
1761 return put_user(s->dma_adc.num_channels, (int *)arg);
1762 else
1763 return put_user(s->dma_dac.num_channels, (int *)arg);
1764
1765 case SOUND_PCM_READ_BITS:
1766 if (file->f_mode & FMODE_READ)
1767 return put_user(s->dma_adc.sample_size, (int *)arg);
1768 else
1769 return put_user(s->dma_dac.sample_size, (int *)arg);
1770
1771 case SOUND_PCM_WRITE_FILTER:
1772 case SNDCTL_DSP_SETSYNCRO:
1773 case SOUND_PCM_READ_FILTER:
1774 return -EINVAL;
1775 }
1776
1777 return mixdev_ioctl(s->codec, cmd, arg);
1778}
1779
1780
1781static int
1782au1550_open(struct inode *inode, struct file *file)
1783{
1784 int minor = MINOR(inode->i_rdev);
1785 DECLARE_WAITQUEUE(wait, current);
1786 struct au1550_state *s = &au1550_state;
1787 int ret;
1788
1789#ifdef DEBUG
1790 if (file->f_flags & O_NONBLOCK)
1791 pr_debug("open: non-blocking\n");
1792 else
1793 pr_debug("open: blocking\n");
1794#endif
1795
1796 file->private_data = s;
1797 /* wait for device to become free */
910f5d20 1798 mutex_lock(&s->open_mutex);
1da177e4
LT		 1799 while (s->open_mode & file->f_mode) {
1800 if (file->f_flags & O_NONBLOCK) {
910f5d20 1801 mutex_unlock(&s->open_mutex);
1da177e4
LT		 1802 return -EBUSY;
1803 }
1804 add_wait_queue(&s->open_wait, &wait);
1805 __set_current_state(TASK_INTERRUPTIBLE);
910f5d20 1806 mutex_unlock(&s->open_mutex);
1da177e4
LT		 1807 schedule();
1808 remove_wait_queue(&s->open_wait, &wait);
1809 set_current_state(TASK_RUNNING);
1810 if (signal_pending(current))
1811 return -ERESTARTSYS;
910f5d20 1812 mutex_lock(&s->open_mutex);
1da177e4
LT		 1813 }
1814
1815 stop_dac(s);
1816 stop_adc(s);
1817
1818 if (file->f_mode & FMODE_READ) {
1819 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1820 s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1821 s->dma_adc.num_channels = 1;
1822 s->dma_adc.sample_size = 8;
1823 set_adc_rate(s, 8000);
1824 if ((minor & 0xf) == SND_DEV_DSP16)
1825 s->dma_adc.sample_size = 16;
1826 }
1827
1828 if (file->f_mode & FMODE_WRITE) {
1829 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1830 s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1831 s->dma_dac.num_channels = 1;
1832 s->dma_dac.sample_size = 8;
1833 set_dac_rate(s, 8000);
1834 if ((minor & 0xf) == SND_DEV_DSP16)
1835 s->dma_dac.sample_size = 16;
1836 }
1837
1838 if (file->f_mode & FMODE_READ) {
1839 if ((ret = prog_dmabuf_adc(s)))
1840 return ret;
1841 }
1842 if (file->f_mode & FMODE_WRITE) {
1843 if ((ret = prog_dmabuf_dac(s)))
1844 return ret;
1845 }
1846
1847 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
910f5d20
IM		 1848 mutex_unlock(&s->open_mutex);
1849 mutex_init(&s->sem);
1da177e4
LT		 1850 return 0;
1851}
1852
1853static int
1854au1550_release(struct inode *inode, struct file *file)
1855{
1856 struct au1550_state *s = (struct au1550_state *)file->private_data;
1857
1858 lock_kernel();
1859
1860 if (file->f_mode & FMODE_WRITE) {
1861 unlock_kernel();
1862 drain_dac(s, file->f_flags & O_NONBLOCK);
1863 lock_kernel();
1864 }
1865
910f5d20 1866 mutex_lock(&s->open_mutex);
1da177e4
LT		 1867 if (file->f_mode & FMODE_WRITE) {
1868 stop_dac(s);
1869 kfree(s->dma_dac.rawbuf);
1870 s->dma_dac.rawbuf = NULL;
1871 }
1872 if (file->f_mode & FMODE_READ) {
1873 stop_adc(s);
1874 kfree(s->dma_adc.rawbuf);
1875 s->dma_adc.rawbuf = NULL;
1876 }
1877 s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
910f5d20 1878 mutex_unlock(&s->open_mutex);
1da177e4
LT		 1879 wake_up(&s->open_wait);
1880 unlock_kernel();
1881 return 0;
1882}
1883
1884static /*const */ struct file_operations au1550_audio_fops = {
1885 owner: THIS_MODULE,
1886 llseek: au1550_llseek,
1887 read: au1550_read,
1888 write: au1550_write,
1889 poll: au1550_poll,
1890 ioctl: au1550_ioctl,
1891 mmap: au1550_mmap,
1892 open: au1550_open,
1893 release: au1550_release,
1894};
1895
1896MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
1897MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
bb12b76e
DP		 1898MODULE_LICENSE("GPL");
1899
1da177e4
LT		 1900
1901static int __devinit
1902au1550_probe(void)
1903{
1904 struct au1550_state *s = &au1550_state;
1905 int val;
1906
1907 memset(s, 0, sizeof(struct au1550_state));
1908
1909 init_waitqueue_head(&s->dma_adc.wait);
1910 init_waitqueue_head(&s->dma_dac.wait);
1911 init_waitqueue_head(&s->open_wait);
910f5d20 1912 mutex_init(&s->open_mutex);
1da177e4
LT		 1913 spin_lock_init(&s->lock);
1914
1915 s->codec = ac97_alloc_codec();
1916 if(s->codec == NULL) {
1917 err("Out of memory");
1918 return -1;
1919 }
1920 s->codec->private_data = s;
1921 s->codec->id = 0;
1922 s->codec->codec_read = rdcodec;
1923 s->codec->codec_write = wrcodec;
1924 s->codec->codec_wait = waitcodec;
1925
1926 if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
1927 0x30, "Au1550 AC97")) {
1928 err("AC'97 ports in use");
1929 }
1930
1931 /* Allocate the DMA Channels
1932 */
1933 if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
1934 DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
1935 err("Can't get DAC DMA");
1936 goto err_dma1;
1937 }
1938 au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
1939 if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
1940 NUM_DBDMA_DESCRIPTORS) == 0) {
1941 err("Can't get DAC DMA descriptors");
1942 goto err_dma1;
1943 }
1944
1945 if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
1946 DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
1947 err("Can't get ADC DMA");
1948 goto err_dma2;
1949 }
1950 au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
1951 if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
1952 NUM_DBDMA_DESCRIPTORS) == 0) {
1953 err("Can't get ADC DMA descriptors");
1954 goto err_dma2;
1955 }
1956
1957 pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
1958
1959 /* register devices */
1960
1961 if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
1962 goto err_dev1;
1963 if ((s->codec->dev_mixer =
1964 register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
1965 goto err_dev2;
1966
1967 /* The GPIO for the appropriate PSC was configured by the
1968 * board specific start up.
1969 *
1970 * configure PSC for AC'97
1971 */
1972 au_writel(0, AC97_PSC_CTRL); /* Disable PSC */
1973 au_sync();
1974 au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
1975 au_sync();
1976
1977 /* cold reset the AC'97
1978 */
1979 au_writel(PSC_AC97RST_RST, PSC_AC97RST);
1980 au_sync();
1981 au1550_delay(10);
1982 au_writel(0, PSC_AC97RST);
1983 au_sync();
1984
1985 /* need to delay around 500msec(bleech) to give
1986 some CODECs enough time to wakeup */
1987 au1550_delay(500);
1988
1989 /* warm reset the AC'97 to start the bitclk
1990 */
1991 au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
1992 au_sync();
1993 udelay(100);
1994 au_writel(0, PSC_AC97RST);
1995 au_sync();
1996
1997 /* Enable PSC
1998 */
1999 au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
2000 au_sync();
2001
2002 /* Wait for PSC ready.
2003 */
2004 do {
05090fc9 2005 val = au_readl(PSC_AC97STAT);
1da177e4
LT		 2006 au_sync();
2007 } while ((val & PSC_AC97STAT_SR) == 0);
2008
2009 /* Configure AC97 controller.
2010 * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
2011 */
2012 val = PSC_AC97CFG_SET_LEN(16);
2013 val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
2014
2015 /* Enable device so we can at least
2016 * talk over the AC-link.
2017 */
2018 au_writel(val, PSC_AC97CFG);
2019 au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
2020 au_sync();
2021 val |= PSC_AC97CFG_DE_ENABLE;
2022 au_writel(val, PSC_AC97CFG);
2023 au_sync();
2024
2025 /* Wait for Device ready.
2026 */
2027 do {
05090fc9 2028 val = au_readl(PSC_AC97STAT);
1da177e4
LT		 2029 au_sync();
2030 } while ((val & PSC_AC97STAT_DR) == 0);
2031
2032 /* codec init */
2033 if (!ac97_probe_codec(s->codec))
2034 goto err_dev3;
2035
2036 s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
2037 s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
2038 pr_info("AC'97 Base/Extended ID = %04x/%04x",
2039 s->codec_base_caps, s->codec_ext_caps);
2040
2041 if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
2042 /* codec does not support VRA
2043 */
2044 s->no_vra = 1;
2045 } else if (!vra) {
2046 /* Boot option says disable VRA
2047 */
2048 u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
2049 wrcodec(s->codec, AC97_EXTENDED_STATUS,
2050 ac97_extstat & ~AC97_EXTSTAT_VRA);
2051 s->no_vra = 1;
2052 }
2053 if (s->no_vra)
2054 pr_info("no VRA, interpolating and decimating");
2055
2056 /* set mic to be the recording source */
2057 val = SOUND_MASK_MIC;
2058 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
2059 (unsigned long) &val);
2060
2061 return 0;
2062
2063 err_dev3:
2064 unregister_sound_mixer(s->codec->dev_mixer);
2065 err_dev2:
2066 unregister_sound_dsp(s->dev_audio);
2067 err_dev1:
2068 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2069 err_dma2:
2070 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2071 err_dma1:
2072 release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2073
2074 ac97_release_codec(s->codec);
2075 return -1;
2076}
2077
2078static void __devinit
2079au1550_remove(void)
2080{
2081 struct au1550_state *s = &au1550_state;
2082
2083 if (!s)
2084 return;
2085 synchronize_irq();
2086 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2087 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2088 release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2089 unregister_sound_dsp(s->dev_audio);
2090 unregister_sound_mixer(s->codec->dev_mixer);
2091 ac97_release_codec(s->codec);
2092}
2093
2094static int __init
2095init_au1550(void)
2096{
2097 return au1550_probe();
2098}
2099
2100static void __exit
2101cleanup_au1550(void)
2102{
2103 au1550_remove();
2104}
2105
2106module_init(init_au1550);
2107module_exit(cleanup_au1550);
2108
2109#ifndef MODULE
2110
2111static int __init
2112au1550_setup(char *options)
2113{
2114 char *this_opt;
2115
2116 if (!options || !*options)
2117 return 0;
2118
2119 while ((this_opt = strsep(&options, ","))) {
2120 if (!*this_opt)
2121 continue;
2122 if (!strncmp(this_opt, "vra", 3)) {
2123 vra = 1;
2124 }
2125 }
2126
2127 return 1;
2128}
2129
2130__setup("au1550_audio=", au1550_setup);
2131
2132#endif /* MODULE */
kernel source for telekom puls (alcatel/mediatek)