Commit | Line | Data |
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66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver PCI Bus Glue. | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/pci.h> | |
7fc2a616 | 24 | #include <linux/slab.h> |
6eb0de82 | 25 | #include <linux/module.h> |
66d4eadd SS |
26 | |
27 | #include "xhci.h" | |
28 | ||
ac9d8fe7 SS |
29 | /* Device for a quirk */ |
30 | #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 | |
31 | #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 | |
bba18e33 | 32 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 |
ac9d8fe7 | 33 | |
c877b3b2 ML |
34 | #define PCI_VENDOR_ID_ETRON 0x1b6f |
35 | #define PCI_DEVICE_ID_ASROCK_P67 0x7023 | |
36 | ||
66d4eadd SS |
37 | static const char hcd_name[] = "xhci_hcd"; |
38 | ||
39 | /* called after powerup, by probe or system-pm "wakeup" */ | |
40 | static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) | |
41 | { | |
42 | /* | |
43 | * TODO: Implement finding debug ports later. | |
44 | * TODO: see if there are any quirks that need to be added to handle | |
45 | * new extended capabilities. | |
46 | */ | |
47 | ||
48 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
49 | if (!pci_set_mwi(pdev)) | |
50 | xhci_dbg(xhci, "MWI active\n"); | |
51 | ||
52 | xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); | |
53 | return 0; | |
54 | } | |
55 | ||
da3c9c4f SAS |
56 | static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) |
57 | { | |
58 | struct pci_dev *pdev = to_pci_dev(dev); | |
59 | ||
ac9d8fe7 SS |
60 | /* Look for vendor-specific quirks */ |
61 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && | |
bba18e33 SS |
62 | (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || |
63 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { | |
64 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && | |
65 | pdev->revision == 0x0) { | |
ac9d8fe7 SS |
66 | xhci->quirks |= XHCI_RESET_EP_QUIRK; |
67 | xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure" | |
68 | " endpoint cmd after reset endpoint\n"); | |
f5182b41 SS |
69 | } |
70 | /* Fresco Logic confirms: all revisions of this chip do not | |
71 | * support MSI, even though some of them claim to in their PCI | |
72 | * capabilities. | |
73 | */ | |
74 | xhci->quirks |= XHCI_BROKEN_MSI; | |
75 | xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u " | |
76 | "has broken MSI implementation\n", | |
77 | pdev->revision); | |
1530bbc6 | 78 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
ac9d8fe7 | 79 | } |
f5182b41 | 80 | |
0238634d SS |
81 | if (pdev->vendor == PCI_VENDOR_ID_NEC) |
82 | xhci->quirks |= XHCI_NEC_HOST; | |
ac9d8fe7 | 83 | |
7e393a83 AX |
84 | if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) |
85 | xhci->quirks |= XHCI_AMD_0x96_HOST; | |
86 | ||
c41136b0 AX |
87 | /* AMD PLL quirk */ |
88 | if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) | |
89 | xhci->quirks |= XHCI_AMD_PLL_FIX; | |
607a00ad HR |
90 | |
91 | if (pdev->vendor == PCI_VENDOR_ID_AMD) | |
92 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; | |
93 | ||
e3567d2c SS |
94 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
95 | xhci->quirks |= XHCI_LPM_SUPPORT; | |
96 | xhci->quirks |= XHCI_INTEL_HOST; | |
2cb264a3 | 97 | xhci->quirks |= XHCI_AVOID_BEI; |
e3567d2c | 98 | } |
ad808333 SS |
99 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
100 | pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { | |
2cf95c18 SS |
101 | xhci->quirks |= XHCI_EP_LIMIT_QUIRK; |
102 | xhci->limit_active_eps = 64; | |
86cc558e | 103 | xhci->quirks |= XHCI_SW_BW_CHECKING; |
e95829f4 SS |
104 | /* |
105 | * PPT desktop boards DH77EB and DH77DF will power back on after | |
106 | * a few seconds of being shutdown. The fix for this is to | |
107 | * switch the ports from xHCI to EHCI on shutdown. We can't use | |
108 | * DMI information to find those particular boards (since each | |
109 | * vendor will change the board name), so we have to key off all | |
110 | * PPT chipsets. | |
111 | */ | |
112 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; | |
ad808333 | 113 | } |
c877b3b2 ML |
114 | if (pdev->vendor == PCI_VENDOR_ID_ETRON && |
115 | pdev->device == PCI_DEVICE_ID_ASROCK_P67) { | |
116 | xhci->quirks |= XHCI_RESET_ON_RESUME; | |
117 | xhci_dbg(xhci, "QUIRK: Resetting on resume\n"); | |
5cb7df2b | 118 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
c877b3b2 | 119 | } |
d04ff9c0 | 120 | if (pdev->vendor == PCI_VENDOR_ID_RENESAS && |
f21d92c4 | 121 | pdev->device == 0x0015) |
d04ff9c0 | 122 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
457a4f61 EF |
123 | if (pdev->vendor == PCI_VENDOR_ID_VIA) |
124 | xhci->quirks |= XHCI_RESET_ON_RESUME; | |
da3c9c4f | 125 | } |
c41136b0 | 126 | |
da3c9c4f SAS |
127 | /* called during probe() after chip reset completes */ |
128 | static int xhci_pci_setup(struct usb_hcd *hcd) | |
129 | { | |
130 | struct xhci_hcd *xhci; | |
131 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
132 | int retval; | |
66d4eadd | 133 | |
da3c9c4f | 134 | retval = xhci_gen_setup(hcd, xhci_pci_quirks); |
66d4eadd | 135 | if (retval) |
da3c9c4f | 136 | return retval; |
006d5820 | 137 | |
da3c9c4f SAS |
138 | xhci = hcd_to_xhci(hcd); |
139 | if (!usb_hcd_is_primary_hcd(hcd)) | |
140 | return 0; | |
66d4eadd SS |
141 | |
142 | pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); | |
143 | xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); | |
144 | ||
145 | /* Find any debug ports */ | |
b02d0ed6 SS |
146 | retval = xhci_pci_reinit(xhci, pdev); |
147 | if (!retval) | |
148 | return retval; | |
149 | ||
b02d0ed6 SS |
150 | kfree(xhci); |
151 | return retval; | |
152 | } | |
153 | ||
f6ff0ac8 SS |
154 | /* |
155 | * We need to register our own PCI probe function (instead of the USB core's | |
156 | * function) in order to create a second roothub under xHCI. | |
157 | */ | |
158 | static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
159 | { | |
160 | int retval; | |
161 | struct xhci_hcd *xhci; | |
162 | struct hc_driver *driver; | |
163 | struct usb_hcd *hcd; | |
164 | ||
165 | driver = (struct hc_driver *)id->driver_data; | |
57ff245e MN |
166 | |
167 | /* Prevent runtime suspending between USB-2 and USB-3 initialization */ | |
168 | pm_runtime_get_noresume(&dev->dev); | |
169 | ||
f6ff0ac8 SS |
170 | /* Register the USB 2.0 roothub. |
171 | * FIXME: USB core must know to register the USB 2.0 roothub first. | |
172 | * This is sort of silly, because we could just set the HCD driver flags | |
173 | * to say USB 2.0, but I'm not sure what the implications would be in | |
174 | * the other parts of the HCD code. | |
175 | */ | |
176 | retval = usb_hcd_pci_probe(dev, id); | |
177 | ||
178 | if (retval) | |
57ff245e | 179 | goto put_runtime_pm; |
f6ff0ac8 SS |
180 | |
181 | /* USB 2.0 roothub is stored in the PCI device now. */ | |
182 | hcd = dev_get_drvdata(&dev->dev); | |
183 | xhci = hcd_to_xhci(hcd); | |
184 | xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, | |
185 | pci_name(dev), hcd); | |
186 | if (!xhci->shared_hcd) { | |
187 | retval = -ENOMEM; | |
188 | goto dealloc_usb2_hcd; | |
189 | } | |
190 | ||
191 | /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset) | |
192 | * is called by usb_add_hcd(). | |
193 | */ | |
194 | *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci; | |
195 | ||
196 | retval = usb_add_hcd(xhci->shared_hcd, dev->irq, | |
b5dd18d8 | 197 | IRQF_SHARED); |
f6ff0ac8 SS |
198 | if (retval) |
199 | goto put_usb3_hcd; | |
200 | /* Roothub already marked as USB 3.0 speed */ | |
3b3db026 SS |
201 | |
202 | /* We know the LPM timeout algorithms for this host, let the USB core | |
203 | * enable and disable LPM for devices under the USB 3.0 roothub. | |
204 | */ | |
205 | if (xhci->quirks & XHCI_LPM_SUPPORT) | |
206 | hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1; | |
207 | ||
57ff245e MN |
208 | /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ |
209 | pm_runtime_put_noidle(&dev->dev); | |
210 | ||
f6ff0ac8 SS |
211 | return 0; |
212 | ||
213 | put_usb3_hcd: | |
214 | usb_put_hcd(xhci->shared_hcd); | |
215 | dealloc_usb2_hcd: | |
216 | usb_hcd_pci_remove(dev); | |
57ff245e MN |
217 | put_runtime_pm: |
218 | pm_runtime_put_noidle(&dev->dev); | |
f6ff0ac8 SS |
219 | return retval; |
220 | } | |
221 | ||
b02d0ed6 SS |
222 | static void xhci_pci_remove(struct pci_dev *dev) |
223 | { | |
224 | struct xhci_hcd *xhci; | |
225 | ||
226 | xhci = hcd_to_xhci(pci_get_drvdata(dev)); | |
2ebbe4f6 | 227 | xhci->xhc_state |= XHCI_STATE_REMOVING; |
f6ff0ac8 SS |
228 | if (xhci->shared_hcd) { |
229 | usb_remove_hcd(xhci->shared_hcd); | |
230 | usb_put_hcd(xhci->shared_hcd); | |
231 | } | |
b02d0ed6 SS |
232 | usb_hcd_pci_remove(dev); |
233 | kfree(xhci); | |
66d4eadd SS |
234 | } |
235 | ||
5535b1d5 AX |
236 | #ifdef CONFIG_PM |
237 | static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) | |
238 | { | |
239 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c3897aa5 SS |
240 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
241 | ||
242 | /* | |
243 | * Systems with the TI redriver that loses port status change events | |
244 | * need to have the registers polled during D3, so avoid D3cold. | |
245 | */ | |
246 | if (xhci_compliance_mode_recovery_timer_quirk_check()) | |
247 | pdev->no_d3cold = true; | |
5535b1d5 | 248 | |
77b84767 | 249 | return xhci_suspend(xhci); |
5535b1d5 AX |
250 | } |
251 | ||
252 | static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) | |
253 | { | |
254 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
69e848c2 | 255 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
5535b1d5 AX |
256 | int retval = 0; |
257 | ||
69e848c2 SS |
258 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
259 | * not support xHCI natively. That means that during system resume, it | |
260 | * may switch the ports back to EHCI so that users can use their | |
261 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
262 | * | |
263 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
264 | * enabled before resume, and switch the ports back to xHCI when the | |
265 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
266 | * writers. | |
267 | * | |
268 | * Unconditionally switch the ports back to xHCI after a system resume. | |
269 | * We can't tell whether the EHCI or xHCI controller will be resumed | |
270 | * first, so we have to do the port switchover in both drivers. Writing | |
271 | * a '1' to the port switchover registers should have no effect if the | |
272 | * port was already switched over. | |
273 | */ | |
274 | if (usb_is_intel_switchable_xhci(pdev)) | |
275 | usb_enable_xhci_ports(pdev); | |
276 | ||
5535b1d5 AX |
277 | retval = xhci_resume(xhci, hibernated); |
278 | return retval; | |
279 | } | |
280 | #endif /* CONFIG_PM */ | |
281 | ||
66d4eadd SS |
282 | static const struct hc_driver xhci_pci_hc_driver = { |
283 | .description = hcd_name, | |
284 | .product_desc = "xHCI Host Controller", | |
b02d0ed6 | 285 | .hcd_priv_size = sizeof(struct xhci_hcd *), |
66d4eadd SS |
286 | |
287 | /* | |
288 | * generic hardware linkage | |
289 | */ | |
7f84eef0 | 290 | .irq = xhci_irq, |
f6ff0ac8 | 291 | .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, |
66d4eadd SS |
292 | |
293 | /* | |
294 | * basic lifecycle operations | |
295 | */ | |
296 | .reset = xhci_pci_setup, | |
297 | .start = xhci_run, | |
5535b1d5 AX |
298 | #ifdef CONFIG_PM |
299 | .pci_suspend = xhci_pci_suspend, | |
300 | .pci_resume = xhci_pci_resume, | |
301 | #endif | |
66d4eadd SS |
302 | .stop = xhci_stop, |
303 | .shutdown = xhci_shutdown, | |
304 | ||
3ffbba95 SS |
305 | /* |
306 | * managing i/o requests and associated device resources | |
307 | */ | |
d0e96f5a SS |
308 | .urb_enqueue = xhci_urb_enqueue, |
309 | .urb_dequeue = xhci_urb_dequeue, | |
3ffbba95 SS |
310 | .alloc_dev = xhci_alloc_dev, |
311 | .free_dev = xhci_free_dev, | |
eab1cafc SS |
312 | .alloc_streams = xhci_alloc_streams, |
313 | .free_streams = xhci_free_streams, | |
f94e0186 SS |
314 | .add_endpoint = xhci_add_endpoint, |
315 | .drop_endpoint = xhci_drop_endpoint, | |
a1587d97 | 316 | .endpoint_reset = xhci_endpoint_reset, |
f94e0186 SS |
317 | .check_bandwidth = xhci_check_bandwidth, |
318 | .reset_bandwidth = xhci_reset_bandwidth, | |
3ffbba95 | 319 | .address_device = xhci_address_device, |
b356b7c7 | 320 | .update_hub_device = xhci_update_hub_device, |
f0615c45 | 321 | .reset_device = xhci_discover_or_reset_device, |
3ffbba95 | 322 | |
66d4eadd SS |
323 | /* |
324 | * scheduling support | |
325 | */ | |
326 | .get_frame_number = xhci_get_frame, | |
327 | ||
0f2a7930 SS |
328 | /* Root hub support */ |
329 | .hub_control = xhci_hub_control, | |
330 | .hub_status_data = xhci_hub_status_data, | |
9777e3ce AX |
331 | .bus_suspend = xhci_bus_suspend, |
332 | .bus_resume = xhci_bus_resume, | |
9574323c AX |
333 | /* |
334 | * call back when device connected and addressed | |
335 | */ | |
336 | .update_device = xhci_update_device, | |
65580b43 | 337 | .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, |
3b3db026 SS |
338 | .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, |
339 | .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, | |
3f5eb141 | 340 | .find_raw_port_number = xhci_find_raw_port_number, |
66d4eadd SS |
341 | }; |
342 | ||
343 | /*-------------------------------------------------------------------------*/ | |
344 | ||
345 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
346 | static const struct pci_device_id pci_ids[] = { { | |
347 | /* handle any USB 3.0 xHCI controller */ | |
348 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), | |
349 | .driver_data = (unsigned long) &xhci_pci_hc_driver, | |
350 | }, | |
351 | { /* end: all zeroes */ } | |
352 | }; | |
353 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
354 | ||
355 | /* pci driver glue; this is a "new style" PCI driver module */ | |
356 | static struct pci_driver xhci_pci_driver = { | |
357 | .name = (char *) hcd_name, | |
358 | .id_table = pci_ids, | |
359 | ||
f6ff0ac8 | 360 | .probe = xhci_pci_probe, |
b02d0ed6 | 361 | .remove = xhci_pci_remove, |
66d4eadd SS |
362 | /* suspend and resume implemented later */ |
363 | ||
364 | .shutdown = usb_hcd_pci_shutdown, | |
c9dd3462 | 365 | #ifdef CONFIG_PM |
5535b1d5 AX |
366 | .driver = { |
367 | .pm = &usb_hcd_pci_pm_ops | |
368 | }, | |
369 | #endif | |
66d4eadd SS |
370 | }; |
371 | ||
0cc47d54 | 372 | int __init xhci_register_pci(void) |
66d4eadd SS |
373 | { |
374 | return pci_register_driver(&xhci_pci_driver); | |
375 | } | |
376 | ||
a46c46a1 | 377 | void xhci_unregister_pci(void) |
66d4eadd SS |
378 | { |
379 | pci_unregister_driver(&xhci_pci_driver); | |
380 | } |