projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'v3.10.108' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / efm32-uart.c
CommitLineData
3afbd89c
UKK		 1#if defined(CONFIG_SERIAL_EFM32_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2#define SUPPORT_SYSRQ
3#endif
4
5#include <linux/kernel.h>
6#include <linux/module.h>
7#include <linux/io.h>
8#include <linux/platform_device.h>
9#include <linux/console.h>
10#include <linux/sysrq.h>
11#include <linux/serial_core.h>
12#include <linux/tty_flip.h>
13#include <linux/slab.h>
14#include <linux/clk.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17
18#include <linux/platform_data/efm32-uart.h>
19
20#define DRIVER_NAME "efm32-uart"
21#define DEV_NAME "ttyefm"
22
23#define UARTn_CTRL 0x00
24#define UARTn_CTRL_SYNC 0x0001
25#define UARTn_CTRL_TXBIL 0x1000
26
27#define UARTn_FRAME 0x04
28#define UARTn_FRAME_DATABITS__MASK 0x000f
29#define UARTn_FRAME_DATABITS(n) ((n) - 3)
12d805b5 30#define UARTn_FRAME_PARITY__MASK 0x0300
3afbd89c
UKK		 31#define UARTn_FRAME_PARITY_NONE 0x0000
32#define UARTn_FRAME_PARITY_EVEN 0x0200
33#define UARTn_FRAME_PARITY_ODD 0x0300
34#define UARTn_FRAME_STOPBITS_HALF 0x0000
35#define UARTn_FRAME_STOPBITS_ONE 0x1000
36#define UARTn_FRAME_STOPBITS_TWO 0x3000
37
38#define UARTn_CMD 0x0c
39#define UARTn_CMD_RXEN 0x0001
40#define UARTn_CMD_RXDIS 0x0002
41#define UARTn_CMD_TXEN 0x0004
42#define UARTn_CMD_TXDIS 0x0008
43
44#define UARTn_STATUS 0x10
45#define UARTn_STATUS_TXENS 0x0002
46#define UARTn_STATUS_TXC 0x0020
47#define UARTn_STATUS_TXBL 0x0040
48#define UARTn_STATUS_RXDATAV 0x0080
49
50#define UARTn_CLKDIV 0x14
51
52#define UARTn_RXDATAX 0x18
53#define UARTn_RXDATAX_RXDATA__MASK 0x01ff
54#define UARTn_RXDATAX_PERR 0x4000
55#define UARTn_RXDATAX_FERR 0x8000
56/*
57 * This is a software only flag used for ignore_status_mask and
58 * read_status_mask! It's used for breaks that the hardware doesn't report
59 * explicitly.
60 */
61#define SW_UARTn_RXDATAX_BERR 0x2000
62
63#define UARTn_TXDATA 0x34
64
65#define UARTn_IF 0x40
66#define UARTn_IF_TXC 0x0001
67#define UARTn_IF_TXBL 0x0002
68#define UARTn_IF_RXDATAV 0x0004
69#define UARTn_IF_RXOF 0x0010
70
71#define UARTn_IFS 0x44
72#define UARTn_IFC 0x48
73#define UARTn_IEN 0x4c
74
75#define UARTn_ROUTE 0x54
76#define UARTn_ROUTE_LOCATION__MASK 0x0700
77#define UARTn_ROUTE_LOCATION(n) (((n) << 8) & UARTn_ROUTE_LOCATION__MASK)
78#define UARTn_ROUTE_RXPEN 0x0001
79#define UARTn_ROUTE_TXPEN 0x0002
80
81struct efm32_uart_port {
82 struct uart_port port;
83 unsigned int txirq;
84 struct clk *clk;
c098020d 85 struct efm32_uart_pdata pdata;
3afbd89c
UKK		 86};
87#define to_efm_port(_port) container_of(_port, struct efm32_uart_port, port)
88#define efm_debug(efm_port, format, arg...) \
89 dev_dbg(efm_port->port.dev, format, ##arg)
90
91static void efm32_uart_write32(struct efm32_uart_port *efm_port,
92 u32 value, unsigned offset)
93{
94 writel_relaxed(value, efm_port->port.membase + offset);
95}
96
97static u32 efm32_uart_read32(struct efm32_uart_port *efm_port,
98 unsigned offset)
99{
100 return readl_relaxed(efm_port->port.membase + offset);
101}
102
103static unsigned int efm32_uart_tx_empty(struct uart_port *port)
104{
105 struct efm32_uart_port *efm_port = to_efm_port(port);
106 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
107
108 if (status & UARTn_STATUS_TXC)
109 return TIOCSER_TEMT;
110 else
111 return 0;
112}
113
114static void efm32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
115{
116 /* sorry, neither handshaking lines nor loop functionallity */
117}
118
119static unsigned int efm32_uart_get_mctrl(struct uart_port *port)
120{
121 /* sorry, no handshaking lines available */
122 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
123}
124
125static void efm32_uart_stop_tx(struct uart_port *port)
126{
127 struct efm32_uart_port *efm_port = to_efm_port(port);
128 u32 ien = efm32_uart_read32(efm_port, UARTn_IEN);
129
130 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
131 ien &= ~(UARTn_IF_TXC | UARTn_IF_TXBL);
132 efm32_uart_write32(efm_port, ien, UARTn_IEN);
133}
134
135static void efm32_uart_tx_chars(struct efm32_uart_port *efm_port)
136{
137 struct uart_port *port = &efm_port->port;
138 struct circ_buf *xmit = &port->state->xmit;
139
140 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
141 UARTn_STATUS_TXBL) {
142 if (port->x_char) {
143 port->icount.tx++;
144 efm32_uart_write32(efm_port, port->x_char,
145 UARTn_TXDATA);
146 port->x_char = 0;
147 continue;
148 }
149 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
150 port->icount.tx++;
151 efm32_uart_write32(efm_port, xmit->buf[xmit->tail],
152 UARTn_TXDATA);
153 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
154 } else
155 break;
156 }
157
158 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
159 uart_write_wakeup(port);
160
161 if (!port->x_char && uart_circ_empty(xmit) &&
162 efm32_uart_read32(efm_port, UARTn_STATUS) &
163 UARTn_STATUS_TXC)
164 efm32_uart_stop_tx(port);
165}
166
167static void efm32_uart_start_tx(struct uart_port *port)
168{
169 struct efm32_uart_port *efm_port = to_efm_port(port);
170 u32 ien;
171
172 efm32_uart_write32(efm_port,
173 UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IFC);
174 ien = efm32_uart_read32(efm_port, UARTn_IEN);
175 efm32_uart_write32(efm_port,
176 ien | UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IEN);
177 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
178
179 efm32_uart_tx_chars(efm_port);
180}
181
182static void efm32_uart_stop_rx(struct uart_port *port)
183{
184 struct efm32_uart_port *efm_port = to_efm_port(port);
185
186 efm32_uart_write32(efm_port, UARTn_CMD_RXDIS, UARTn_CMD);
187}
188
189static void efm32_uart_enable_ms(struct uart_port *port)
190{
191 /* no handshake lines, no modem status interrupts */
192}
193
194static void efm32_uart_break_ctl(struct uart_port *port, int ctl)
195{
196 /* not possible without fiddling with gpios */
197}
198
92a19f9c 199static void efm32_uart_rx_chars(struct efm32_uart_port *efm_port)
3afbd89c
UKK		 200{
201 struct uart_port *port = &efm_port->port;
202
203 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
204 UARTn_STATUS_RXDATAV) {
205 u32 rxdata = efm32_uart_read32(efm_port, UARTn_RXDATAX);
206 int flag = 0;
207
208 /*
209 * This is a reserved bit and I only saw it read as 0. But to be
210 * sure not to be confused too much by new devices adhere to the
211 * warning in the reference manual that reserverd bits might
212 * read as 1 in the future.
213 */
214 rxdata &= ~SW_UARTn_RXDATAX_BERR;
215
216 port->icount.rx++;
217
218 if ((rxdata & UARTn_RXDATAX_FERR) &&
219 !(rxdata & UARTn_RXDATAX_RXDATA__MASK)) {
220 rxdata |= SW_UARTn_RXDATAX_BERR;
221 port->icount.brk++;
222 if (uart_handle_break(port))
223 continue;
224 } else if (rxdata & UARTn_RXDATAX_PERR)
225 port->icount.parity++;
226 else if (rxdata & UARTn_RXDATAX_FERR)
227 port->icount.frame++;
228
229 rxdata &= port->read_status_mask;
230
231 if (rxdata & SW_UARTn_RXDATAX_BERR)
232 flag = TTY_BREAK;
233 else if (rxdata & UARTn_RXDATAX_PERR)
234 flag = TTY_PARITY;
235 else if (rxdata & UARTn_RXDATAX_FERR)
236 flag = TTY_FRAME;
237 else if (uart_handle_sysrq_char(port,
238 rxdata & UARTn_RXDATAX_RXDATA__MASK))
239 continue;
240
92a19f9c
JS		 241 if ((rxdata & port->ignore_status_mask) == 0)
242 tty_insert_flip_char(&port->state->port,
3afbd89c
UKK		 243 rxdata & UARTn_RXDATAX_RXDATA__MASK, flag);
244 }
245}
246
247static irqreturn_t efm32_uart_rxirq(int irq, void *data)
248{
249 struct efm32_uart_port *efm_port = data;
250 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
251 int handled = IRQ_NONE;
252 struct uart_port *port = &efm_port->port;
92a19f9c 253 struct tty_port *tport = &port->state->port;
3afbd89c
UKK		 254
255 spin_lock(&port->lock);
256
3afbd89c
UKK		 257 if (irqflag & UARTn_IF_RXDATAV) {
258 efm32_uart_write32(efm_port, UARTn_IF_RXDATAV, UARTn_IFC);
92a19f9c 259 efm32_uart_rx_chars(efm_port);
3afbd89c
UKK		 260
261 handled = IRQ_HANDLED;
262 }
263
264 if (irqflag & UARTn_IF_RXOF) {
265 efm32_uart_write32(efm_port, UARTn_IF_RXOF, UARTn_IFC);
266 port->icount.overrun++;
92a19f9c 267 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
3afbd89c
UKK		 268
269 handled = IRQ_HANDLED;
270 }
271
2e124b4a 272 tty_flip_buffer_push(tport);
3afbd89c
UKK		 273
274 spin_unlock(&port->lock);
275
276 return handled;
277}
278
279static irqreturn_t efm32_uart_txirq(int irq, void *data)
280{
281 struct efm32_uart_port *efm_port = data;
282 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
283
284 /* TXBL doesn't need to be cleared */
285 if (irqflag & UARTn_IF_TXC)
286 efm32_uart_write32(efm_port, UARTn_IF_TXC, UARTn_IFC);
287
288 if (irqflag & (UARTn_IF_TXC | UARTn_IF_TXBL)) {
289 efm32_uart_tx_chars(efm_port);
290 return IRQ_HANDLED;
291 } else
292 return IRQ_NONE;
293}
294
295static int efm32_uart_startup(struct uart_port *port)
296{
297 struct efm32_uart_port *efm_port = to_efm_port(port);
3afbd89c
UKK		 298 int ret;
299
3afbd89c
UKK		 300 ret = clk_enable(efm_port->clk);
301 if (ret) {
302 efm_debug(efm_port, "failed to enable clk\n");
303 goto err_clk_enable;
304 }
305 port->uartclk = clk_get_rate(efm_port->clk);
306
307 /* Enable pins at configured location */
c098020d
UKK		 308 efm32_uart_write32(efm_port,
309 UARTn_ROUTE_LOCATION(efm_port->pdata.location) |
310 UARTn_ROUTE_RXPEN | UARTn_ROUTE_TXPEN,
3afbd89c
UKK		 311 UARTn_ROUTE);
312
313 ret = request_irq(port->irq, efm32_uart_rxirq, 0,
314 DRIVER_NAME, efm_port);
315 if (ret) {
316 efm_debug(efm_port, "failed to register rxirq\n");
317 goto err_request_irq_rx;
318 }
319
320 /* disable all irqs */
321 efm32_uart_write32(efm_port, 0, UARTn_IEN);
322
323 ret = request_irq(efm_port->txirq, efm32_uart_txirq, 0,
324 DRIVER_NAME, efm_port);
325 if (ret) {
326 efm_debug(efm_port, "failed to register txirq\n");
327 free_irq(port->irq, efm_port);
328err_request_irq_rx:
329
330 clk_disable(efm_port->clk);
331 } else {
332 efm32_uart_write32(efm_port,
333 UARTn_IF_RXDATAV | UARTn_IF_RXOF, UARTn_IEN);
334 efm32_uart_write32(efm_port, UARTn_CMD_RXEN, UARTn_CMD);
335 }
336
337err_clk_enable:
338 return ret;
339}
340
341static void efm32_uart_shutdown(struct uart_port *port)
342{
343 struct efm32_uart_port *efm_port = to_efm_port(port);
344
345 efm32_uart_write32(efm_port, 0, UARTn_IEN);
346 free_irq(port->irq, efm_port);
347
348 clk_disable(efm_port->clk);
349}
350
351static void efm32_uart_set_termios(struct uart_port *port,
352 struct ktermios *new, struct ktermios *old)
353{
354 struct efm32_uart_port *efm_port = to_efm_port(port);
355 unsigned long flags;
356 unsigned baud;
357 u32 clkdiv;
358 u32 frame = 0;
359
360 /* no modem control lines */
361 new->c_cflag &= ~(CRTSCTS | CMSPAR);
362
363 baud = uart_get_baud_rate(port, new, old,
364 DIV_ROUND_CLOSEST(port->uartclk, 16 * 8192),
365 DIV_ROUND_CLOSEST(port->uartclk, 16));
366
367 switch (new->c_cflag & CSIZE) {
368 case CS5:
369 frame |= UARTn_FRAME_DATABITS(5);
370 break;
371 case CS6:
372 frame |= UARTn_FRAME_DATABITS(6);
373 break;
374 case CS7:
375 frame |= UARTn_FRAME_DATABITS(7);
376 break;
377 case CS8:
378 frame |= UARTn_FRAME_DATABITS(8);
379 break;
380 }
381
382 if (new->c_cflag & CSTOPB)
383 /* the receiver only verifies the first stop bit */
384 frame |= UARTn_FRAME_STOPBITS_TWO;
385 else
386 frame |= UARTn_FRAME_STOPBITS_ONE;
387
388 if (new->c_cflag & PARENB) {
389 if (new->c_cflag & PARODD)
390 frame |= UARTn_FRAME_PARITY_ODD;
391 else
392 frame |= UARTn_FRAME_PARITY_EVEN;
393 } else
394 frame |= UARTn_FRAME_PARITY_NONE;
395
396 /*
397 * the 6 lowest bits of CLKDIV are dc, bit 6 has value 0.25.
398 * port->uartclk <= 14e6, so 4 * port->uartclk doesn't overflow.
399 */
400 clkdiv = (DIV_ROUND_CLOSEST(4 * port->uartclk, 16 * baud) - 4) << 6;
401
402 spin_lock_irqsave(&port->lock, flags);
403
404 efm32_uart_write32(efm_port,
405 UARTn_CMD_TXDIS | UARTn_CMD_RXDIS, UARTn_CMD);
406
407 port->read_status_mask = UARTn_RXDATAX_RXDATA__MASK;
408 if (new->c_iflag & INPCK)
409 port->read_status_mask |=
410 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
411 if (new->c_iflag & (BRKINT | PARMRK))
412 port->read_status_mask |= SW_UARTn_RXDATAX_BERR;
413
414 port->ignore_status_mask = 0;
415 if (new->c_iflag & IGNPAR)
416 port->ignore_status_mask |=
417 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
418 if (new->c_iflag & IGNBRK)
419 port->ignore_status_mask |= SW_UARTn_RXDATAX_BERR;
420
421 uart_update_timeout(port, new->c_cflag, baud);
422
423 efm32_uart_write32(efm_port, UARTn_CTRL_TXBIL, UARTn_CTRL);
424 efm32_uart_write32(efm_port, frame, UARTn_FRAME);
425 efm32_uart_write32(efm_port, clkdiv, UARTn_CLKDIV);
426
427 efm32_uart_write32(efm_port, UARTn_CMD_TXEN | UARTn_CMD_RXEN,
428 UARTn_CMD);
429
430 spin_unlock_irqrestore(&port->lock, flags);
431}
432
433static const char *efm32_uart_type(struct uart_port *port)
434{
435 return port->type == PORT_EFMUART ? "efm32-uart" : NULL;
436}
437
438static void efm32_uart_release_port(struct uart_port *port)
439{
440 struct efm32_uart_port *efm_port = to_efm_port(port);
441
442 clk_unprepare(efm_port->clk);
443 clk_put(efm_port->clk);
444 iounmap(port->membase);
445}
446
447static int efm32_uart_request_port(struct uart_port *port)
448{
449 struct efm32_uart_port *efm_port = to_efm_port(port);
450 int ret;
451
452 port->membase = ioremap(port->mapbase, 60);
453 if (!efm_port->port.membase) {
454 ret = -ENOMEM;
455 efm_debug(efm_port, "failed to remap\n");
456 goto err_ioremap;
457 }
458
459 efm_port->clk = clk_get(port->dev, NULL);
460 if (IS_ERR(efm_port->clk)) {
461 ret = PTR_ERR(efm_port->clk);
462 efm_debug(efm_port, "failed to get clock\n");
463 goto err_clk_get;
464 }
465
466 ret = clk_prepare(efm_port->clk);
467 if (ret) {
468 clk_put(efm_port->clk);
469err_clk_get:
470
471 iounmap(port->membase);
472err_ioremap:
473 return ret;
474 }
475 return 0;
476}
477
478static void efm32_uart_config_port(struct uart_port *port, int type)
479{
480 if (type & UART_CONFIG_TYPE &&
481 !efm32_uart_request_port(port))
482 port->type = PORT_EFMUART;
483}
484
485static int efm32_uart_verify_port(struct uart_port *port,
486 struct serial_struct *serinfo)
487{
488 int ret = 0;
489
490 if (serinfo->type != PORT_UNKNOWN && serinfo->type != PORT_EFMUART)
491 ret = -EINVAL;
492
493 return ret;
494}
495
496static struct uart_ops efm32_uart_pops = {
497 .tx_empty = efm32_uart_tx_empty,
498 .set_mctrl = efm32_uart_set_mctrl,
499 .get_mctrl = efm32_uart_get_mctrl,
500 .stop_tx = efm32_uart_stop_tx,
501 .start_tx = efm32_uart_start_tx,
502 .stop_rx = efm32_uart_stop_rx,
503 .enable_ms = efm32_uart_enable_ms,
504 .break_ctl = efm32_uart_break_ctl,
505 .startup = efm32_uart_startup,
506 .shutdown = efm32_uart_shutdown,
507 .set_termios = efm32_uart_set_termios,
508 .type = efm32_uart_type,
509 .release_port = efm32_uart_release_port,
510 .request_port = efm32_uart_request_port,
511 .config_port = efm32_uart_config_port,
512 .verify_port = efm32_uart_verify_port,
513};
514
515static struct efm32_uart_port *efm32_uart_ports[5];
516
517#ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE
518static void efm32_uart_console_putchar(struct uart_port *port, int ch)
519{
520 struct efm32_uart_port *efm_port = to_efm_port(port);
521 unsigned int timeout = 0x400;
522 u32 status;
523
524 while (1) {
525 status = efm32_uart_read32(efm_port, UARTn_STATUS);
526
527 if (status & UARTn_STATUS_TXBL)
528 break;
529 if (!timeout--)
530 return;
531 }
532 efm32_uart_write32(efm_port, ch, UARTn_TXDATA);
533}
534
535static void efm32_uart_console_write(struct console *co, const char *s,
536 unsigned int count)
537{
538 struct efm32_uart_port *efm_port = efm32_uart_ports[co->index];
539 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
540 unsigned int timeout = 0x400;
541
542 if (!(status & UARTn_STATUS_TXENS))
543 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
544
545 uart_console_write(&efm_port->port, s, count,
546 efm32_uart_console_putchar);
547
548 /* Wait for the transmitter to become empty */
549 while (1) {
550 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
551 if (status & UARTn_STATUS_TXC)
552 break;
553 if (!timeout--)
554 break;
555 }
556
557 if (!(status & UARTn_STATUS_TXENS))
558 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
559}
560
561static void efm32_uart_console_get_options(struct efm32_uart_port *efm_port,
562 int *baud, int *parity, int *bits)
563{
564 u32 ctrl = efm32_uart_read32(efm_port, UARTn_CTRL);
565 u32 route, clkdiv, frame;
566
567 if (ctrl & UARTn_CTRL_SYNC)
568 /* not operating in async mode */
569 return;
570
571 route = efm32_uart_read32(efm_port, UARTn_ROUTE);
572 if (!(route & UARTn_ROUTE_TXPEN))
573 /* tx pin not routed */
574 return;
575
576 clkdiv = efm32_uart_read32(efm_port, UARTn_CLKDIV);
577
578 *baud = DIV_ROUND_CLOSEST(4 * efm_port->port.uartclk,
579 16 * (4 + (clkdiv >> 6)));
580
581 frame = efm32_uart_read32(efm_port, UARTn_FRAME);
12d805b5
CJ		 582 switch (frame & UARTn_FRAME_PARITY__MASK) {
583 case UARTn_FRAME_PARITY_ODD:
3afbd89c 584 *parity = 'o';
12d805b5
CJ		 585 break;
586 case UARTn_FRAME_PARITY_EVEN:
3afbd89c 587 *parity = 'e';
12d805b5
CJ		 588 break;
589 default:
3afbd89c 590 *parity = 'n';
12d805b5 591 }
3afbd89c
UKK		 592
593 *bits = (frame & UARTn_FRAME_DATABITS__MASK) -
594 UARTn_FRAME_DATABITS(4) + 4;
595
596 efm_debug(efm_port, "get_opts: options=%d%c%d\n",
597 *baud, *parity, *bits);
598}
599
600static int efm32_uart_console_setup(struct console *co, char *options)
601{
602 struct efm32_uart_port *efm_port;
603 int baud = 115200;
604 int bits = 8;
605 int parity = 'n';
606 int flow = 'n';
607 int ret;
608
609 if (co->index < 0 || co->index >= ARRAY_SIZE(efm32_uart_ports)) {
610 unsigned i;
611 for (i = 0; i < ARRAY_SIZE(efm32_uart_ports); ++i) {
612 if (efm32_uart_ports[i]) {
613 pr_warn("efm32-console: fall back to console index %u (from %hhi)\n",
614 i, co->index);
615 co->index = i;
616 break;
617 }
618 }
619 }
620
621 efm_port = efm32_uart_ports[co->index];
622 if (!efm_port) {
623 pr_warn("efm32-console: No port at %d\n", co->index);
624 return -ENODEV;
625 }
626
627 ret = clk_prepare(efm_port->clk);
628 if (ret) {
629 dev_warn(efm_port->port.dev,
630 "console: clk_prepare failed: %d\n", ret);
631 return ret;
632 }
633
634 efm_port->port.uartclk = clk_get_rate(efm_port->clk);
635
636 if (options)
637 uart_parse_options(options, &baud, &parity, &bits, &flow);
638 else
639 efm32_uart_console_get_options(efm_port,
640 &baud, &parity, &bits);
641
642 return uart_set_options(&efm_port->port, co, baud, parity, bits, flow);
643}
644
645static struct uart_driver efm32_uart_reg;
646
647static struct console efm32_uart_console = {
648 .name = DEV_NAME,
649 .write = efm32_uart_console_write,
650 .device = uart_console_device,
651 .setup = efm32_uart_console_setup,
652 .flags = CON_PRINTBUFFER,
653 .index = -1,
654 .data = &efm32_uart_reg,
655};
656
657#else
658#define efm32_uart_console (*(struct console *)NULL)
659#endif /* ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE / else */
660
661static struct uart_driver efm32_uart_reg = {
662 .owner = THIS_MODULE,
663 .driver_name = DRIVER_NAME,
664 .dev_name = DEV_NAME,
665 .nr = ARRAY_SIZE(efm32_uart_ports),
666 .cons = &efm32_uart_console,
667};
668
669static int efm32_uart_probe_dt(struct platform_device *pdev,
670 struct efm32_uart_port *efm_port)
671{
672 struct device_node *np = pdev->dev.of_node;
c098020d 673 u32 location;
3afbd89c
UKK		 674 int ret;
675
676 if (!np)
677 return 1;
678
c098020d
UKK		 679 ret = of_property_read_u32(np, "location", &location);
680 if (!ret) {
681 if (location > 5) {
682 dev_err(&pdev->dev, "invalid location\n");
683 return -EINVAL;
684 }
685 efm_debug(efm_port, "using location %u\n", location);
686 efm_port->pdata.location = location;
687 } else {
688 efm_debug(efm_port, "fall back to location 0\n");
689 }
690
3afbd89c
UKK		 691 ret = of_alias_get_id(np, "serial");
692 if (ret < 0) {
693 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
694 return ret;
695 } else {
696 efm_port->port.line = ret;
697 return 0;
698 }
699
700}
701
9671f099 702static int efm32_uart_probe(struct platform_device *pdev)
3afbd89c
UKK		 703{
704 struct efm32_uart_port *efm_port;
705 struct resource *res;
706 int ret;
707
708 efm_port = kzalloc(sizeof(*efm_port), GFP_KERNEL);
709 if (!efm_port) {
710 dev_dbg(&pdev->dev, "failed to allocate private data\n");
711 return -ENOMEM;
712 }
713
714 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
715 if (!res) {
716 ret = -ENODEV;
717 dev_dbg(&pdev->dev, "failed to determine base address\n");
718 goto err_get_base;
719 }
720
721 if (resource_size(res) < 60) {
722 ret = -EINVAL;
723 dev_dbg(&pdev->dev, "memory resource too small\n");
724 goto err_too_small;
725 }
726
727 ret = platform_get_irq(pdev, 0);
728 if (ret <= 0) {
729 dev_dbg(&pdev->dev, "failed to get rx irq\n");
730 goto err_get_rxirq;
731 }
732
733 efm_port->port.irq = ret;
734
735 ret = platform_get_irq(pdev, 1);
736 if (ret <= 0)
737 ret = efm_port->port.irq + 1;
738
739 efm_port->txirq = ret;
740
741 efm_port->port.dev = &pdev->dev;
742 efm_port->port.mapbase = res->start;
743 efm_port->port.type = PORT_EFMUART;
744 efm_port->port.iotype = UPIO_MEM32;
745 efm_port->port.fifosize = 2;
746 efm_port->port.ops = &efm32_uart_pops;
747 efm_port->port.flags = UPF_BOOT_AUTOCONF;
748
749 ret = efm32_uart_probe_dt(pdev, efm_port);
c098020d 750 if (ret > 0) {
3afbd89c 751 /* not created by device tree */
c098020d
UKK		 752 const struct efm32_uart_pdata *pdata = dev_get_platdata(&pdev->dev);
753
3afbd89c
UKK		 754 efm_port->port.line = pdev->id;
755
c098020d
UKK		 756 if (pdata)
757 efm_port->pdata = *pdata;
758 }
759
3afbd89c
UKK		 760 if (efm_port->port.line >= 0 &&
761 efm_port->port.line < ARRAY_SIZE(efm32_uart_ports))
762 efm32_uart_ports[efm_port->port.line] = efm_port;
763
764 ret = uart_add_one_port(&efm32_uart_reg, &efm_port->port);
765 if (ret) {
766 dev_dbg(&pdev->dev, "failed to add port: %d\n", ret);
767
768 if (pdev->id >= 0 && pdev->id < ARRAY_SIZE(efm32_uart_ports))
769 efm32_uart_ports[pdev->id] = NULL;
770err_get_rxirq:
771err_too_small:
772err_get_base:
773 kfree(efm_port);
774 } else {
775 platform_set_drvdata(pdev, efm_port);
776 dev_dbg(&pdev->dev, "\\o/\n");
777 }
778
779 return ret;
780}
781
ae8d8a14 782static int efm32_uart_remove(struct platform_device *pdev)
3afbd89c
UKK		 783{
784 struct efm32_uart_port *efm_port = platform_get_drvdata(pdev);
785
786 platform_set_drvdata(pdev, NULL);
787
788 uart_remove_one_port(&efm32_uart_reg, &efm_port->port);
789
790 if (pdev->id >= 0 && pdev->id < ARRAY_SIZE(efm32_uart_ports))
791 efm32_uart_ports[pdev->id] = NULL;
792
793 kfree(efm_port);
794
795 return 0;
796}
797
798static struct of_device_id efm32_uart_dt_ids[] = {
799 {
800 .compatible = "efm32,uart",
801 }, {
802 /* sentinel */
803 }
804};
805MODULE_DEVICE_TABLE(of, efm32_uart_dt_ids);
806
807static struct platform_driver efm32_uart_driver = {
808 .probe = efm32_uart_probe,
2d47b716 809 .remove = efm32_uart_remove,
3afbd89c
UKK		 810
811 .driver = {
812 .name = DRIVER_NAME,
813 .owner = THIS_MODULE,
814 .of_match_table = efm32_uart_dt_ids,
815 },
816};
817
818static int __init efm32_uart_init(void)
819{
820 int ret;
821
822 ret = uart_register_driver(&efm32_uart_reg);
823 if (ret)
824 return ret;
825
826 ret = platform_driver_register(&efm32_uart_driver);
827 if (ret)
828 uart_unregister_driver(&efm32_uart_reg);
829
830 pr_info("EFM32 UART/USART driver\n");
831
832 return ret;
833}
834module_init(efm32_uart_init);
835
836static void __exit efm32_uart_exit(void)
837{
838 platform_driver_unregister(&efm32_uart_driver);
839 uart_unregister_driver(&efm32_uart_reg);
840}
841
842MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
843MODULE_DESCRIPTION("EFM32 UART/USART driver");
844MODULE_LICENSE("GPL v2");
845MODULE_ALIAS("platform:" DRIVER_NAME);
kernel source for telekom puls (alcatel/mediatek)