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ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/dma-mapping.h> | |
53741ed8 RK |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/omap-dma.h> | |
ccdc7bf9 SO |
33 | #include <linux/platform_device.h> |
34 | #include <linux/err.h> | |
35 | #include <linux/clk.h> | |
36 | #include <linux/io.h> | |
5a0e3ad6 | 37 | #include <linux/slab.h> |
1f1a4384 | 38 | #include <linux/pm_runtime.h> |
d5a80031 BC |
39 | #include <linux/of.h> |
40 | #include <linux/of_device.h> | |
ec155afa MP |
41 | #include <linux/pinctrl/consumer.h> |
42 | #include <linux/err.h> | |
ccdc7bf9 SO |
43 | |
44 | #include <linux/spi/spi.h> | |
45 | ||
2203747c | 46 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
47 | |
48 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
27b5284c | 49 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
50 | |
51 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
52 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
53 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
54 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
55 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
56 | #define OMAP2_MCSPI_SYST 0x24 | |
57 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
58 | ||
59 | /* per-channel banks, 0x14 bytes each, first is: */ | |
60 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
61 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
62 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
63 | #define OMAP2_MCSPI_TX0 0x38 | |
64 | #define OMAP2_MCSPI_RX0 0x3c | |
65 | ||
66 | /* per-register bitmasks: */ | |
67 | ||
7a8fa725 JH |
68 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
69 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
70 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 71 | |
7a8fa725 JH |
72 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
73 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 74 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 75 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 76 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
77 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
78 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 79 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
80 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
81 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
82 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
83 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
84 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
85 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
86 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
ccdc7bf9 | 87 | |
7a8fa725 JH |
88 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
89 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
90 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
ccdc7bf9 | 91 | |
7a8fa725 | 92 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
ccdc7bf9 | 93 | |
7a8fa725 | 94 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
95 | |
96 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
97 | struct omap2_mcspi_dma { | |
53741ed8 RK |
98 | struct dma_chan *dma_tx; |
99 | struct dma_chan *dma_rx; | |
ccdc7bf9 SO |
100 | |
101 | int dma_tx_sync_dev; | |
102 | int dma_rx_sync_dev; | |
103 | ||
104 | struct completion dma_tx_completion; | |
105 | struct completion dma_rx_completion; | |
106 | }; | |
107 | ||
108 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
109 | * cache operations; better heuristics consider wordsize and bitrate. | |
110 | */ | |
8b66c134 | 111 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
112 | |
113 | ||
1bd897f8 BC |
114 | /* |
115 | * Used for context save and restore, structure members to be updated whenever | |
116 | * corresponding registers are modified. | |
117 | */ | |
118 | struct omap2_mcspi_regs { | |
119 | u32 modulctrl; | |
120 | u32 wakeupenable; | |
121 | struct list_head cs; | |
122 | }; | |
123 | ||
ccdc7bf9 | 124 | struct omap2_mcspi { |
ccdc7bf9 | 125 | struct spi_master *master; |
ccdc7bf9 SO |
126 | /* Virtual base address of the controller */ |
127 | void __iomem *base; | |
e5480b73 | 128 | unsigned long phys; |
ccdc7bf9 SO |
129 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
130 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 131 | struct device *dev; |
1bd897f8 | 132 | struct omap2_mcspi_regs ctx; |
ccdc7bf9 SO |
133 | }; |
134 | ||
135 | struct omap2_mcspi_cs { | |
136 | void __iomem *base; | |
e5480b73 | 137 | unsigned long phys; |
ccdc7bf9 | 138 | int word_len; |
89c05372 | 139 | struct list_head node; |
a41ae1ad H |
140 | /* Context save and restore shadow register */ |
141 | u32 chconf0; | |
142 | }; | |
143 | ||
ccdc7bf9 SO |
144 | static inline void mcspi_write_reg(struct spi_master *master, |
145 | int idx, u32 val) | |
146 | { | |
147 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
148 | ||
149 | __raw_writel(val, mcspi->base + idx); | |
150 | } | |
151 | ||
152 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
153 | { | |
154 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
155 | ||
156 | return __raw_readl(mcspi->base + idx); | |
157 | } | |
158 | ||
159 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
160 | int idx, u32 val) | |
161 | { | |
162 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
163 | ||
164 | __raw_writel(val, cs->base + idx); | |
165 | } | |
166 | ||
167 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
168 | { | |
169 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
170 | ||
171 | return __raw_readl(cs->base + idx); | |
172 | } | |
173 | ||
a41ae1ad H |
174 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
175 | { | |
176 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
177 | ||
178 | return cs->chconf0; | |
179 | } | |
180 | ||
181 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
182 | { | |
183 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
184 | ||
185 | cs->chconf0 = val; | |
186 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 187 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
188 | } |
189 | ||
ccdc7bf9 SO |
190 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
191 | int is_read, int enable) | |
192 | { | |
193 | u32 l, rw; | |
194 | ||
a41ae1ad | 195 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
196 | |
197 | if (is_read) /* 1 is read, 0 write */ | |
198 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
199 | else | |
200 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
201 | ||
af4e944d S |
202 | if (enable) |
203 | l |= rw; | |
204 | else | |
205 | l &= ~rw; | |
206 | ||
a41ae1ad | 207 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
208 | } |
209 | ||
210 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
211 | { | |
212 | u32 l; | |
213 | ||
214 | l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; | |
215 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); | |
4743a0f8 RT |
216 | /* Flash post-writes */ |
217 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
218 | } |
219 | ||
220 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) | |
221 | { | |
222 | u32 l; | |
223 | ||
a41ae1ad | 224 | l = mcspi_cached_chconf0(spi); |
af4e944d S |
225 | if (cs_active) |
226 | l |= OMAP2_MCSPI_CHCONF_FORCE; | |
227 | else | |
228 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
229 | ||
a41ae1ad | 230 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
231 | } |
232 | ||
233 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
234 | { | |
1bd897f8 BC |
235 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
236 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
237 | u32 l; |
238 | ||
1bd897f8 BC |
239 | /* |
240 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
241 | * to single-channel master mode |
242 | */ | |
243 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
af4e944d S |
244 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
245 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
ccdc7bf9 | 246 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
a41ae1ad | 247 | |
1bd897f8 | 248 | ctx->modulctrl = l; |
a41ae1ad H |
249 | } |
250 | ||
251 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) | |
252 | { | |
1bd897f8 BC |
253 | struct spi_master *spi_cntrl = mcspi->master; |
254 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
255 | struct omap2_mcspi_cs *cs; | |
a41ae1ad H |
256 | |
257 | /* McSPI: context restore */ | |
1bd897f8 BC |
258 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
259 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
a41ae1ad | 260 | |
1bd897f8 | 261 | list_for_each_entry(cs, &ctx->cs, node) |
89c05372 | 262 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
a41ae1ad | 263 | } |
ccdc7bf9 | 264 | |
5fda88f5 S |
265 | static int omap2_prepare_transfer(struct spi_master *master) |
266 | { | |
267 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
268 | ||
269 | pm_runtime_get_sync(mcspi->dev); | |
270 | return 0; | |
271 | } | |
272 | ||
273 | static int omap2_unprepare_transfer(struct spi_master *master) | |
274 | { | |
275 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
276 | ||
277 | pm_runtime_mark_last_busy(mcspi->dev); | |
278 | pm_runtime_put_autosuspend(mcspi->dev); | |
279 | return 0; | |
280 | } | |
281 | ||
2764c500 IK |
282 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
283 | { | |
284 | unsigned long timeout; | |
285 | ||
286 | timeout = jiffies + msecs_to_jiffies(1000); | |
287 | while (!(__raw_readl(reg) & bit)) { | |
288 | if (time_after(jiffies, timeout)) | |
289 | return -1; | |
290 | cpu_relax(); | |
291 | } | |
292 | return 0; | |
293 | } | |
294 | ||
53741ed8 RK |
295 | static void omap2_mcspi_rx_callback(void *data) |
296 | { | |
297 | struct spi_device *spi = data; | |
298 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
299 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
300 | ||
301 | complete(&mcspi_dma->dma_rx_completion); | |
302 | ||
303 | /* We must disable the DMA RX request */ | |
304 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
305 | } | |
306 | ||
307 | static void omap2_mcspi_tx_callback(void *data) | |
308 | { | |
309 | struct spi_device *spi = data; | |
310 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
311 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
312 | ||
313 | complete(&mcspi_dma->dma_tx_completion); | |
314 | ||
315 | /* We must disable the DMA TX request */ | |
316 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
317 | } | |
318 | ||
d7b4394e S |
319 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
320 | struct spi_transfer *xfer, | |
321 | struct dma_slave_config cfg) | |
ccdc7bf9 SO |
322 | { |
323 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 | 324 | struct omap2_mcspi_dma *mcspi_dma; |
8c7494a5 | 325 | unsigned int count; |
ccdc7bf9 SO |
326 | const u8 * tx; |
327 | ||
328 | mcspi = spi_master_get_devdata(spi->master); | |
329 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
d7b4394e | 330 | count = xfer->len; |
ccdc7bf9 | 331 | |
d7b4394e | 332 | tx = xfer->tx_buf; |
2764c500 | 333 | |
d7b4394e | 334 | if (mcspi_dma->dma_tx) { |
53741ed8 RK |
335 | struct dma_async_tx_descriptor *tx; |
336 | struct scatterlist sg; | |
337 | ||
338 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
339 | ||
340 | sg_init_table(&sg, 1); | |
341 | sg_dma_address(&sg) = xfer->tx_dma; | |
342 | sg_dma_len(&sg) = xfer->len; | |
343 | ||
344 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, | |
d7b4394e | 345 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
53741ed8 RK |
346 | if (tx) { |
347 | tx->callback = omap2_mcspi_tx_callback; | |
348 | tx->callback_param = spi; | |
349 | dmaengine_submit(tx); | |
350 | } else { | |
351 | /* FIXME: fall back to PIO? */ | |
352 | } | |
353 | } | |
d7b4394e S |
354 | dma_async_issue_pending(mcspi_dma->dma_tx); |
355 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
356 | ||
d7b4394e | 357 | } |
53741ed8 | 358 | |
d7b4394e S |
359 | static unsigned |
360 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | |
361 | struct dma_slave_config cfg, | |
362 | unsigned es) | |
363 | { | |
364 | struct omap2_mcspi *mcspi; | |
365 | struct omap2_mcspi_dma *mcspi_dma; | |
366 | unsigned int count; | |
367 | u32 l; | |
368 | int elements = 0; | |
369 | int word_len, element_count; | |
370 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
371 | mcspi = spi_master_get_devdata(spi->master); | |
372 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
373 | count = xfer->len; | |
374 | word_len = cs->word_len; | |
375 | l = mcspi_cached_chconf0(spi); | |
53741ed8 | 376 | |
d7b4394e S |
377 | if (word_len <= 8) |
378 | element_count = count; | |
379 | else if (word_len <= 16) | |
380 | element_count = count >> 1; | |
381 | else /* word_len <= 32 */ | |
382 | element_count = count >> 2; | |
383 | ||
384 | if (mcspi_dma->dma_rx) { | |
53741ed8 RK |
385 | struct dma_async_tx_descriptor *tx; |
386 | struct scatterlist sg; | |
387 | size_t len = xfer->len - es; | |
388 | ||
389 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
390 | ||
391 | if (l & OMAP2_MCSPI_CHCONF_TURBO) | |
392 | len -= es; | |
393 | ||
394 | sg_init_table(&sg, 1); | |
395 | sg_dma_address(&sg) = xfer->rx_dma; | |
396 | sg_dma_len(&sg) = len; | |
397 | ||
398 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, | |
d7b4394e S |
399 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | |
400 | DMA_CTRL_ACK); | |
53741ed8 RK |
401 | if (tx) { |
402 | tx->callback = omap2_mcspi_rx_callback; | |
403 | tx->callback_param = spi; | |
404 | dmaengine_submit(tx); | |
405 | } else { | |
d7b4394e | 406 | /* FIXME: fall back to PIO? */ |
2764c500 | 407 | } |
ccdc7bf9 SO |
408 | } |
409 | ||
d7b4394e S |
410 | dma_async_issue_pending(mcspi_dma->dma_rx); |
411 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
4743a0f8 | 412 | |
d7b4394e S |
413 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
414 | dma_unmap_single(mcspi->dev, xfer->rx_dma, count, | |
415 | DMA_FROM_DEVICE); | |
416 | omap2_mcspi_set_enable(spi, 0); | |
53741ed8 | 417 | |
d7b4394e | 418 | elements = element_count - 1; |
4743a0f8 | 419 | |
d7b4394e S |
420 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
421 | elements--; | |
4743a0f8 | 422 | |
57c5c28d | 423 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
d7b4394e | 424 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
57c5c28d EN |
425 | u32 w; |
426 | ||
427 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
428 | if (word_len <= 8) | |
d7b4394e | 429 | ((u8 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 430 | else if (word_len <= 16) |
d7b4394e | 431 | ((u16 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 432 | else /* word_len <= 32 */ |
d7b4394e | 433 | ((u32 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 434 | } else { |
d7b4394e S |
435 | dev_err(&spi->dev, "DMA RX penultimate word empty"); |
436 | count -= (word_len <= 8) ? 2 : | |
437 | (word_len <= 16) ? 4 : | |
438 | /* word_len <= 32 */ 8; | |
439 | omap2_mcspi_set_enable(spi, 1); | |
440 | return count; | |
57c5c28d | 441 | } |
ccdc7bf9 | 442 | } |
d7b4394e S |
443 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
444 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
445 | u32 w; | |
446 | ||
447 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
448 | if (word_len <= 8) | |
449 | ((u8 *)xfer->rx_buf)[elements] = w; | |
450 | else if (word_len <= 16) | |
451 | ((u16 *)xfer->rx_buf)[elements] = w; | |
452 | else /* word_len <= 32 */ | |
453 | ((u32 *)xfer->rx_buf)[elements] = w; | |
454 | } else { | |
455 | dev_err(&spi->dev, "DMA RX last word empty"); | |
456 | count -= (word_len <= 8) ? 1 : | |
457 | (word_len <= 16) ? 2 : | |
458 | /* word_len <= 32 */ 4; | |
459 | } | |
460 | omap2_mcspi_set_enable(spi, 1); | |
461 | return count; | |
462 | } | |
463 | ||
464 | static unsigned | |
465 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
466 | { | |
467 | struct omap2_mcspi *mcspi; | |
468 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
469 | struct omap2_mcspi_dma *mcspi_dma; | |
470 | unsigned int count; | |
471 | u32 l; | |
472 | u8 *rx; | |
473 | const u8 *tx; | |
474 | struct dma_slave_config cfg; | |
475 | enum dma_slave_buswidth width; | |
476 | unsigned es; | |
e47a682a | 477 | void __iomem *chstat_reg; |
d7b4394e S |
478 | |
479 | mcspi = spi_master_get_devdata(spi->master); | |
480 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
481 | l = mcspi_cached_chconf0(spi); | |
482 | ||
483 | ||
484 | if (cs->word_len <= 8) { | |
485 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
486 | es = 1; | |
487 | } else if (cs->word_len <= 16) { | |
488 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
489 | es = 2; | |
490 | } else { | |
491 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
492 | es = 4; | |
493 | } | |
494 | ||
495 | memset(&cfg, 0, sizeof(cfg)); | |
496 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
497 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
498 | cfg.src_addr_width = width; | |
499 | cfg.dst_addr_width = width; | |
500 | cfg.src_maxburst = 1; | |
501 | cfg.dst_maxburst = 1; | |
502 | ||
503 | rx = xfer->rx_buf; | |
504 | tx = xfer->tx_buf; | |
505 | ||
506 | count = xfer->len; | |
507 | ||
508 | if (tx != NULL) | |
509 | omap2_mcspi_tx_dma(spi, xfer, cfg); | |
510 | ||
511 | if (rx != NULL) | |
e47a682a S |
512 | count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); |
513 | ||
514 | if (tx != NULL) { | |
515 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; | |
516 | wait_for_completion(&mcspi_dma->dma_tx_completion); | |
517 | dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, | |
518 | DMA_TO_DEVICE); | |
519 | ||
520 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
521 | if (rx == NULL) { | |
522 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
523 | OMAP2_MCSPI_CHSTAT_TXS) < 0) | |
524 | dev_err(&spi->dev, "TXS timed out\n"); | |
525 | else if (mcspi_wait_for_reg_bit(chstat_reg, | |
526 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
527 | dev_err(&spi->dev, "EOT timed out\n"); | |
528 | } | |
529 | } | |
ccdc7bf9 SO |
530 | return count; |
531 | } | |
532 | ||
ccdc7bf9 SO |
533 | static unsigned |
534 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
535 | { | |
536 | struct omap2_mcspi *mcspi; | |
537 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
538 | unsigned int count, c; | |
539 | u32 l; | |
540 | void __iomem *base = cs->base; | |
541 | void __iomem *tx_reg; | |
542 | void __iomem *rx_reg; | |
543 | void __iomem *chstat_reg; | |
544 | int word_len; | |
545 | ||
546 | mcspi = spi_master_get_devdata(spi->master); | |
547 | count = xfer->len; | |
548 | c = count; | |
549 | word_len = cs->word_len; | |
550 | ||
a41ae1ad | 551 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
552 | |
553 | /* We store the pre-calculated register addresses on stack to speed | |
554 | * up the transfer loop. */ | |
555 | tx_reg = base + OMAP2_MCSPI_TX0; | |
556 | rx_reg = base + OMAP2_MCSPI_RX0; | |
557 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
558 | ||
adef658d MJ |
559 | if (c < (word_len>>3)) |
560 | return 0; | |
561 | ||
ccdc7bf9 SO |
562 | if (word_len <= 8) { |
563 | u8 *rx; | |
564 | const u8 *tx; | |
565 | ||
566 | rx = xfer->rx_buf; | |
567 | tx = xfer->tx_buf; | |
568 | ||
569 | do { | |
feed9bab | 570 | c -= 1; |
ccdc7bf9 SO |
571 | if (tx != NULL) { |
572 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
573 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
574 | dev_err(&spi->dev, "TXS timed out\n"); | |
575 | goto out; | |
576 | } | |
079a176d | 577 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 578 | word_len, *tx); |
ccdc7bf9 SO |
579 | __raw_writel(*tx++, tx_reg); |
580 | } | |
581 | if (rx != NULL) { | |
582 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
583 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
584 | dev_err(&spi->dev, "RXS timed out\n"); | |
585 | goto out; | |
586 | } | |
4743a0f8 RT |
587 | |
588 | if (c == 1 && tx == NULL && | |
589 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
590 | omap2_mcspi_set_enable(spi, 0); | |
591 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 592 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 593 | word_len, *(rx - 1)); |
4743a0f8 RT |
594 | if (mcspi_wait_for_reg_bit(chstat_reg, |
595 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
596 | dev_err(&spi->dev, | |
597 | "RXS timed out\n"); | |
598 | goto out; | |
599 | } | |
600 | c = 0; | |
601 | } else if (c == 0 && tx == NULL) { | |
602 | omap2_mcspi_set_enable(spi, 0); | |
603 | } | |
604 | ||
ccdc7bf9 | 605 | *rx++ = __raw_readl(rx_reg); |
079a176d | 606 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 607 | word_len, *(rx - 1)); |
ccdc7bf9 | 608 | } |
95c5c3ab | 609 | } while (c); |
ccdc7bf9 SO |
610 | } else if (word_len <= 16) { |
611 | u16 *rx; | |
612 | const u16 *tx; | |
613 | ||
614 | rx = xfer->rx_buf; | |
615 | tx = xfer->tx_buf; | |
616 | do { | |
feed9bab | 617 | c -= 2; |
ccdc7bf9 SO |
618 | if (tx != NULL) { |
619 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
620 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
621 | dev_err(&spi->dev, "TXS timed out\n"); | |
622 | goto out; | |
623 | } | |
079a176d | 624 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 625 | word_len, *tx); |
ccdc7bf9 SO |
626 | __raw_writel(*tx++, tx_reg); |
627 | } | |
628 | if (rx != NULL) { | |
629 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
630 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
631 | dev_err(&spi->dev, "RXS timed out\n"); | |
632 | goto out; | |
633 | } | |
4743a0f8 RT |
634 | |
635 | if (c == 2 && tx == NULL && | |
636 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
637 | omap2_mcspi_set_enable(spi, 0); | |
638 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 639 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 640 | word_len, *(rx - 1)); |
4743a0f8 RT |
641 | if (mcspi_wait_for_reg_bit(chstat_reg, |
642 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
643 | dev_err(&spi->dev, | |
644 | "RXS timed out\n"); | |
645 | goto out; | |
646 | } | |
647 | c = 0; | |
648 | } else if (c == 0 && tx == NULL) { | |
649 | omap2_mcspi_set_enable(spi, 0); | |
650 | } | |
651 | ||
ccdc7bf9 | 652 | *rx++ = __raw_readl(rx_reg); |
079a176d | 653 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 654 | word_len, *(rx - 1)); |
ccdc7bf9 | 655 | } |
95c5c3ab | 656 | } while (c >= 2); |
ccdc7bf9 SO |
657 | } else if (word_len <= 32) { |
658 | u32 *rx; | |
659 | const u32 *tx; | |
660 | ||
661 | rx = xfer->rx_buf; | |
662 | tx = xfer->tx_buf; | |
663 | do { | |
feed9bab | 664 | c -= 4; |
ccdc7bf9 SO |
665 | if (tx != NULL) { |
666 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
667 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
668 | dev_err(&spi->dev, "TXS timed out\n"); | |
669 | goto out; | |
670 | } | |
079a176d | 671 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 672 | word_len, *tx); |
ccdc7bf9 SO |
673 | __raw_writel(*tx++, tx_reg); |
674 | } | |
675 | if (rx != NULL) { | |
676 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
677 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
678 | dev_err(&spi->dev, "RXS timed out\n"); | |
679 | goto out; | |
680 | } | |
4743a0f8 RT |
681 | |
682 | if (c == 4 && tx == NULL && | |
683 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
684 | omap2_mcspi_set_enable(spi, 0); | |
685 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 686 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 687 | word_len, *(rx - 1)); |
4743a0f8 RT |
688 | if (mcspi_wait_for_reg_bit(chstat_reg, |
689 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
690 | dev_err(&spi->dev, | |
691 | "RXS timed out\n"); | |
692 | goto out; | |
693 | } | |
694 | c = 0; | |
695 | } else if (c == 0 && tx == NULL) { | |
696 | omap2_mcspi_set_enable(spi, 0); | |
697 | } | |
698 | ||
ccdc7bf9 | 699 | *rx++ = __raw_readl(rx_reg); |
079a176d | 700 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 701 | word_len, *(rx - 1)); |
ccdc7bf9 | 702 | } |
95c5c3ab | 703 | } while (c >= 4); |
ccdc7bf9 SO |
704 | } |
705 | ||
706 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
707 | if (xfer->rx_buf == NULL) { | |
708 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
709 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
710 | dev_err(&spi->dev, "TXS timed out\n"); | |
711 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
712 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
713 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
714 | |
715 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
716 | * otherwise these rx datas will affect the direct following | |
717 | * RX_ONLY transfer. | |
718 | */ | |
719 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
720 | } |
721 | out: | |
4743a0f8 | 722 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
723 | return count - c; |
724 | } | |
725 | ||
57d9c10d HH |
726 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
727 | { | |
728 | u32 div; | |
729 | ||
730 | for (div = 0; div < 15; div++) | |
731 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
732 | return div; | |
733 | ||
734 | return 15; | |
735 | } | |
736 | ||
ccdc7bf9 SO |
737 | /* called only when no transfer is active to this device */ |
738 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
739 | struct spi_transfer *t) | |
740 | { | |
741 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
742 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 743 | struct spi_master *spi_cntrl; |
ccdc7bf9 SO |
744 | u32 l = 0, div = 0; |
745 | u8 word_len = spi->bits_per_word; | |
9bd4517d | 746 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
747 | |
748 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 749 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
750 | |
751 | if (t != NULL && t->bits_per_word) | |
752 | word_len = t->bits_per_word; | |
753 | ||
754 | cs->word_len = word_len; | |
755 | ||
9bd4517d SE |
756 | if (t && t->speed_hz) |
757 | speed_hz = t->speed_hz; | |
758 | ||
57d9c10d HH |
759 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
760 | div = omap2_mcspi_calc_divisor(speed_hz); | |
ccdc7bf9 | 761 | |
a41ae1ad | 762 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
763 | |
764 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
765 | * REVISIT: this controller could support SPI_3WIRE mode. | |
766 | */ | |
767 | l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1); | |
768 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
769 | ||
770 | /* wordlength */ | |
771 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
772 | l |= (word_len - 1) << 7; | |
773 | ||
774 | /* set chipselect polarity; manage with FORCE */ | |
775 | if (!(spi->mode & SPI_CS_HIGH)) | |
776 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
777 | else | |
778 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
779 | ||
780 | /* set clock divisor */ | |
781 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
782 | l |= div << 2; | |
783 | ||
784 | /* set SPI mode 0..3 */ | |
785 | if (spi->mode & SPI_CPOL) | |
786 | l |= OMAP2_MCSPI_CHCONF_POL; | |
787 | else | |
788 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
789 | if (spi->mode & SPI_CPHA) | |
790 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
791 | else | |
792 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
793 | ||
a41ae1ad | 794 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
795 | |
796 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", | |
57d9c10d | 797 | OMAP2_MCSPI_MAX_FREQ >> div, |
ccdc7bf9 SO |
798 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
799 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
800 | ||
801 | return 0; | |
802 | } | |
803 | ||
ccdc7bf9 SO |
804 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
805 | { | |
806 | struct spi_master *master = spi->master; | |
807 | struct omap2_mcspi *mcspi; | |
808 | struct omap2_mcspi_dma *mcspi_dma; | |
53741ed8 RK |
809 | dma_cap_mask_t mask; |
810 | unsigned sig; | |
ccdc7bf9 SO |
811 | |
812 | mcspi = spi_master_get_devdata(master); | |
813 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
814 | ||
53741ed8 RK |
815 | init_completion(&mcspi_dma->dma_rx_completion); |
816 | init_completion(&mcspi_dma->dma_tx_completion); | |
817 | ||
818 | dma_cap_zero(mask); | |
819 | dma_cap_set(DMA_SLAVE, mask); | |
53741ed8 RK |
820 | sig = mcspi_dma->dma_rx_sync_dev; |
821 | mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
822 | if (!mcspi_dma->dma_rx) { | |
823 | dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n"); | |
ccdc7bf9 SO |
824 | return -EAGAIN; |
825 | } | |
826 | ||
53741ed8 RK |
827 | sig = mcspi_dma->dma_tx_sync_dev; |
828 | mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
829 | if (!mcspi_dma->dma_tx) { | |
830 | dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n"); | |
831 | dma_release_channel(mcspi_dma->dma_rx); | |
832 | mcspi_dma->dma_rx = NULL; | |
ccdc7bf9 SO |
833 | return -EAGAIN; |
834 | } | |
835 | ||
ccdc7bf9 SO |
836 | return 0; |
837 | } | |
838 | ||
ccdc7bf9 SO |
839 | static int omap2_mcspi_setup(struct spi_device *spi) |
840 | { | |
841 | int ret; | |
1bd897f8 BC |
842 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
843 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
844 | struct omap2_mcspi_dma *mcspi_dma; |
845 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
846 | ||
7d077197 | 847 | if (spi->bits_per_word < 4 || spi->bits_per_word > 32) { |
ccdc7bf9 SO |
848 | dev_dbg(&spi->dev, "setup: unsupported %d bit words\n", |
849 | spi->bits_per_word); | |
850 | return -EINVAL; | |
851 | } | |
852 | ||
ccdc7bf9 SO |
853 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
854 | ||
855 | if (!cs) { | |
10aa5a35 | 856 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
857 | if (!cs) |
858 | return -ENOMEM; | |
859 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 860 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
a41ae1ad | 861 | cs->chconf0 = 0; |
ccdc7bf9 | 862 | spi->controller_state = cs; |
89c05372 | 863 | /* Link this to context save list */ |
1bd897f8 | 864 | list_add_tail(&cs->node, &ctx->cs); |
ccdc7bf9 SO |
865 | } |
866 | ||
8c7494a5 | 867 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 SO |
868 | ret = omap2_mcspi_request_dma(spi); |
869 | if (ret < 0) | |
870 | return ret; | |
871 | } | |
872 | ||
034d3dc9 | 873 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
874 | if (ret < 0) |
875 | return ret; | |
a41ae1ad | 876 | |
86eeb6fe | 877 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
034d3dc9 S |
878 | pm_runtime_mark_last_busy(mcspi->dev); |
879 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
880 | |
881 | return ret; | |
882 | } | |
883 | ||
884 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
885 | { | |
886 | struct omap2_mcspi *mcspi; | |
887 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 888 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
889 | |
890 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 891 | |
5e774943 SE |
892 | if (spi->controller_state) { |
893 | /* Unlink controller state from context save list */ | |
894 | cs = spi->controller_state; | |
895 | list_del(&cs->node); | |
89c05372 | 896 | |
10aa5a35 | 897 | kfree(cs); |
5e774943 | 898 | } |
ccdc7bf9 | 899 | |
99f1a43f SE |
900 | if (spi->chip_select < spi->master->num_chipselect) { |
901 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
902 | ||
53741ed8 RK |
903 | if (mcspi_dma->dma_rx) { |
904 | dma_release_channel(mcspi_dma->dma_rx); | |
905 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 906 | } |
53741ed8 RK |
907 | if (mcspi_dma->dma_tx) { |
908 | dma_release_channel(mcspi_dma->dma_tx); | |
909 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 910 | } |
ccdc7bf9 SO |
911 | } |
912 | } | |
913 | ||
5fda88f5 | 914 | static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) |
ccdc7bf9 | 915 | { |
ccdc7bf9 SO |
916 | |
917 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 918 | * -- although this controller would gladly |
ccdc7bf9 SO |
919 | * arbitrate among multiple channels. This corresponds to "single |
920 | * channel" master mode. As a side effect, we need to manage the | |
921 | * chipselect with the FORCE bit ... CS != channel enable. | |
922 | */ | |
ccdc7bf9 | 923 | |
5fda88f5 S |
924 | struct spi_device *spi; |
925 | struct spi_transfer *t = NULL; | |
926 | int cs_active = 0; | |
927 | struct omap2_mcspi_cs *cs; | |
928 | struct omap2_mcspi_device_config *cd; | |
929 | int par_override = 0; | |
930 | int status = 0; | |
931 | u32 chconf; | |
ccdc7bf9 | 932 | |
5fda88f5 S |
933 | spi = m->spi; |
934 | cs = spi->controller_state; | |
935 | cd = spi->controller_data; | |
ccdc7bf9 | 936 | |
5fda88f5 S |
937 | omap2_mcspi_set_enable(spi, 1); |
938 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
939 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { | |
940 | status = -EINVAL; | |
941 | break; | |
942 | } | |
943 | if (par_override || t->speed_hz || t->bits_per_word) { | |
944 | par_override = 1; | |
945 | status = omap2_mcspi_setup_transfer(spi, t); | |
946 | if (status < 0) | |
947 | break; | |
948 | if (!t->speed_hz && !t->bits_per_word) | |
949 | par_override = 0; | |
950 | } | |
4743a0f8 | 951 | |
5fda88f5 S |
952 | if (!cs_active) { |
953 | omap2_mcspi_force_cs(spi, 1); | |
954 | cs_active = 1; | |
955 | } | |
4743a0f8 | 956 | |
5fda88f5 S |
957 | chconf = mcspi_cached_chconf0(spi); |
958 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
959 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
ccdc7bf9 | 960 | |
5fda88f5 S |
961 | if (t->tx_buf == NULL) |
962 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
963 | else if (t->rx_buf == NULL) | |
964 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
ccdc7bf9 | 965 | |
5fda88f5 S |
966 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
967 | /* Turbo mode is for more than one word */ | |
968 | if (t->len > ((cs->word_len + 7) >> 3)) | |
969 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
970 | } | |
ccdc7bf9 | 971 | |
5fda88f5 | 972 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 973 | |
5fda88f5 S |
974 | if (t->len) { |
975 | unsigned count; | |
976 | ||
977 | /* RX_ONLY mode needs dummy data in TX reg */ | |
978 | if (t->tx_buf == NULL) | |
979 | __raw_writel(0, cs->base | |
980 | + OMAP2_MCSPI_TX0); | |
ccdc7bf9 | 981 | |
5fda88f5 S |
982 | if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) |
983 | count = omap2_mcspi_txrx_dma(spi, t); | |
984 | else | |
985 | count = omap2_mcspi_txrx_pio(spi, t); | |
986 | m->actual_length += count; | |
ccdc7bf9 | 987 | |
5fda88f5 S |
988 | if (count != t->len) { |
989 | status = -EIO; | |
990 | break; | |
ccdc7bf9 SO |
991 | } |
992 | } | |
993 | ||
5fda88f5 S |
994 | if (t->delay_usecs) |
995 | udelay(t->delay_usecs); | |
ccdc7bf9 | 996 | |
5fda88f5 S |
997 | /* ignore the "leave it on after last xfer" hint */ |
998 | if (t->cs_change) { | |
ccdc7bf9 | 999 | omap2_mcspi_force_cs(spi, 0); |
5fda88f5 S |
1000 | cs_active = 0; |
1001 | } | |
1002 | } | |
1003 | /* Restore defaults if they were overriden */ | |
1004 | if (par_override) { | |
1005 | par_override = 0; | |
1006 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
1007 | } | |
ccdc7bf9 | 1008 | |
5fda88f5 S |
1009 | if (cs_active) |
1010 | omap2_mcspi_force_cs(spi, 0); | |
ccdc7bf9 | 1011 | |
5fda88f5 | 1012 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 1013 | |
5fda88f5 | 1014 | m->status = status; |
1f1a4384 | 1015 | |
ccdc7bf9 SO |
1016 | } |
1017 | ||
5fda88f5 S |
1018 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, |
1019 | struct spi_message *m) | |
ccdc7bf9 SO |
1020 | { |
1021 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 SO |
1022 | struct spi_transfer *t; |
1023 | ||
5fda88f5 | 1024 | mcspi = spi_master_get_devdata(master); |
ccdc7bf9 SO |
1025 | m->actual_length = 0; |
1026 | m->status = 0; | |
1027 | ||
1028 | /* reject invalid messages and transfers */ | |
5fda88f5 | 1029 | if (list_empty(&m->transfers)) |
ccdc7bf9 SO |
1030 | return -EINVAL; |
1031 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
1032 | const void *tx_buf = t->tx_buf; | |
1033 | void *rx_buf = t->rx_buf; | |
1034 | unsigned len = t->len; | |
1035 | ||
1036 | if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ | |
1037 | || (len && !(rx_buf || tx_buf)) | |
1038 | || (t->bits_per_word && | |
1039 | ( t->bits_per_word < 4 | |
1040 | || t->bits_per_word > 32))) { | |
5fda88f5 | 1041 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
ccdc7bf9 SO |
1042 | t->speed_hz, |
1043 | len, | |
1044 | tx_buf ? "tx" : "", | |
1045 | rx_buf ? "rx" : "", | |
1046 | t->bits_per_word); | |
1047 | return -EINVAL; | |
1048 | } | |
57d9c10d | 1049 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { |
5fda88f5 | 1050 | dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", |
57d9c10d HH |
1051 | t->speed_hz, |
1052 | OMAP2_MCSPI_MAX_FREQ >> 15); | |
ccdc7bf9 SO |
1053 | return -EINVAL; |
1054 | } | |
1055 | ||
1056 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) | |
1057 | continue; | |
1058 | ||
ccdc7bf9 | 1059 | if (tx_buf != NULL) { |
5fda88f5 | 1060 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, |
ccdc7bf9 | 1061 | len, DMA_TO_DEVICE); |
5fda88f5 S |
1062 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { |
1063 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1064 | 'T', len); |
1065 | return -EINVAL; | |
1066 | } | |
1067 | } | |
1068 | if (rx_buf != NULL) { | |
5fda88f5 | 1069 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, |
ccdc7bf9 | 1070 | DMA_FROM_DEVICE); |
5fda88f5 S |
1071 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { |
1072 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1073 | 'R', len); |
1074 | if (tx_buf != NULL) | |
5fda88f5 | 1075 | dma_unmap_single(mcspi->dev, t->tx_dma, |
ccdc7bf9 SO |
1076 | len, DMA_TO_DEVICE); |
1077 | return -EINVAL; | |
1078 | } | |
1079 | } | |
1080 | } | |
1081 | ||
5fda88f5 S |
1082 | omap2_mcspi_work(mcspi, m); |
1083 | spi_finalize_current_message(master); | |
ccdc7bf9 SO |
1084 | return 0; |
1085 | } | |
1086 | ||
24ab3275 | 1087 | static int __devinit omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1088 | { |
1089 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1090 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1091 | int ret = 0; |
ccdc7bf9 | 1092 | |
034d3dc9 | 1093 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1094 | if (ret < 0) |
1095 | return ret; | |
ddb22195 | 1096 | |
39f8052d S |
1097 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
1098 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); | |
1099 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; | |
ccdc7bf9 SO |
1100 | |
1101 | omap2_mcspi_set_master_mode(master); | |
034d3dc9 S |
1102 | pm_runtime_mark_last_busy(mcspi->dev); |
1103 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1104 | return 0; |
1105 | } | |
1106 | ||
1f1a4384 G |
1107 | static int omap_mcspi_runtime_resume(struct device *dev) |
1108 | { | |
1109 | struct omap2_mcspi *mcspi; | |
1110 | struct spi_master *master; | |
1111 | ||
1112 | master = dev_get_drvdata(dev); | |
1113 | mcspi = spi_master_get_devdata(master); | |
1114 | omap2_mcspi_restore_ctx(mcspi); | |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | ||
d5a80031 BC |
1119 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1120 | .regs_offset = 0, | |
1121 | }; | |
1122 | ||
1123 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1124 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1125 | }; | |
1126 | ||
1127 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1128 | { | |
1129 | .compatible = "ti,omap2-mcspi", | |
1130 | .data = &omap2_pdata, | |
1131 | }, | |
1132 | { | |
1133 | .compatible = "ti,omap4-mcspi", | |
1134 | .data = &omap4_pdata, | |
1135 | }, | |
1136 | { }, | |
1137 | }; | |
1138 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1139 | |
7d6b6d83 | 1140 | static int __devinit omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1141 | { |
1142 | struct spi_master *master; | |
83a01e72 | 1143 | const struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1144 | struct omap2_mcspi *mcspi; |
1145 | struct resource *r; | |
1146 | int status = 0, i; | |
d5a80031 BC |
1147 | u32 regs_offset = 0; |
1148 | static int bus_num = 1; | |
1149 | struct device_node *node = pdev->dev.of_node; | |
1150 | const struct of_device_id *match; | |
ec155afa | 1151 | struct pinctrl *pinctrl; |
ccdc7bf9 SO |
1152 | |
1153 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1154 | if (master == NULL) { | |
1155 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1156 | return -ENOMEM; | |
1157 | } | |
1158 | ||
e7db06b5 DB |
1159 | /* the spi->mode bits understood by this driver: */ |
1160 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
1161 | ||
ccdc7bf9 | 1162 | master->setup = omap2_mcspi_setup; |
5fda88f5 S |
1163 | master->prepare_transfer_hardware = omap2_prepare_transfer; |
1164 | master->unprepare_transfer_hardware = omap2_unprepare_transfer; | |
1165 | master->transfer_one_message = omap2_mcspi_transfer_one_message; | |
ccdc7bf9 | 1166 | master->cleanup = omap2_mcspi_cleanup; |
d5a80031 BC |
1167 | master->dev.of_node = node; |
1168 | ||
1169 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); | |
1170 | if (match) { | |
1171 | u32 num_cs = 1; /* default number of chipselect */ | |
1172 | pdata = match->data; | |
1173 | ||
1174 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1175 | master->num_chipselect = num_cs; | |
1176 | master->bus_num = bus_num++; | |
1177 | } else { | |
1178 | pdata = pdev->dev.platform_data; | |
1179 | master->num_chipselect = pdata->num_cs; | |
1180 | if (pdev->id != -1) | |
1181 | master->bus_num = pdev->id; | |
1182 | } | |
1183 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 SO |
1184 | |
1185 | dev_set_drvdata(&pdev->dev, master); | |
1186 | ||
1187 | mcspi = spi_master_get_devdata(master); | |
1188 | mcspi->master = master; | |
1189 | ||
1190 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1191 | if (r == NULL) { | |
1192 | status = -ENODEV; | |
39f1b565 | 1193 | goto free_master; |
ccdc7bf9 | 1194 | } |
1458d160 | 1195 | |
d5a80031 BC |
1196 | r->start += regs_offset; |
1197 | r->end += regs_offset; | |
1458d160 | 1198 | mcspi->phys = r->start; |
ccdc7bf9 | 1199 | |
1a77b127 | 1200 | mcspi->base = devm_request_and_ioremap(&pdev->dev, r); |
55c381e4 RK |
1201 | if (!mcspi->base) { |
1202 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); | |
1203 | status = -ENOMEM; | |
1a77b127 | 1204 | goto free_master; |
55c381e4 | 1205 | } |
ccdc7bf9 | 1206 | |
1f1a4384 | 1207 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1208 | |
1bd897f8 | 1209 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1210 | |
ccdc7bf9 SO |
1211 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
1212 | sizeof(struct omap2_mcspi_dma), | |
1213 | GFP_KERNEL); | |
1214 | ||
1215 | if (mcspi->dma_channels == NULL) | |
1a77b127 | 1216 | goto free_master; |
ccdc7bf9 | 1217 | |
1a5d8190 C |
1218 | for (i = 0; i < master->num_chipselect; i++) { |
1219 | char dma_ch_name[14]; | |
1220 | struct resource *dma_res; | |
1221 | ||
1222 | sprintf(dma_ch_name, "rx%d", i); | |
1223 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | |
1224 | dma_ch_name); | |
1225 | if (!dma_res) { | |
1226 | dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); | |
1227 | status = -ENODEV; | |
1228 | break; | |
1229 | } | |
1230 | ||
1a5d8190 C |
1231 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; |
1232 | sprintf(dma_ch_name, "tx%d", i); | |
1233 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | |
1234 | dma_ch_name); | |
1235 | if (!dma_res) { | |
1236 | dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); | |
1237 | status = -ENODEV; | |
1238 | break; | |
1239 | } | |
1240 | ||
1a5d8190 | 1241 | mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; |
ccdc7bf9 SO |
1242 | } |
1243 | ||
39f1b565 S |
1244 | if (status < 0) |
1245 | goto dma_chnl_free; | |
1246 | ||
ec155afa MP |
1247 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1248 | if (IS_ERR(pinctrl)) | |
1249 | dev_warn(&pdev->dev, | |
1250 | "pins are not configured from the driver\n"); | |
1251 | ||
27b5284c S |
1252 | pm_runtime_use_autosuspend(&pdev->dev); |
1253 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1254 | pm_runtime_enable(&pdev->dev); |
1255 | ||
1256 | if (status || omap2_mcspi_master_setup(mcspi) < 0) | |
39f1b565 | 1257 | goto disable_pm; |
ccdc7bf9 SO |
1258 | |
1259 | status = spi_register_master(master); | |
1260 | if (status < 0) | |
37a2d84a | 1261 | goto disable_pm; |
ccdc7bf9 SO |
1262 | |
1263 | return status; | |
1264 | ||
39f1b565 | 1265 | disable_pm: |
751c925c | 1266 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1267 | dma_chnl_free: |
1f1a4384 | 1268 | kfree(mcspi->dma_channels); |
39f1b565 | 1269 | free_master: |
37a2d84a | 1270 | spi_master_put(master); |
ccdc7bf9 SO |
1271 | return status; |
1272 | } | |
1273 | ||
7d6b6d83 | 1274 | static int __devexit omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 SO |
1275 | { |
1276 | struct spi_master *master; | |
1277 | struct omap2_mcspi *mcspi; | |
1278 | struct omap2_mcspi_dma *dma_channels; | |
ccdc7bf9 SO |
1279 | |
1280 | master = dev_get_drvdata(&pdev->dev); | |
1281 | mcspi = spi_master_get_devdata(master); | |
1282 | dma_channels = mcspi->dma_channels; | |
1283 | ||
a93a2029 | 1284 | pm_runtime_put_sync(mcspi->dev); |
751c925c | 1285 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 SO |
1286 | |
1287 | spi_unregister_master(master); | |
1288 | kfree(dma_channels); | |
1289 | ||
1290 | return 0; | |
1291 | } | |
1292 | ||
7e38c3c4 KS |
1293 | /* work with hotplug and coldplug */ |
1294 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1295 | ||
42ce7fd6 GC |
1296 | #ifdef CONFIG_SUSPEND |
1297 | /* | |
1298 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1299 | * unactive state when driver was suspend, then force it to unactive state at | |
1300 | * wake up. | |
1301 | */ | |
1302 | static int omap2_mcspi_resume(struct device *dev) | |
1303 | { | |
1304 | struct spi_master *master = dev_get_drvdata(dev); | |
1305 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1bd897f8 BC |
1306 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1307 | struct omap2_mcspi_cs *cs; | |
42ce7fd6 | 1308 | |
034d3dc9 | 1309 | pm_runtime_get_sync(mcspi->dev); |
1bd897f8 | 1310 | list_for_each_entry(cs, &ctx->cs, node) { |
42ce7fd6 | 1311 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
42ce7fd6 GC |
1312 | /* |
1313 | * We need to toggle CS state for OMAP take this | |
1314 | * change in account. | |
1315 | */ | |
af4e944d | 1316 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
42ce7fd6 | 1317 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
af4e944d | 1318 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
42ce7fd6 GC |
1319 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
1320 | } | |
1321 | } | |
034d3dc9 S |
1322 | pm_runtime_mark_last_busy(mcspi->dev); |
1323 | pm_runtime_put_autosuspend(mcspi->dev); | |
42ce7fd6 GC |
1324 | return 0; |
1325 | } | |
1326 | #else | |
1327 | #define omap2_mcspi_resume NULL | |
1328 | #endif | |
1329 | ||
1330 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1331 | .resume = omap2_mcspi_resume, | |
1f1a4384 | 1332 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1333 | }; |
1334 | ||
ccdc7bf9 SO |
1335 | static struct platform_driver omap2_mcspi_driver = { |
1336 | .driver = { | |
1337 | .name = "omap2_mcspi", | |
1338 | .owner = THIS_MODULE, | |
d5a80031 BC |
1339 | .pm = &omap2_mcspi_pm_ops, |
1340 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1341 | }, |
7d6b6d83 FB |
1342 | .probe = omap2_mcspi_probe, |
1343 | .remove = __devexit_p(omap2_mcspi_remove), | |
ccdc7bf9 SO |
1344 | }; |
1345 | ||
9fdca9df | 1346 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1347 | MODULE_LICENSE("GPL"); |