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Merge branch 'spi-linus' into spi-next
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi-omap2-mcspi.c
CommitLineData
ccdc7bf9
SO		 1/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
1a5d8190 6 * Juha Yrj�l� <juha.yrjola@nokia.com>
ccdc7bf9
SO		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/device.h>
29#include <linux/delay.h>
30#include <linux/dma-mapping.h>
53741ed8
RK		 31#include <linux/dmaengine.h>
32#include <linux/omap-dma.h>
ccdc7bf9
SO		 33#include <linux/platform_device.h>
34#include <linux/err.h>
35#include <linux/clk.h>
36#include <linux/io.h>
5a0e3ad6 37#include <linux/slab.h>
1f1a4384 38#include <linux/pm_runtime.h>
d5a80031
BC		 39#include <linux/of.h>
40#include <linux/of_device.h>
ec155afa
MP		 41#include <linux/pinctrl/consumer.h>
42#include <linux/err.h>
ccdc7bf9
SO		 43
44#include <linux/spi/spi.h>
45
2203747c 46#include <linux/platform_data/spi-omap2-mcspi.h>
ccdc7bf9
SO		 47
48#define OMAP2_MCSPI_MAX_FREQ 48000000
27b5284c 49#define SPI_AUTOSUSPEND_TIMEOUT 2000
ccdc7bf9
SO		 50
51#define OMAP2_MCSPI_REVISION 0x00
ccdc7bf9
SO		 52#define OMAP2_MCSPI_SYSSTATUS 0x14
53#define OMAP2_MCSPI_IRQSTATUS 0x18
54#define OMAP2_MCSPI_IRQENABLE 0x1c
55#define OMAP2_MCSPI_WAKEUPENABLE 0x20
56#define OMAP2_MCSPI_SYST 0x24
57#define OMAP2_MCSPI_MODULCTRL 0x28
58
59/* per-channel banks, 0x14 bytes each, first is: */
60#define OMAP2_MCSPI_CHCONF0 0x2c
61#define OMAP2_MCSPI_CHSTAT0 0x30
62#define OMAP2_MCSPI_CHCTRL0 0x34
63#define OMAP2_MCSPI_TX0 0x38
64#define OMAP2_MCSPI_RX0 0x3c
65
66/* per-register bitmasks: */
67
7a8fa725
JH		 68#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
69#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
70#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
ccdc7bf9 71
7a8fa725
JH		 72#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
73#define OMAP2_MCSPI_CHCONF_POL BIT(1)
ccdc7bf9 74#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
7a8fa725 75#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
ccdc7bf9 76#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
7a8fa725
JH		 77#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
78#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
ccdc7bf9 79#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
7a8fa725
JH		 80#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
81#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
82#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
83#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
84#define OMAP2_MCSPI_CHCONF_IS BIT(18)
85#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
86#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
ccdc7bf9 87
7a8fa725
JH		 88#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
89#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
90#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
ccdc7bf9 91
7a8fa725 92#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
ccdc7bf9 93
7a8fa725 94#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
ccdc7bf9
SO		 95
96/* We have 2 DMA channels per CS, one for RX and one for TX */
97struct omap2_mcspi_dma {
53741ed8
RK		 98 struct dma_chan *dma_tx;
99 struct dma_chan *dma_rx;
ccdc7bf9
SO		 100
101 int dma_tx_sync_dev;
102 int dma_rx_sync_dev;
103
104 struct completion dma_tx_completion;
105 struct completion dma_rx_completion;
106};
107
108/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
109 * cache operations; better heuristics consider wordsize and bitrate.
110 */
8b66c134 111#define DMA_MIN_BYTES 160
ccdc7bf9
SO		 112
113
1bd897f8
BC		 114/*
115 * Used for context save and restore, structure members to be updated whenever
116 * corresponding registers are modified.
117 */
118struct omap2_mcspi_regs {
119 u32 modulctrl;
120 u32 wakeupenable;
121 struct list_head cs;
122};
123
ccdc7bf9 124struct omap2_mcspi {
ccdc7bf9 125 struct spi_master *master;
ccdc7bf9
SO		 126 /* Virtual base address of the controller */
127 void __iomem *base;
e5480b73 128 unsigned long phys;
ccdc7bf9
SO		 129 /* SPI1 has 4 channels, while SPI2 has 2 */
130 struct omap2_mcspi_dma *dma_channels;
1bd897f8 131 struct device *dev;
1bd897f8 132 struct omap2_mcspi_regs ctx;
0384e90b 133 unsigned int pin_dir:1;
ccdc7bf9
SO		 134};
135
136struct omap2_mcspi_cs {
137 void __iomem *base;
e5480b73 138 unsigned long phys;
ccdc7bf9 139 int word_len;
89c05372 140 struct list_head node;
a41ae1ad
H		 141 /* Context save and restore shadow register */
142 u32 chconf0;
143};
144
ccdc7bf9
SO		 145static inline void mcspi_write_reg(struct spi_master *master,
146 int idx, u32 val)
147{
148 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
149
150 __raw_writel(val, mcspi->base + idx);
151}
152
153static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
154{
155 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
156
157 return __raw_readl(mcspi->base + idx);
158}
159
160static inline void mcspi_write_cs_reg(const struct spi_device *spi,
161 int idx, u32 val)
162{
163 struct omap2_mcspi_cs *cs = spi->controller_state;
164
165 __raw_writel(val, cs->base + idx);
166}
167
168static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
169{
170 struct omap2_mcspi_cs *cs = spi->controller_state;
171
172 return __raw_readl(cs->base + idx);
173}
174
a41ae1ad
H		 175static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
176{
177 struct omap2_mcspi_cs *cs = spi->controller_state;
178
179 return cs->chconf0;
180}
181
182static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
183{
184 struct omap2_mcspi_cs *cs = spi->controller_state;
185
186 cs->chconf0 = val;
187 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
a330ce20 188 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
a41ae1ad
H		 189}
190
ccdc7bf9
SO		 191static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
192 int is_read, int enable)
193{
194 u32 l, rw;
195
a41ae1ad 196 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 197
198 if (is_read) /* 1 is read, 0 write */
199 rw = OMAP2_MCSPI_CHCONF_DMAR;
200 else
201 rw = OMAP2_MCSPI_CHCONF_DMAW;
202
af4e944d
S		 203 if (enable)
204 l |= rw;
205 else
206 l &= ~rw;
207
a41ae1ad 208 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 209}
210
211static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
212{
213 u32 l;
214
215 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
216 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
4743a0f8
RT		 217 /* Flash post-writes */
218 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
ccdc7bf9
SO		 219}
220
221static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
222{
223 u32 l;
224
a41ae1ad 225 l = mcspi_cached_chconf0(spi);
af4e944d
S		 226 if (cs_active)
227 l |= OMAP2_MCSPI_CHCONF_FORCE;
228 else
229 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
230
a41ae1ad 231 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 232}
233
234static void omap2_mcspi_set_master_mode(struct spi_master *master)
235{
1bd897f8
BC		 236 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
237 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
ccdc7bf9
SO		 238 u32 l;
239
1bd897f8
BC		 240 /*
241 * Setup when switching from (reset default) slave mode
ccdc7bf9
SO		 242 * to single-channel master mode
243 */
244 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
af4e944d
S		 245 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
246 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
ccdc7bf9 247 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
a41ae1ad 248
1bd897f8 249 ctx->modulctrl = l;
a41ae1ad
H		 250}
251
252static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
253{
1bd897f8
BC		 254 struct spi_master *spi_cntrl = mcspi->master;
255 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
256 struct omap2_mcspi_cs *cs;
a41ae1ad
H		 257
258 /* McSPI: context restore */
1bd897f8
BC		 259 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
260 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
a41ae1ad 261
1bd897f8 262 list_for_each_entry(cs, &ctx->cs, node)
89c05372 263 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
a41ae1ad 264}
ccdc7bf9 265
5fda88f5
S		 266static int omap2_prepare_transfer(struct spi_master *master)
267{
268 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
269
270 pm_runtime_get_sync(mcspi->dev);
271 return 0;
272}
273
274static int omap2_unprepare_transfer(struct spi_master *master)
275{
276 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
277
278 pm_runtime_mark_last_busy(mcspi->dev);
279 pm_runtime_put_autosuspend(mcspi->dev);
280 return 0;
281}
282
2764c500
IK		 283static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
284{
285 unsigned long timeout;
286
287 timeout = jiffies + msecs_to_jiffies(1000);
288 while (!(__raw_readl(reg) & bit)) {
289 if (time_after(jiffies, timeout))
290 return -1;
291 cpu_relax();
292 }
293 return 0;
294}
295
53741ed8
RK		 296static void omap2_mcspi_rx_callback(void *data)
297{
298 struct spi_device *spi = data;
299 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
300 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
301
302 complete(&mcspi_dma->dma_rx_completion);
303
304 /* We must disable the DMA RX request */
305 omap2_mcspi_set_dma_req(spi, 1, 0);
306}
307
308static void omap2_mcspi_tx_callback(void *data)
309{
310 struct spi_device *spi = data;
311 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
312 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
313
314 complete(&mcspi_dma->dma_tx_completion);
315
316 /* We must disable the DMA TX request */
317 omap2_mcspi_set_dma_req(spi, 0, 0);
318}
319
d7b4394e
S		 320static void omap2_mcspi_tx_dma(struct spi_device *spi,
321 struct spi_transfer *xfer,
322 struct dma_slave_config cfg)
ccdc7bf9
SO		 323{
324 struct omap2_mcspi *mcspi;
ccdc7bf9 325 struct omap2_mcspi_dma *mcspi_dma;
8c7494a5 326 unsigned int count;
ccdc7bf9
SO		 327 const u8 * tx;
328
329 mcspi = spi_master_get_devdata(spi->master);
330 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
d7b4394e 331 count = xfer->len;
ccdc7bf9 332
d7b4394e 333 tx = xfer->tx_buf;
2764c500 334
d7b4394e 335 if (mcspi_dma->dma_tx) {
53741ed8
RK		 336 struct dma_async_tx_descriptor *tx;
337 struct scatterlist sg;
338
339 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
340
341 sg_init_table(&sg, 1);
342 sg_dma_address(&sg) = xfer->tx_dma;
343 sg_dma_len(&sg) = xfer->len;
344
345 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
d7b4394e 346 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
53741ed8
RK		 347 if (tx) {
348 tx->callback = omap2_mcspi_tx_callback;
349 tx->callback_param = spi;
350 dmaengine_submit(tx);
351 } else {
352 /* FIXME: fall back to PIO? */
353 }
354 }
d7b4394e
S		 355 dma_async_issue_pending(mcspi_dma->dma_tx);
356 omap2_mcspi_set_dma_req(spi, 0, 1);
357
d7b4394e 358}
53741ed8 359
d7b4394e
S		 360static unsigned
361omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
362 struct dma_slave_config cfg,
363 unsigned es)
364{
365 struct omap2_mcspi *mcspi;
366 struct omap2_mcspi_dma *mcspi_dma;
367 unsigned int count;
368 u32 l;
369 int elements = 0;
370 int word_len, element_count;
371 struct omap2_mcspi_cs *cs = spi->controller_state;
372 mcspi = spi_master_get_devdata(spi->master);
373 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
374 count = xfer->len;
375 word_len = cs->word_len;
376 l = mcspi_cached_chconf0(spi);
53741ed8 377
d7b4394e
S		 378 if (word_len <= 8)
379 element_count = count;
380 else if (word_len <= 16)
381 element_count = count >> 1;
382 else /* word_len <= 32 */
383 element_count = count >> 2;
384
385 if (mcspi_dma->dma_rx) {
53741ed8
RK		 386 struct dma_async_tx_descriptor *tx;
387 struct scatterlist sg;
388 size_t len = xfer->len - es;
389
390 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
391
392 if (l & OMAP2_MCSPI_CHCONF_TURBO)
393 len -= es;
394
395 sg_init_table(&sg, 1);
396 sg_dma_address(&sg) = xfer->rx_dma;
397 sg_dma_len(&sg) = len;
398
399 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
d7b4394e
S		 400 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
401 DMA_CTRL_ACK);
53741ed8
RK		 402 if (tx) {
403 tx->callback = omap2_mcspi_rx_callback;
404 tx->callback_param = spi;
405 dmaengine_submit(tx);
406 } else {
d7b4394e 407 /* FIXME: fall back to PIO? */
2764c500 408 }
ccdc7bf9
SO		 409 }
410
d7b4394e
S		 411 dma_async_issue_pending(mcspi_dma->dma_rx);
412 omap2_mcspi_set_dma_req(spi, 1, 1);
4743a0f8 413
d7b4394e
S		 414 wait_for_completion(&mcspi_dma->dma_rx_completion);
415 dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
416 DMA_FROM_DEVICE);
417 omap2_mcspi_set_enable(spi, 0);
53741ed8 418
d7b4394e 419 elements = element_count - 1;
4743a0f8 420
d7b4394e
S		 421 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
422 elements--;
4743a0f8 423
57c5c28d 424 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
d7b4394e 425 & OMAP2_MCSPI_CHSTAT_RXS)) {
57c5c28d
EN		 426 u32 w;
427
428 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
429 if (word_len <= 8)
d7b4394e 430 ((u8 *)xfer->rx_buf)[elements++] = w;
57c5c28d 431 else if (word_len <= 16)
d7b4394e 432 ((u16 *)xfer->rx_buf)[elements++] = w;
57c5c28d 433 else /* word_len <= 32 */
d7b4394e 434 ((u32 *)xfer->rx_buf)[elements++] = w;
57c5c28d 435 } else {
d7b4394e
S		 436 dev_err(&spi->dev, "DMA RX penultimate word empty");
437 count -= (word_len <= 8) ? 2 :
438 (word_len <= 16) ? 4 :
439 /* word_len <= 32 */ 8;
440 omap2_mcspi_set_enable(spi, 1);
441 return count;
57c5c28d 442 }
ccdc7bf9 443 }
d7b4394e
S		 444 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
445 & OMAP2_MCSPI_CHSTAT_RXS)) {
446 u32 w;
447
448 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
449 if (word_len <= 8)
450 ((u8 *)xfer->rx_buf)[elements] = w;
451 else if (word_len <= 16)
452 ((u16 *)xfer->rx_buf)[elements] = w;
453 else /* word_len <= 32 */
454 ((u32 *)xfer->rx_buf)[elements] = w;
455 } else {
456 dev_err(&spi->dev, "DMA RX last word empty");
457 count -= (word_len <= 8) ? 1 :
458 (word_len <= 16) ? 2 :
459 /* word_len <= 32 */ 4;
460 }
461 omap2_mcspi_set_enable(spi, 1);
462 return count;
463}
464
465static unsigned
466omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
467{
468 struct omap2_mcspi *mcspi;
469 struct omap2_mcspi_cs *cs = spi->controller_state;
470 struct omap2_mcspi_dma *mcspi_dma;
471 unsigned int count;
472 u32 l;
473 u8 *rx;
474 const u8 *tx;
475 struct dma_slave_config cfg;
476 enum dma_slave_buswidth width;
477 unsigned es;
e47a682a 478 void __iomem *chstat_reg;
d7b4394e
S		 479
480 mcspi = spi_master_get_devdata(spi->master);
481 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
482 l = mcspi_cached_chconf0(spi);
483
484
485 if (cs->word_len <= 8) {
486 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
487 es = 1;
488 } else if (cs->word_len <= 16) {
489 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
490 es = 2;
491 } else {
492 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
493 es = 4;
494 }
495
496 memset(&cfg, 0, sizeof(cfg));
497 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
498 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
499 cfg.src_addr_width = width;
500 cfg.dst_addr_width = width;
501 cfg.src_maxburst = 1;
502 cfg.dst_maxburst = 1;
503
504 rx = xfer->rx_buf;
505 tx = xfer->tx_buf;
506
507 count = xfer->len;
508
509 if (tx != NULL)
510 omap2_mcspi_tx_dma(spi, xfer, cfg);
511
512 if (rx != NULL)
e47a682a
S		 513 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
514
515 if (tx != NULL) {
516 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
517 wait_for_completion(&mcspi_dma->dma_tx_completion);
518 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
519 DMA_TO_DEVICE);
520
521 /* for TX_ONLY mode, be sure all words have shifted out */
522 if (rx == NULL) {
523 if (mcspi_wait_for_reg_bit(chstat_reg,
524 OMAP2_MCSPI_CHSTAT_TXS) < 0)
525 dev_err(&spi->dev, "TXS timed out\n");
526 else if (mcspi_wait_for_reg_bit(chstat_reg,
527 OMAP2_MCSPI_CHSTAT_EOT) < 0)
528 dev_err(&spi->dev, "EOT timed out\n");
529 }
530 }
ccdc7bf9
SO		 531 return count;
532}
533
ccdc7bf9
SO		 534static unsigned
535omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
536{
537 struct omap2_mcspi *mcspi;
538 struct omap2_mcspi_cs *cs = spi->controller_state;
539 unsigned int count, c;
540 u32 l;
541 void __iomem *base = cs->base;
542 void __iomem *tx_reg;
543 void __iomem *rx_reg;
544 void __iomem *chstat_reg;
545 int word_len;
546
547 mcspi = spi_master_get_devdata(spi->master);
548 count = xfer->len;
549 c = count;
550 word_len = cs->word_len;
551
a41ae1ad 552 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 553
554 /* We store the pre-calculated register addresses on stack to speed
555 * up the transfer loop. */
556 tx_reg = base + OMAP2_MCSPI_TX0;
557 rx_reg = base + OMAP2_MCSPI_RX0;
558 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
559
adef658d
MJ		 560 if (c < (word_len>>3))
561 return 0;
562
ccdc7bf9
SO		 563 if (word_len <= 8) {
564 u8 *rx;
565 const u8 *tx;
566
567 rx = xfer->rx_buf;
568 tx = xfer->tx_buf;
569
570 do {
feed9bab 571 c -= 1;
ccdc7bf9
SO		 572 if (tx != NULL) {
573 if (mcspi_wait_for_reg_bit(chstat_reg,
574 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
575 dev_err(&spi->dev, "TXS timed out\n");
576 goto out;
577 }
079a176d 578 dev_vdbg(&spi->dev, "write-%d %02x\n",
ccdc7bf9 579 word_len, *tx);
ccdc7bf9
SO		 580 __raw_writel(*tx++, tx_reg);
581 }
582 if (rx != NULL) {
583 if (mcspi_wait_for_reg_bit(chstat_reg,
584 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
585 dev_err(&spi->dev, "RXS timed out\n");
586 goto out;
587 }
4743a0f8
RT		 588
589 if (c == 1 && tx == NULL &&
590 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
591 omap2_mcspi_set_enable(spi, 0);
592 *rx++ = __raw_readl(rx_reg);
079a176d 593 dev_vdbg(&spi->dev, "read-%d %02x\n",
4743a0f8 594 word_len, *(rx - 1));
4743a0f8
RT		 595 if (mcspi_wait_for_reg_bit(chstat_reg,
596 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
597 dev_err(&spi->dev,
598 "RXS timed out\n");
599 goto out;
600 }
601 c = 0;
602 } else if (c == 0 && tx == NULL) {
603 omap2_mcspi_set_enable(spi, 0);
604 }
605
ccdc7bf9 606 *rx++ = __raw_readl(rx_reg);
079a176d 607 dev_vdbg(&spi->dev, "read-%d %02x\n",
ccdc7bf9 608 word_len, *(rx - 1));
ccdc7bf9 609 }
95c5c3ab 610 } while (c);
ccdc7bf9
SO		 611 } else if (word_len <= 16) {
612 u16 *rx;
613 const u16 *tx;
614
615 rx = xfer->rx_buf;
616 tx = xfer->tx_buf;
617 do {
feed9bab 618 c -= 2;
ccdc7bf9
SO		 619 if (tx != NULL) {
620 if (mcspi_wait_for_reg_bit(chstat_reg,
621 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
622 dev_err(&spi->dev, "TXS timed out\n");
623 goto out;
624 }
079a176d 625 dev_vdbg(&spi->dev, "write-%d %04x\n",
ccdc7bf9 626 word_len, *tx);
ccdc7bf9
SO		 627 __raw_writel(*tx++, tx_reg);
628 }
629 if (rx != NULL) {
630 if (mcspi_wait_for_reg_bit(chstat_reg,
631 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
632 dev_err(&spi->dev, "RXS timed out\n");
633 goto out;
634 }
4743a0f8
RT		 635
636 if (c == 2 && tx == NULL &&
637 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
638 omap2_mcspi_set_enable(spi, 0);
639 *rx++ = __raw_readl(rx_reg);
079a176d 640 dev_vdbg(&spi->dev, "read-%d %04x\n",
4743a0f8 641 word_len, *(rx - 1));
4743a0f8
RT		 642 if (mcspi_wait_for_reg_bit(chstat_reg,
643 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
644 dev_err(&spi->dev,
645 "RXS timed out\n");
646 goto out;
647 }
648 c = 0;
649 } else if (c == 0 && tx == NULL) {
650 omap2_mcspi_set_enable(spi, 0);
651 }
652
ccdc7bf9 653 *rx++ = __raw_readl(rx_reg);
079a176d 654 dev_vdbg(&spi->dev, "read-%d %04x\n",
ccdc7bf9 655 word_len, *(rx - 1));
ccdc7bf9 656 }
95c5c3ab 657 } while (c >= 2);
ccdc7bf9
SO		 658 } else if (word_len <= 32) {
659 u32 *rx;
660 const u32 *tx;
661
662 rx = xfer->rx_buf;
663 tx = xfer->tx_buf;
664 do {
feed9bab 665 c -= 4;
ccdc7bf9
SO		 666 if (tx != NULL) {
667 if (mcspi_wait_for_reg_bit(chstat_reg,
668 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
669 dev_err(&spi->dev, "TXS timed out\n");
670 goto out;
671 }
079a176d 672 dev_vdbg(&spi->dev, "write-%d %08x\n",
ccdc7bf9 673 word_len, *tx);
ccdc7bf9
SO		 674 __raw_writel(*tx++, tx_reg);
675 }
676 if (rx != NULL) {
677 if (mcspi_wait_for_reg_bit(chstat_reg,
678 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
679 dev_err(&spi->dev, "RXS timed out\n");
680 goto out;
681 }
4743a0f8
RT		 682
683 if (c == 4 && tx == NULL &&
684 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
685 omap2_mcspi_set_enable(spi, 0);
686 *rx++ = __raw_readl(rx_reg);
079a176d 687 dev_vdbg(&spi->dev, "read-%d %08x\n",
4743a0f8 688 word_len, *(rx - 1));
4743a0f8
RT		 689 if (mcspi_wait_for_reg_bit(chstat_reg,
690 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
691 dev_err(&spi->dev,
692 "RXS timed out\n");
693 goto out;
694 }
695 c = 0;
696 } else if (c == 0 && tx == NULL) {
697 omap2_mcspi_set_enable(spi, 0);
698 }
699
ccdc7bf9 700 *rx++ = __raw_readl(rx_reg);
079a176d 701 dev_vdbg(&spi->dev, "read-%d %08x\n",
ccdc7bf9 702 word_len, *(rx - 1));
ccdc7bf9 703 }
95c5c3ab 704 } while (c >= 4);
ccdc7bf9
SO		 705 }
706
707 /* for TX_ONLY mode, be sure all words have shifted out */
708 if (xfer->rx_buf == NULL) {
709 if (mcspi_wait_for_reg_bit(chstat_reg,
710 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
711 dev_err(&spi->dev, "TXS timed out\n");
712 } else if (mcspi_wait_for_reg_bit(chstat_reg,
713 OMAP2_MCSPI_CHSTAT_EOT) < 0)
714 dev_err(&spi->dev, "EOT timed out\n");
e1993ed6
JW		 715
716 /* disable chan to purge rx datas received in TX_ONLY transfer,
717 * otherwise these rx datas will affect the direct following
718 * RX_ONLY transfer.
719 */
720 omap2_mcspi_set_enable(spi, 0);
ccdc7bf9
SO		 721 }
722out:
4743a0f8 723 omap2_mcspi_set_enable(spi, 1);
ccdc7bf9
SO		 724 return count - c;
725}
726
57d9c10d
HH		 727static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
728{
729 u32 div;
730
731 for (div = 0; div < 15; div++)
732 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
733 return div;
734
735 return 15;
736}
737
ccdc7bf9
SO		 738/* called only when no transfer is active to this device */
739static int omap2_mcspi_setup_transfer(struct spi_device *spi,
740 struct spi_transfer *t)
741{
742 struct omap2_mcspi_cs *cs = spi->controller_state;
743 struct omap2_mcspi *mcspi;
a41ae1ad 744 struct spi_master *spi_cntrl;
ccdc7bf9
SO		 745 u32 l = 0, div = 0;
746 u8 word_len = spi->bits_per_word;
9bd4517d 747 u32 speed_hz = spi->max_speed_hz;
ccdc7bf9
SO		 748
749 mcspi = spi_master_get_devdata(spi->master);
a41ae1ad 750 spi_cntrl = mcspi->master;
ccdc7bf9
SO		 751
752 if (t != NULL && t->bits_per_word)
753 word_len = t->bits_per_word;
754
755 cs->word_len = word_len;
756
9bd4517d
SE		 757 if (t && t->speed_hz)
758 speed_hz = t->speed_hz;
759
57d9c10d
HH		 760 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
761 div = omap2_mcspi_calc_divisor(speed_hz);
ccdc7bf9 762
a41ae1ad 763 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 764
765 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
766 * REVISIT: this controller could support SPI_3WIRE mode.
767 */
0384e90b
DM		 768 if (mcspi->pin_dir == MCSPI_PINDIR_D0_OUT_D1_IN) {
769 l &= ~OMAP2_MCSPI_CHCONF_IS;
770 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
771 l |= OMAP2_MCSPI_CHCONF_DPE0;
772 } else {
773 l |= OMAP2_MCSPI_CHCONF_IS;
774 l |= OMAP2_MCSPI_CHCONF_DPE1;
775 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
776 }
ccdc7bf9
SO		 777
778 /* wordlength */
779 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
780 l |= (word_len - 1) << 7;
781
782 /* set chipselect polarity; manage with FORCE */
783 if (!(spi->mode & SPI_CS_HIGH))
784 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
785 else
786 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
787
788 /* set clock divisor */
789 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
790 l |= div << 2;
791
792 /* set SPI mode 0..3 */
793 if (spi->mode & SPI_CPOL)
794 l |= OMAP2_MCSPI_CHCONF_POL;
795 else
796 l &= ~OMAP2_MCSPI_CHCONF_POL;
797 if (spi->mode & SPI_CPHA)
798 l |= OMAP2_MCSPI_CHCONF_PHA;
799 else
800 l &= ~OMAP2_MCSPI_CHCONF_PHA;
801
a41ae1ad 802 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 803
804 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
57d9c10d 805 OMAP2_MCSPI_MAX_FREQ >> div,
ccdc7bf9
SO		 806 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
807 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
808
809 return 0;
810}
811
ccdc7bf9
SO		 812static int omap2_mcspi_request_dma(struct spi_device *spi)
813{
814 struct spi_master *master = spi->master;
815 struct omap2_mcspi *mcspi;
816 struct omap2_mcspi_dma *mcspi_dma;
53741ed8
RK		 817 dma_cap_mask_t mask;
818 unsigned sig;
ccdc7bf9
SO		 819
820 mcspi = spi_master_get_devdata(master);
821 mcspi_dma = mcspi->dma_channels + spi->chip_select;
822
53741ed8
RK		 823 init_completion(&mcspi_dma->dma_rx_completion);
824 init_completion(&mcspi_dma->dma_tx_completion);
825
826 dma_cap_zero(mask);
827 dma_cap_set(DMA_SLAVE, mask);
53741ed8
RK		 828 sig = mcspi_dma->dma_rx_sync_dev;
829 mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
830 if (!mcspi_dma->dma_rx) {
831 dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
ccdc7bf9
SO		 832 return -EAGAIN;
833 }
834
53741ed8
RK		 835 sig = mcspi_dma->dma_tx_sync_dev;
836 mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
837 if (!mcspi_dma->dma_tx) {
838 dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n");
839 dma_release_channel(mcspi_dma->dma_rx);
840 mcspi_dma->dma_rx = NULL;
ccdc7bf9
SO		 841 return -EAGAIN;
842 }
843
ccdc7bf9
SO		 844 return 0;
845}
846
ccdc7bf9
SO		 847static int omap2_mcspi_setup(struct spi_device *spi)
848{
849 int ret;
1bd897f8
BC		 850 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
851 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
ccdc7bf9
SO		 852 struct omap2_mcspi_dma *mcspi_dma;
853 struct omap2_mcspi_cs *cs = spi->controller_state;
854
7d077197 855 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
ccdc7bf9
SO		 856 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
857 spi->bits_per_word);
858 return -EINVAL;
859 }
860
ccdc7bf9
SO		 861 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
862
863 if (!cs) {
10aa5a35 864 cs = kzalloc(sizeof *cs, GFP_KERNEL);
ccdc7bf9
SO		 865 if (!cs)
866 return -ENOMEM;
867 cs->base = mcspi->base + spi->chip_select * 0x14;
e5480b73 868 cs->phys = mcspi->phys + spi->chip_select * 0x14;
a41ae1ad 869 cs->chconf0 = 0;
ccdc7bf9 870 spi->controller_state = cs;
89c05372 871 /* Link this to context save list */
1bd897f8 872 list_add_tail(&cs->node, &ctx->cs);
ccdc7bf9
SO		 873 }
874
8c7494a5 875 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
ccdc7bf9
SO		 876 ret = omap2_mcspi_request_dma(spi);
877 if (ret < 0)
878 return ret;
879 }
880
034d3dc9 881 ret = pm_runtime_get_sync(mcspi->dev);
1f1a4384
G		 882 if (ret < 0)
883 return ret;
a41ae1ad 884
86eeb6fe 885 ret = omap2_mcspi_setup_transfer(spi, NULL);
034d3dc9
S		 886 pm_runtime_mark_last_busy(mcspi->dev);
887 pm_runtime_put_autosuspend(mcspi->dev);
ccdc7bf9
SO		 888
889 return ret;
890}
891
892static void omap2_mcspi_cleanup(struct spi_device *spi)
893{
894 struct omap2_mcspi *mcspi;
895 struct omap2_mcspi_dma *mcspi_dma;
89c05372 896 struct omap2_mcspi_cs *cs;
ccdc7bf9
SO		 897
898 mcspi = spi_master_get_devdata(spi->master);
ccdc7bf9 899
5e774943
SE		 900 if (spi->controller_state) {
901 /* Unlink controller state from context save list */
902 cs = spi->controller_state;
903 list_del(&cs->node);
89c05372 904
10aa5a35 905 kfree(cs);
5e774943 906 }
ccdc7bf9 907
99f1a43f
SE		 908 if (spi->chip_select < spi->master->num_chipselect) {
909 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
910
53741ed8
RK		 911 if (mcspi_dma->dma_rx) {
912 dma_release_channel(mcspi_dma->dma_rx);
913 mcspi_dma->dma_rx = NULL;
99f1a43f 914 }
53741ed8
RK		 915 if (mcspi_dma->dma_tx) {
916 dma_release_channel(mcspi_dma->dma_tx);
917 mcspi_dma->dma_tx = NULL;
99f1a43f 918 }
ccdc7bf9
SO		 919 }
920}
921
5fda88f5 922static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
ccdc7bf9 923{
ccdc7bf9
SO		 924
925 /* We only enable one channel at a time -- the one whose message is
5fda88f5 926 * -- although this controller would gladly
ccdc7bf9
SO		 927 * arbitrate among multiple channels. This corresponds to "single
928 * channel" master mode. As a side effect, we need to manage the
929 * chipselect with the FORCE bit ... CS != channel enable.
930 */
ccdc7bf9 931
5fda88f5
S		 932 struct spi_device *spi;
933 struct spi_transfer *t = NULL;
934 int cs_active = 0;
935 struct omap2_mcspi_cs *cs;
936 struct omap2_mcspi_device_config *cd;
937 int par_override = 0;
938 int status = 0;
939 u32 chconf;
ccdc7bf9 940
5fda88f5
S		 941 spi = m->spi;
942 cs = spi->controller_state;
943 cd = spi->controller_data;
ccdc7bf9 944
5fda88f5
S		 945 omap2_mcspi_set_enable(spi, 1);
946 list_for_each_entry(t, &m->transfers, transfer_list) {
947 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
948 status = -EINVAL;
949 break;
950 }
951 if (par_override || t->speed_hz || t->bits_per_word) {
952 par_override = 1;
953 status = omap2_mcspi_setup_transfer(spi, t);
954 if (status < 0)
955 break;
956 if (!t->speed_hz && !t->bits_per_word)
957 par_override = 0;
958 }
4743a0f8 959
5fda88f5
S		 960 if (!cs_active) {
961 omap2_mcspi_force_cs(spi, 1);
962 cs_active = 1;
963 }
4743a0f8 964
5fda88f5
S		 965 chconf = mcspi_cached_chconf0(spi);
966 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
967 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
ccdc7bf9 968
5fda88f5
S		 969 if (t->tx_buf == NULL)
970 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
971 else if (t->rx_buf == NULL)
972 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
ccdc7bf9 973
5fda88f5
S		 974 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
975 /* Turbo mode is for more than one word */
976 if (t->len > ((cs->word_len + 7) >> 3))
977 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
978 }
ccdc7bf9 979
5fda88f5 980 mcspi_write_chconf0(spi, chconf);
ccdc7bf9 981
5fda88f5
S		 982 if (t->len) {
983 unsigned count;
984
985 /* RX_ONLY mode needs dummy data in TX reg */
986 if (t->tx_buf == NULL)
987 __raw_writel(0, cs->base
988 + OMAP2_MCSPI_TX0);
ccdc7bf9 989
5fda88f5
S		 990 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
991 count = omap2_mcspi_txrx_dma(spi, t);
992 else
993 count = omap2_mcspi_txrx_pio(spi, t);
994 m->actual_length += count;
ccdc7bf9 995
5fda88f5
S		 996 if (count != t->len) {
997 status = -EIO;
998 break;
ccdc7bf9
SO		 999 }
1000 }
1001
5fda88f5
S		 1002 if (t->delay_usecs)
1003 udelay(t->delay_usecs);
ccdc7bf9 1004
5fda88f5
S		 1005 /* ignore the "leave it on after last xfer" hint */
1006 if (t->cs_change) {
ccdc7bf9 1007 omap2_mcspi_force_cs(spi, 0);
5fda88f5
S		 1008 cs_active = 0;
1009 }
1010 }
1011 /* Restore defaults if they were overriden */
1012 if (par_override) {
1013 par_override = 0;
1014 status = omap2_mcspi_setup_transfer(spi, NULL);
1015 }
ccdc7bf9 1016
5fda88f5
S		 1017 if (cs_active)
1018 omap2_mcspi_force_cs(spi, 0);
ccdc7bf9 1019
5fda88f5 1020 omap2_mcspi_set_enable(spi, 0);
ccdc7bf9 1021
5fda88f5 1022 m->status = status;
1f1a4384 1023
ccdc7bf9
SO		 1024}
1025
5fda88f5
S		 1026static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1027 struct spi_message *m)
ccdc7bf9
SO		 1028{
1029 struct omap2_mcspi *mcspi;
ccdc7bf9
SO		 1030 struct spi_transfer *t;
1031
5fda88f5 1032 mcspi = spi_master_get_devdata(master);
ccdc7bf9
SO		 1033 m->actual_length = 0;
1034 m->status = 0;
1035
1036 /* reject invalid messages and transfers */
5fda88f5 1037 if (list_empty(&m->transfers))
ccdc7bf9
SO		 1038 return -EINVAL;
1039 list_for_each_entry(t, &m->transfers, transfer_list) {
1040 const void *tx_buf = t->tx_buf;
1041 void *rx_buf = t->rx_buf;
1042 unsigned len = t->len;
1043
1044 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1045 || (len && !(rx_buf || tx_buf))
1046 || (t->bits_per_word &&
1047 ( t->bits_per_word < 4
1048 || t->bits_per_word > 32))) {
5fda88f5 1049 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
ccdc7bf9
SO		 1050 t->speed_hz,
1051 len,
1052 tx_buf ? "tx" : "",
1053 rx_buf ? "rx" : "",
1054 t->bits_per_word);
1055 return -EINVAL;
1056 }
57d9c10d 1057 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
5fda88f5 1058 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
57d9c10d
HH		 1059 t->speed_hz,
1060 OMAP2_MCSPI_MAX_FREQ >> 15);
ccdc7bf9
SO		 1061 return -EINVAL;
1062 }
1063
1064 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1065 continue;
1066
ccdc7bf9 1067 if (tx_buf != NULL) {
5fda88f5 1068 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
ccdc7bf9 1069 len, DMA_TO_DEVICE);
5fda88f5
S		 1070 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1071 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
ccdc7bf9
SO		 1072 'T', len);
1073 return -EINVAL;
1074 }
1075 }
1076 if (rx_buf != NULL) {
5fda88f5 1077 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
ccdc7bf9 1078 DMA_FROM_DEVICE);
5fda88f5
S		 1079 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1080 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
ccdc7bf9
SO		 1081 'R', len);
1082 if (tx_buf != NULL)
5fda88f5 1083 dma_unmap_single(mcspi->dev, t->tx_dma,
ccdc7bf9
SO		 1084 len, DMA_TO_DEVICE);
1085 return -EINVAL;
1086 }
1087 }
1088 }
1089
5fda88f5
S		 1090 omap2_mcspi_work(mcspi, m);
1091 spi_finalize_current_message(master);
ccdc7bf9
SO		 1092 return 0;
1093}
1094
24ab3275 1095static int __devinit omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
ccdc7bf9
SO		 1096{
1097 struct spi_master *master = mcspi->master;
1bd897f8 1098 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1bd897f8 1099 int ret = 0;
ccdc7bf9 1100
034d3dc9 1101 ret = pm_runtime_get_sync(mcspi->dev);
1f1a4384
G		 1102 if (ret < 0)
1103 return ret;
ddb22195 1104
39f8052d
S		 1105 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1106 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1107 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
ccdc7bf9
SO		 1108
1109 omap2_mcspi_set_master_mode(master);
034d3dc9
S		 1110 pm_runtime_mark_last_busy(mcspi->dev);
1111 pm_runtime_put_autosuspend(mcspi->dev);
ccdc7bf9
SO		 1112 return 0;
1113}
1114
1f1a4384
G		 1115static int omap_mcspi_runtime_resume(struct device *dev)
1116{
1117 struct omap2_mcspi *mcspi;
1118 struct spi_master *master;
1119
1120 master = dev_get_drvdata(dev);
1121 mcspi = spi_master_get_devdata(master);
1122 omap2_mcspi_restore_ctx(mcspi);
1123
1124 return 0;
1125}
1126
d5a80031
BC		 1127static struct omap2_mcspi_platform_config omap2_pdata = {
1128 .regs_offset = 0,
1129};
1130
1131static struct omap2_mcspi_platform_config omap4_pdata = {
1132 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1133};
1134
1135static const struct of_device_id omap_mcspi_of_match[] = {
1136 {
1137 .compatible = "ti,omap2-mcspi",
1138 .data = &omap2_pdata,
1139 },
1140 {
1141 .compatible = "ti,omap4-mcspi",
1142 .data = &omap4_pdata,
1143 },
1144 { },
1145};
1146MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
ccc7baed 1147
7d6b6d83 1148static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
ccdc7bf9
SO		 1149{
1150 struct spi_master *master;
83a01e72 1151 const struct omap2_mcspi_platform_config *pdata;
ccdc7bf9
SO		 1152 struct omap2_mcspi *mcspi;
1153 struct resource *r;
1154 int status = 0, i;
d5a80031
BC		 1155 u32 regs_offset = 0;
1156 static int bus_num = 1;
1157 struct device_node *node = pdev->dev.of_node;
1158 const struct of_device_id *match;
ec155afa 1159 struct pinctrl *pinctrl;
ccdc7bf9
SO		 1160
1161 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1162 if (master == NULL) {
1163 dev_dbg(&pdev->dev, "master allocation failed\n");
1164 return -ENOMEM;
1165 }
1166
e7db06b5
DB		 1167 /* the spi->mode bits understood by this driver: */
1168 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1169
ccdc7bf9 1170 master->setup = omap2_mcspi_setup;
5fda88f5
S		 1171 master->prepare_transfer_hardware = omap2_prepare_transfer;
1172 master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1173 master->transfer_one_message = omap2_mcspi_transfer_one_message;
ccdc7bf9 1174 master->cleanup = omap2_mcspi_cleanup;
d5a80031
BC		 1175 master->dev.of_node = node;
1176
0384e90b
DM		 1177 dev_set_drvdata(&pdev->dev, master);
1178
1179 mcspi = spi_master_get_devdata(master);
1180 mcspi->master = master;
1181
d5a80031
BC		 1182 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1183 if (match) {
1184 u32 num_cs = 1; /* default number of chipselect */
1185 pdata = match->data;
1186
1187 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1188 master->num_chipselect = num_cs;
1189 master->bus_num = bus_num++;
0384e90b
DM		 1190 if (of_get_property(node, "ti,pindir-d0-in-d1-out", NULL))
1191 mcspi->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
d5a80031
BC		 1192 } else {
1193 pdata = pdev->dev.platform_data;
1194 master->num_chipselect = pdata->num_cs;
1195 if (pdev->id != -1)
1196 master->bus_num = pdev->id;
0384e90b 1197 mcspi->pin_dir = pdata->pin_dir;
d5a80031
BC		 1198 }
1199 regs_offset = pdata->regs_offset;
ccdc7bf9 1200
ccdc7bf9
SO		 1201 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1202 if (r == NULL) {
1203 status = -ENODEV;
39f1b565 1204 goto free_master;
ccdc7bf9 1205 }
1458d160 1206
d5a80031
BC		 1207 r->start += regs_offset;
1208 r->end += regs_offset;
1458d160 1209 mcspi->phys = r->start;
ccdc7bf9 1210
1a77b127 1211 mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
55c381e4
RK		 1212 if (!mcspi->base) {
1213 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1214 status = -ENOMEM;
1a77b127 1215 goto free_master;
55c381e4 1216 }
ccdc7bf9 1217
1f1a4384 1218 mcspi->dev = &pdev->dev;
ccdc7bf9 1219
1bd897f8 1220 INIT_LIST_HEAD(&mcspi->ctx.cs);
ccdc7bf9 1221
ccdc7bf9
SO		 1222 mcspi->dma_channels = kcalloc(master->num_chipselect,
1223 sizeof(struct omap2_mcspi_dma),
1224 GFP_KERNEL);
1225
1226 if (mcspi->dma_channels == NULL)
1a77b127 1227 goto free_master;
ccdc7bf9 1228
1a5d8190
C		 1229 for (i = 0; i < master->num_chipselect; i++) {
1230 char dma_ch_name[14];
1231 struct resource *dma_res;
1232
1233 sprintf(dma_ch_name, "rx%d", i);
1234 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1235 dma_ch_name);
1236 if (!dma_res) {
1237 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1238 status = -ENODEV;
1239 break;
1240 }
1241
1a5d8190
C		 1242 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1243 sprintf(dma_ch_name, "tx%d", i);
1244 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1245 dma_ch_name);
1246 if (!dma_res) {
1247 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1248 status = -ENODEV;
1249 break;
1250 }
1251
1a5d8190 1252 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
ccdc7bf9
SO		 1253 }
1254
39f1b565
S		 1255 if (status < 0)
1256 goto dma_chnl_free;
1257
ec155afa
MP		 1258 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1259 if (IS_ERR(pinctrl))
1260 dev_warn(&pdev->dev,
1261 "pins are not configured from the driver\n");
1262
27b5284c
S		 1263 pm_runtime_use_autosuspend(&pdev->dev);
1264 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1f1a4384
G		 1265 pm_runtime_enable(&pdev->dev);
1266
1267 if (status || omap2_mcspi_master_setup(mcspi) < 0)
39f1b565 1268 goto disable_pm;
ccdc7bf9
SO		 1269
1270 status = spi_register_master(master);
1271 if (status < 0)
37a2d84a 1272 goto disable_pm;
ccdc7bf9
SO		 1273
1274 return status;
1275
39f1b565 1276disable_pm:
751c925c 1277 pm_runtime_disable(&pdev->dev);
39f1b565 1278dma_chnl_free:
1f1a4384 1279 kfree(mcspi->dma_channels);
39f1b565 1280free_master:
37a2d84a 1281 spi_master_put(master);
ccdc7bf9
SO		 1282 return status;
1283}
1284
7d6b6d83 1285static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
ccdc7bf9
SO		 1286{
1287 struct spi_master *master;
1288 struct omap2_mcspi *mcspi;
1289 struct omap2_mcspi_dma *dma_channels;
ccdc7bf9
SO		 1290
1291 master = dev_get_drvdata(&pdev->dev);
1292 mcspi = spi_master_get_devdata(master);
1293 dma_channels = mcspi->dma_channels;
1294
a93a2029 1295 pm_runtime_put_sync(mcspi->dev);
751c925c 1296 pm_runtime_disable(&pdev->dev);
ccdc7bf9
SO		 1297
1298 spi_unregister_master(master);
1299 kfree(dma_channels);
1300
1301 return 0;
1302}
1303
7e38c3c4
KS		 1304/* work with hotplug and coldplug */
1305MODULE_ALIAS("platform:omap2_mcspi");
1306
42ce7fd6
GC		 1307#ifdef CONFIG_SUSPEND
1308/*
1309 * When SPI wake up from off-mode, CS is in activate state. If it was in
1310 * unactive state when driver was suspend, then force it to unactive state at
1311 * wake up.
1312 */
1313static int omap2_mcspi_resume(struct device *dev)
1314{
1315 struct spi_master *master = dev_get_drvdata(dev);
1316 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1bd897f8
BC		 1317 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1318 struct omap2_mcspi_cs *cs;
42ce7fd6 1319
034d3dc9 1320 pm_runtime_get_sync(mcspi->dev);
1bd897f8 1321 list_for_each_entry(cs, &ctx->cs, node) {
42ce7fd6 1322 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
42ce7fd6
GC		 1323 /*
1324 * We need to toggle CS state for OMAP take this
1325 * change in account.
1326 */
af4e944d 1327 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
42ce7fd6 1328 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
af4e944d 1329 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
42ce7fd6
GC		 1330 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1331 }
1332 }
034d3dc9
S		 1333 pm_runtime_mark_last_busy(mcspi->dev);
1334 pm_runtime_put_autosuspend(mcspi->dev);
42ce7fd6
GC		 1335 return 0;
1336}
1337#else
1338#define omap2_mcspi_resume NULL
1339#endif
1340
1341static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1342 .resume = omap2_mcspi_resume,
1f1a4384 1343 .runtime_resume = omap_mcspi_runtime_resume,
42ce7fd6
GC		 1344};
1345
ccdc7bf9
SO		 1346static struct platform_driver omap2_mcspi_driver = {
1347 .driver = {
1348 .name = "omap2_mcspi",
1349 .owner = THIS_MODULE,
d5a80031
BC		 1350 .pm = &omap2_mcspi_pm_ops,
1351 .of_match_table = omap_mcspi_of_match,
ccdc7bf9 1352 },
7d6b6d83
FB		 1353 .probe = omap2_mcspi_probe,
1354 .remove = __devexit_p(omap2_mcspi_remove),
ccdc7bf9
SO		 1355};
1356
9fdca9df 1357module_platform_driver(omap2_mcspi_driver);
ccdc7bf9 1358MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)