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spi: omap2-mcspi: Fix the redifine warning
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi-omap2-mcspi.c
CommitLineData
ccdc7bf9
SO		 1/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
1a5d8190 6 * Juha Yrj�l� <juha.yrjola@nokia.com>
ccdc7bf9
SO		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/device.h>
29#include <linux/delay.h>
30#include <linux/dma-mapping.h>
53741ed8
RK		 31#include <linux/dmaengine.h>
32#include <linux/omap-dma.h>
ccdc7bf9
SO		 33#include <linux/platform_device.h>
34#include <linux/err.h>
35#include <linux/clk.h>
36#include <linux/io.h>
5a0e3ad6 37#include <linux/slab.h>
1f1a4384 38#include <linux/pm_runtime.h>
d5a80031
BC		 39#include <linux/of.h>
40#include <linux/of_device.h>
ec155afa
MP		 41#include <linux/pinctrl/consumer.h>
42#include <linux/err.h>
ccdc7bf9
SO		 43
44#include <linux/spi/spi.h>
45
2203747c 46#include <linux/platform_data/spi-omap2-mcspi.h>
ccdc7bf9
SO		 47
48#define OMAP2_MCSPI_MAX_FREQ 48000000
27b5284c 49#define SPI_AUTOSUSPEND_TIMEOUT 2000
ccdc7bf9
SO		 50
51#define OMAP2_MCSPI_REVISION 0x00
ccdc7bf9
SO		 52#define OMAP2_MCSPI_SYSSTATUS 0x14
53#define OMAP2_MCSPI_IRQSTATUS 0x18
54#define OMAP2_MCSPI_IRQENABLE 0x1c
55#define OMAP2_MCSPI_WAKEUPENABLE 0x20
56#define OMAP2_MCSPI_SYST 0x24
57#define OMAP2_MCSPI_MODULCTRL 0x28
58
59/* per-channel banks, 0x14 bytes each, first is: */
60#define OMAP2_MCSPI_CHCONF0 0x2c
61#define OMAP2_MCSPI_CHSTAT0 0x30
62#define OMAP2_MCSPI_CHCTRL0 0x34
63#define OMAP2_MCSPI_TX0 0x38
64#define OMAP2_MCSPI_RX0 0x3c
65
66/* per-register bitmasks: */
67
7a8fa725
JH		 68#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
69#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
70#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
ccdc7bf9 71
7a8fa725
JH		 72#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
73#define OMAP2_MCSPI_CHCONF_POL BIT(1)
ccdc7bf9 74#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
7a8fa725 75#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
ccdc7bf9 76#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
7a8fa725
JH		 77#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
78#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
ccdc7bf9 79#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
7a8fa725
JH		 80#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
81#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
82#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
83#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
84#define OMAP2_MCSPI_CHCONF_IS BIT(18)
85#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
86#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
ccdc7bf9 87
7a8fa725
JH		 88#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
89#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
90#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
ccdc7bf9 91
7a8fa725 92#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
ccdc7bf9 93
7a8fa725 94#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
ccdc7bf9
SO		 95
96/* We have 2 DMA channels per CS, one for RX and one for TX */
97struct omap2_mcspi_dma {
53741ed8
RK		 98 struct dma_chan *dma_tx;
99 struct dma_chan *dma_rx;
ccdc7bf9
SO		 100
101 int dma_tx_sync_dev;
102 int dma_rx_sync_dev;
103
104 struct completion dma_tx_completion;
105 struct completion dma_rx_completion;
106};
107
108/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
109 * cache operations; better heuristics consider wordsize and bitrate.
110 */
8b66c134 111#define DMA_MIN_BYTES 160
ccdc7bf9
SO		 112
113
1bd897f8
BC		 114/*
115 * Used for context save and restore, structure members to be updated whenever
116 * corresponding registers are modified.
117 */
118struct omap2_mcspi_regs {
119 u32 modulctrl;
120 u32 wakeupenable;
121 struct list_head cs;
122};
123
ccdc7bf9 124struct omap2_mcspi {
ccdc7bf9 125 struct spi_master *master;
ccdc7bf9
SO		 126 /* Virtual base address of the controller */
127 void __iomem *base;
e5480b73 128 unsigned long phys;
ccdc7bf9
SO		 129 /* SPI1 has 4 channels, while SPI2 has 2 */
130 struct omap2_mcspi_dma *dma_channels;
1bd897f8 131 struct device *dev;
1bd897f8 132 struct omap2_mcspi_regs ctx;
0384e90b 133 unsigned int pin_dir:1;
ccdc7bf9
SO		 134};
135
136struct omap2_mcspi_cs {
137 void __iomem *base;
e5480b73 138 unsigned long phys;
ccdc7bf9 139 int word_len;
89c05372 140 struct list_head node;
a41ae1ad
H		 141 /* Context save and restore shadow register */
142 u32 chconf0;
143};
144
ccdc7bf9
SO		 145static inline void mcspi_write_reg(struct spi_master *master,
146 int idx, u32 val)
147{
148 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
149
150 __raw_writel(val, mcspi->base + idx);
151}
152
153static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
154{
155 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
156
157 return __raw_readl(mcspi->base + idx);
158}
159
160static inline void mcspi_write_cs_reg(const struct spi_device *spi,
161 int idx, u32 val)
162{
163 struct omap2_mcspi_cs *cs = spi->controller_state;
164
165 __raw_writel(val, cs->base + idx);
166}
167
168static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
169{
170 struct omap2_mcspi_cs *cs = spi->controller_state;
171
172 return __raw_readl(cs->base + idx);
173}
174
a41ae1ad
H		 175static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
176{
177 struct omap2_mcspi_cs *cs = spi->controller_state;
178
179 return cs->chconf0;
180}
181
182static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
183{
184 struct omap2_mcspi_cs *cs = spi->controller_state;
185
186 cs->chconf0 = val;
187 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
a330ce20 188 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
a41ae1ad
H		 189}
190
ccdc7bf9
SO		 191static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
192 int is_read, int enable)
193{
194 u32 l, rw;
195
a41ae1ad 196 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 197
198 if (is_read) /* 1 is read, 0 write */
199 rw = OMAP2_MCSPI_CHCONF_DMAR;
200 else
201 rw = OMAP2_MCSPI_CHCONF_DMAW;
202
af4e944d
S		 203 if (enable)
204 l |= rw;
205 else
206 l &= ~rw;
207
a41ae1ad 208 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 209}
210
211static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
212{
213 u32 l;
214
215 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
216 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
4743a0f8
RT		 217 /* Flash post-writes */
218 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
ccdc7bf9
SO		 219}
220
221static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
222{
223 u32 l;
224
a41ae1ad 225 l = mcspi_cached_chconf0(spi);
af4e944d
S		 226 if (cs_active)
227 l |= OMAP2_MCSPI_CHCONF_FORCE;
228 else
229 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
230
a41ae1ad 231 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 232}
233
234static void omap2_mcspi_set_master_mode(struct spi_master *master)
235{
1bd897f8
BC		 236 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
237 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
ccdc7bf9
SO		 238 u32 l;
239
1bd897f8
BC		 240 /*
241 * Setup when switching from (reset default) slave mode
ccdc7bf9
SO		 242 * to single-channel master mode
243 */
244 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
af4e944d
S		 245 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
246 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
ccdc7bf9 247 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
a41ae1ad 248
1bd897f8 249 ctx->modulctrl = l;
a41ae1ad
H		 250}
251
252static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
253{
1bd897f8
BC		 254 struct spi_master *spi_cntrl = mcspi->master;
255 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
256 struct omap2_mcspi_cs *cs;
a41ae1ad
H		 257
258 /* McSPI: context restore */
1bd897f8
BC		 259 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
260 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
a41ae1ad 261
1bd897f8 262 list_for_each_entry(cs, &ctx->cs, node)
89c05372 263 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
a41ae1ad 264}
ccdc7bf9 265
5fda88f5
S		 266static int omap2_prepare_transfer(struct spi_master *master)
267{
268 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
269
270 pm_runtime_get_sync(mcspi->dev);
271 return 0;
272}
273
274static int omap2_unprepare_transfer(struct spi_master *master)
275{
276 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
277
278 pm_runtime_mark_last_busy(mcspi->dev);
279 pm_runtime_put_autosuspend(mcspi->dev);
280 return 0;
281}
282
2764c500
IK		 283static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
284{
285 unsigned long timeout;
286
287 timeout = jiffies + msecs_to_jiffies(1000);
288 while (!(__raw_readl(reg) & bit)) {
289 if (time_after(jiffies, timeout))
290 return -1;
291 cpu_relax();
292 }
293 return 0;
294}
295
53741ed8
RK		 296static void omap2_mcspi_rx_callback(void *data)
297{
298 struct spi_device *spi = data;
299 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
300 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
301
302 complete(&mcspi_dma->dma_rx_completion);
303
304 /* We must disable the DMA RX request */
305 omap2_mcspi_set_dma_req(spi, 1, 0);
306}
307
308static void omap2_mcspi_tx_callback(void *data)
309{
310 struct spi_device *spi = data;
311 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
312 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
313
314 complete(&mcspi_dma->dma_tx_completion);
315
316 /* We must disable the DMA TX request */
317 omap2_mcspi_set_dma_req(spi, 0, 0);
318}
319
d7b4394e
S		 320static void omap2_mcspi_tx_dma(struct spi_device *spi,
321 struct spi_transfer *xfer,
322 struct dma_slave_config cfg)
ccdc7bf9
SO		 323{
324 struct omap2_mcspi *mcspi;
ccdc7bf9 325 struct omap2_mcspi_dma *mcspi_dma;
8c7494a5 326 unsigned int count;
ccdc7bf9
SO		 327
328 mcspi = spi_master_get_devdata(spi->master);
329 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
d7b4394e 330 count = xfer->len;
ccdc7bf9 331
d7b4394e 332 if (mcspi_dma->dma_tx) {
53741ed8
RK		 333 struct dma_async_tx_descriptor *tx;
334 struct scatterlist sg;
335
336 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
337
338 sg_init_table(&sg, 1);
339 sg_dma_address(&sg) = xfer->tx_dma;
340 sg_dma_len(&sg) = xfer->len;
341
342 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
d7b4394e 343 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
53741ed8
RK		 344 if (tx) {
345 tx->callback = omap2_mcspi_tx_callback;
346 tx->callback_param = spi;
347 dmaengine_submit(tx);
348 } else {
349 /* FIXME: fall back to PIO? */
350 }
351 }
d7b4394e
S		 352 dma_async_issue_pending(mcspi_dma->dma_tx);
353 omap2_mcspi_set_dma_req(spi, 0, 1);
354
d7b4394e 355}
53741ed8 356
d7b4394e
S		 357static unsigned
358omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
359 struct dma_slave_config cfg,
360 unsigned es)
361{
362 struct omap2_mcspi *mcspi;
363 struct omap2_mcspi_dma *mcspi_dma;
364 unsigned int count;
365 u32 l;
366 int elements = 0;
367 int word_len, element_count;
368 struct omap2_mcspi_cs *cs = spi->controller_state;
369 mcspi = spi_master_get_devdata(spi->master);
370 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
371 count = xfer->len;
372 word_len = cs->word_len;
373 l = mcspi_cached_chconf0(spi);
53741ed8 374
d7b4394e
S		 375 if (word_len <= 8)
376 element_count = count;
377 else if (word_len <= 16)
378 element_count = count >> 1;
379 else /* word_len <= 32 */
380 element_count = count >> 2;
381
382 if (mcspi_dma->dma_rx) {
53741ed8
RK		 383 struct dma_async_tx_descriptor *tx;
384 struct scatterlist sg;
385 size_t len = xfer->len - es;
386
387 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
388
389 if (l & OMAP2_MCSPI_CHCONF_TURBO)
390 len -= es;
391
392 sg_init_table(&sg, 1);
393 sg_dma_address(&sg) = xfer->rx_dma;
394 sg_dma_len(&sg) = len;
395
396 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
d7b4394e
S		 397 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
398 DMA_CTRL_ACK);
53741ed8
RK		 399 if (tx) {
400 tx->callback = omap2_mcspi_rx_callback;
401 tx->callback_param = spi;
402 dmaengine_submit(tx);
403 } else {
d7b4394e 404 /* FIXME: fall back to PIO? */
2764c500 405 }
ccdc7bf9
SO		 406 }
407
d7b4394e
S		 408 dma_async_issue_pending(mcspi_dma->dma_rx);
409 omap2_mcspi_set_dma_req(spi, 1, 1);
4743a0f8 410
d7b4394e
S		 411 wait_for_completion(&mcspi_dma->dma_rx_completion);
412 dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
413 DMA_FROM_DEVICE);
414 omap2_mcspi_set_enable(spi, 0);
53741ed8 415
d7b4394e 416 elements = element_count - 1;
4743a0f8 417
d7b4394e
S		 418 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
419 elements--;
4743a0f8 420
57c5c28d 421 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
d7b4394e 422 & OMAP2_MCSPI_CHSTAT_RXS)) {
57c5c28d
EN		 423 u32 w;
424
425 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
426 if (word_len <= 8)
d7b4394e 427 ((u8 *)xfer->rx_buf)[elements++] = w;
57c5c28d 428 else if (word_len <= 16)
d7b4394e 429 ((u16 *)xfer->rx_buf)[elements++] = w;
57c5c28d 430 else /* word_len <= 32 */
d7b4394e 431 ((u32 *)xfer->rx_buf)[elements++] = w;
57c5c28d 432 } else {
d7b4394e
S		 433 dev_err(&spi->dev, "DMA RX penultimate word empty");
434 count -= (word_len <= 8) ? 2 :
435 (word_len <= 16) ? 4 :
436 /* word_len <= 32 */ 8;
437 omap2_mcspi_set_enable(spi, 1);
438 return count;
57c5c28d 439 }
ccdc7bf9 440 }
d7b4394e
S		 441 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
442 & OMAP2_MCSPI_CHSTAT_RXS)) {
443 u32 w;
444
445 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
446 if (word_len <= 8)
447 ((u8 *)xfer->rx_buf)[elements] = w;
448 else if (word_len <= 16)
449 ((u16 *)xfer->rx_buf)[elements] = w;
450 else /* word_len <= 32 */
451 ((u32 *)xfer->rx_buf)[elements] = w;
452 } else {
453 dev_err(&spi->dev, "DMA RX last word empty");
454 count -= (word_len <= 8) ? 1 :
455 (word_len <= 16) ? 2 :
456 /* word_len <= 32 */ 4;
457 }
458 omap2_mcspi_set_enable(spi, 1);
459 return count;
460}
461
462static unsigned
463omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
464{
465 struct omap2_mcspi *mcspi;
466 struct omap2_mcspi_cs *cs = spi->controller_state;
467 struct omap2_mcspi_dma *mcspi_dma;
468 unsigned int count;
469 u32 l;
470 u8 *rx;
471 const u8 *tx;
472 struct dma_slave_config cfg;
473 enum dma_slave_buswidth width;
474 unsigned es;
e47a682a 475 void __iomem *chstat_reg;
d7b4394e
S		 476
477 mcspi = spi_master_get_devdata(spi->master);
478 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
479 l = mcspi_cached_chconf0(spi);
480
481
482 if (cs->word_len <= 8) {
483 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
484 es = 1;
485 } else if (cs->word_len <= 16) {
486 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
487 es = 2;
488 } else {
489 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
490 es = 4;
491 }
492
493 memset(&cfg, 0, sizeof(cfg));
494 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
495 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
496 cfg.src_addr_width = width;
497 cfg.dst_addr_width = width;
498 cfg.src_maxburst = 1;
499 cfg.dst_maxburst = 1;
500
501 rx = xfer->rx_buf;
502 tx = xfer->tx_buf;
503
504 count = xfer->len;
505
506 if (tx != NULL)
507 omap2_mcspi_tx_dma(spi, xfer, cfg);
508
509 if (rx != NULL)
e47a682a
S		 510 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
511
512 if (tx != NULL) {
513 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
514 wait_for_completion(&mcspi_dma->dma_tx_completion);
515 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
516 DMA_TO_DEVICE);
517
518 /* for TX_ONLY mode, be sure all words have shifted out */
519 if (rx == NULL) {
520 if (mcspi_wait_for_reg_bit(chstat_reg,
521 OMAP2_MCSPI_CHSTAT_TXS) < 0)
522 dev_err(&spi->dev, "TXS timed out\n");
523 else if (mcspi_wait_for_reg_bit(chstat_reg,
524 OMAP2_MCSPI_CHSTAT_EOT) < 0)
525 dev_err(&spi->dev, "EOT timed out\n");
526 }
527 }
ccdc7bf9
SO		 528 return count;
529}
530
ccdc7bf9
SO		 531static unsigned
532omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
533{
534 struct omap2_mcspi *mcspi;
535 struct omap2_mcspi_cs *cs = spi->controller_state;
536 unsigned int count, c;
537 u32 l;
538 void __iomem *base = cs->base;
539 void __iomem *tx_reg;
540 void __iomem *rx_reg;
541 void __iomem *chstat_reg;
542 int word_len;
543
544 mcspi = spi_master_get_devdata(spi->master);
545 count = xfer->len;
546 c = count;
547 word_len = cs->word_len;
548
a41ae1ad 549 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 550
551 /* We store the pre-calculated register addresses on stack to speed
552 * up the transfer loop. */
553 tx_reg = base + OMAP2_MCSPI_TX0;
554 rx_reg = base + OMAP2_MCSPI_RX0;
555 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
556
adef658d
MJ		 557 if (c < (word_len>>3))
558 return 0;
559
ccdc7bf9
SO		 560 if (word_len <= 8) {
561 u8 *rx;
562 const u8 *tx;
563
564 rx = xfer->rx_buf;
565 tx = xfer->tx_buf;
566
567 do {
feed9bab 568 c -= 1;
ccdc7bf9
SO		 569 if (tx != NULL) {
570 if (mcspi_wait_for_reg_bit(chstat_reg,
571 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
572 dev_err(&spi->dev, "TXS timed out\n");
573 goto out;
574 }
079a176d 575 dev_vdbg(&spi->dev, "write-%d %02x\n",
ccdc7bf9 576 word_len, *tx);
ccdc7bf9
SO		 577 __raw_writel(*tx++, tx_reg);
578 }
579 if (rx != NULL) {
580 if (mcspi_wait_for_reg_bit(chstat_reg,
581 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
582 dev_err(&spi->dev, "RXS timed out\n");
583 goto out;
584 }
4743a0f8
RT		 585
586 if (c == 1 && tx == NULL &&
587 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
588 omap2_mcspi_set_enable(spi, 0);
589 *rx++ = __raw_readl(rx_reg);
079a176d 590 dev_vdbg(&spi->dev, "read-%d %02x\n",
4743a0f8 591 word_len, *(rx - 1));
4743a0f8
RT		 592 if (mcspi_wait_for_reg_bit(chstat_reg,
593 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
594 dev_err(&spi->dev,
595 "RXS timed out\n");
596 goto out;
597 }
598 c = 0;
599 } else if (c == 0 && tx == NULL) {
600 omap2_mcspi_set_enable(spi, 0);
601 }
602
ccdc7bf9 603 *rx++ = __raw_readl(rx_reg);
079a176d 604 dev_vdbg(&spi->dev, "read-%d %02x\n",
ccdc7bf9 605 word_len, *(rx - 1));
ccdc7bf9 606 }
95c5c3ab 607 } while (c);
ccdc7bf9
SO		 608 } else if (word_len <= 16) {
609 u16 *rx;
610 const u16 *tx;
611
612 rx = xfer->rx_buf;
613 tx = xfer->tx_buf;
614 do {
feed9bab 615 c -= 2;
ccdc7bf9
SO		 616 if (tx != NULL) {
617 if (mcspi_wait_for_reg_bit(chstat_reg,
618 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
619 dev_err(&spi->dev, "TXS timed out\n");
620 goto out;
621 }
079a176d 622 dev_vdbg(&spi->dev, "write-%d %04x\n",
ccdc7bf9 623 word_len, *tx);
ccdc7bf9
SO		 624 __raw_writel(*tx++, tx_reg);
625 }
626 if (rx != NULL) {
627 if (mcspi_wait_for_reg_bit(chstat_reg,
628 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
629 dev_err(&spi->dev, "RXS timed out\n");
630 goto out;
631 }
4743a0f8
RT		 632
633 if (c == 2 && tx == NULL &&
634 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
635 omap2_mcspi_set_enable(spi, 0);
636 *rx++ = __raw_readl(rx_reg);
079a176d 637 dev_vdbg(&spi->dev, "read-%d %04x\n",
4743a0f8 638 word_len, *(rx - 1));
4743a0f8
RT		 639 if (mcspi_wait_for_reg_bit(chstat_reg,
640 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
641 dev_err(&spi->dev,
642 "RXS timed out\n");
643 goto out;
644 }
645 c = 0;
646 } else if (c == 0 && tx == NULL) {
647 omap2_mcspi_set_enable(spi, 0);
648 }
649
ccdc7bf9 650 *rx++ = __raw_readl(rx_reg);
079a176d 651 dev_vdbg(&spi->dev, "read-%d %04x\n",
ccdc7bf9 652 word_len, *(rx - 1));
ccdc7bf9 653 }
95c5c3ab 654 } while (c >= 2);
ccdc7bf9
SO		 655 } else if (word_len <= 32) {
656 u32 *rx;
657 const u32 *tx;
658
659 rx = xfer->rx_buf;
660 tx = xfer->tx_buf;
661 do {
feed9bab 662 c -= 4;
ccdc7bf9
SO		 663 if (tx != NULL) {
664 if (mcspi_wait_for_reg_bit(chstat_reg,
665 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
666 dev_err(&spi->dev, "TXS timed out\n");
667 goto out;
668 }
079a176d 669 dev_vdbg(&spi->dev, "write-%d %08x\n",
ccdc7bf9 670 word_len, *tx);
ccdc7bf9
SO		 671 __raw_writel(*tx++, tx_reg);
672 }
673 if (rx != NULL) {
674 if (mcspi_wait_for_reg_bit(chstat_reg,
675 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
676 dev_err(&spi->dev, "RXS timed out\n");
677 goto out;
678 }
4743a0f8
RT		 679
680 if (c == 4 && tx == NULL &&
681 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
682 omap2_mcspi_set_enable(spi, 0);
683 *rx++ = __raw_readl(rx_reg);
079a176d 684 dev_vdbg(&spi->dev, "read-%d %08x\n",
4743a0f8 685 word_len, *(rx - 1));
4743a0f8
RT		 686 if (mcspi_wait_for_reg_bit(chstat_reg,
687 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
688 dev_err(&spi->dev,
689 "RXS timed out\n");
690 goto out;
691 }
692 c = 0;
693 } else if (c == 0 && tx == NULL) {
694 omap2_mcspi_set_enable(spi, 0);
695 }
696
ccdc7bf9 697 *rx++ = __raw_readl(rx_reg);
079a176d 698 dev_vdbg(&spi->dev, "read-%d %08x\n",
ccdc7bf9 699 word_len, *(rx - 1));
ccdc7bf9 700 }
95c5c3ab 701 } while (c >= 4);
ccdc7bf9
SO		 702 }
703
704 /* for TX_ONLY mode, be sure all words have shifted out */
705 if (xfer->rx_buf == NULL) {
706 if (mcspi_wait_for_reg_bit(chstat_reg,
707 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
708 dev_err(&spi->dev, "TXS timed out\n");
709 } else if (mcspi_wait_for_reg_bit(chstat_reg,
710 OMAP2_MCSPI_CHSTAT_EOT) < 0)
711 dev_err(&spi->dev, "EOT timed out\n");
e1993ed6
JW		 712
713 /* disable chan to purge rx datas received in TX_ONLY transfer,
714 * otherwise these rx datas will affect the direct following
715 * RX_ONLY transfer.
716 */
717 omap2_mcspi_set_enable(spi, 0);
ccdc7bf9
SO		 718 }
719out:
4743a0f8 720 omap2_mcspi_set_enable(spi, 1);
ccdc7bf9
SO		 721 return count - c;
722}
723
57d9c10d
HH		 724static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
725{
726 u32 div;
727
728 for (div = 0; div < 15; div++)
729 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
730 return div;
731
732 return 15;
733}
734
ccdc7bf9
SO		 735/* called only when no transfer is active to this device */
736static int omap2_mcspi_setup_transfer(struct spi_device *spi,
737 struct spi_transfer *t)
738{
739 struct omap2_mcspi_cs *cs = spi->controller_state;
740 struct omap2_mcspi *mcspi;
a41ae1ad 741 struct spi_master *spi_cntrl;
ccdc7bf9
SO		 742 u32 l = 0, div = 0;
743 u8 word_len = spi->bits_per_word;
9bd4517d 744 u32 speed_hz = spi->max_speed_hz;
ccdc7bf9
SO		 745
746 mcspi = spi_master_get_devdata(spi->master);
a41ae1ad 747 spi_cntrl = mcspi->master;
ccdc7bf9
SO		 748
749 if (t != NULL && t->bits_per_word)
750 word_len = t->bits_per_word;
751
752 cs->word_len = word_len;
753
9bd4517d
SE		 754 if (t && t->speed_hz)
755 speed_hz = t->speed_hz;
756
57d9c10d
HH		 757 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
758 div = omap2_mcspi_calc_divisor(speed_hz);
ccdc7bf9 759
a41ae1ad 760 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 761
762 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
763 * REVISIT: this controller could support SPI_3WIRE mode.
764 */
2cd45179 765 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
0384e90b
DM		 766 l &= ~OMAP2_MCSPI_CHCONF_IS;
767 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
768 l |= OMAP2_MCSPI_CHCONF_DPE0;
769 } else {
770 l |= OMAP2_MCSPI_CHCONF_IS;
771 l |= OMAP2_MCSPI_CHCONF_DPE1;
772 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
773 }
ccdc7bf9
SO		 774
775 /* wordlength */
776 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
777 l |= (word_len - 1) << 7;
778
779 /* set chipselect polarity; manage with FORCE */
780 if (!(spi->mode & SPI_CS_HIGH))
781 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
782 else
783 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
784
785 /* set clock divisor */
786 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
787 l |= div << 2;
788
789 /* set SPI mode 0..3 */
790 if (spi->mode & SPI_CPOL)
791 l |= OMAP2_MCSPI_CHCONF_POL;
792 else
793 l &= ~OMAP2_MCSPI_CHCONF_POL;
794 if (spi->mode & SPI_CPHA)
795 l |= OMAP2_MCSPI_CHCONF_PHA;
796 else
797 l &= ~OMAP2_MCSPI_CHCONF_PHA;
798
a41ae1ad 799 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 800
801 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
57d9c10d 802 OMAP2_MCSPI_MAX_FREQ >> div,
ccdc7bf9
SO		 803 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
804 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
805
806 return 0;
807}
808
ccdc7bf9
SO		 809static int omap2_mcspi_request_dma(struct spi_device *spi)
810{
811 struct spi_master *master = spi->master;
812 struct omap2_mcspi *mcspi;
813 struct omap2_mcspi_dma *mcspi_dma;
53741ed8
RK		 814 dma_cap_mask_t mask;
815 unsigned sig;
ccdc7bf9
SO		 816
817 mcspi = spi_master_get_devdata(master);
818 mcspi_dma = mcspi->dma_channels + spi->chip_select;
819
53741ed8
RK		 820 init_completion(&mcspi_dma->dma_rx_completion);
821 init_completion(&mcspi_dma->dma_tx_completion);
822
823 dma_cap_zero(mask);
824 dma_cap_set(DMA_SLAVE, mask);
53741ed8
RK		 825 sig = mcspi_dma->dma_rx_sync_dev;
826 mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
827 if (!mcspi_dma->dma_rx) {
828 dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
ccdc7bf9
SO		 829 return -EAGAIN;
830 }
831
53741ed8
RK		 832 sig = mcspi_dma->dma_tx_sync_dev;
833 mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
834 if (!mcspi_dma->dma_tx) {
835 dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n");
836 dma_release_channel(mcspi_dma->dma_rx);
837 mcspi_dma->dma_rx = NULL;
ccdc7bf9
SO		 838 return -EAGAIN;
839 }
840
ccdc7bf9
SO		 841 return 0;
842}
843
ccdc7bf9
SO		 844static int omap2_mcspi_setup(struct spi_device *spi)
845{
846 int ret;
1bd897f8
BC		 847 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
848 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
ccdc7bf9
SO		 849 struct omap2_mcspi_dma *mcspi_dma;
850 struct omap2_mcspi_cs *cs = spi->controller_state;
851
7d077197 852 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
ccdc7bf9
SO		 853 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
854 spi->bits_per_word);
855 return -EINVAL;
856 }
857
ccdc7bf9
SO		 858 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
859
860 if (!cs) {
10aa5a35 861 cs = kzalloc(sizeof *cs, GFP_KERNEL);
ccdc7bf9
SO		 862 if (!cs)
863 return -ENOMEM;
864 cs->base = mcspi->base + spi->chip_select * 0x14;
e5480b73 865 cs->phys = mcspi->phys + spi->chip_select * 0x14;
a41ae1ad 866 cs->chconf0 = 0;
ccdc7bf9 867 spi->controller_state = cs;
89c05372 868 /* Link this to context save list */
1bd897f8 869 list_add_tail(&cs->node, &ctx->cs);
ccdc7bf9
SO		 870 }
871
8c7494a5 872 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
ccdc7bf9
SO		 873 ret = omap2_mcspi_request_dma(spi);
874 if (ret < 0)
875 return ret;
876 }
877
034d3dc9 878 ret = pm_runtime_get_sync(mcspi->dev);
1f1a4384
G		 879 if (ret < 0)
880 return ret;
a41ae1ad 881
86eeb6fe 882 ret = omap2_mcspi_setup_transfer(spi, NULL);
034d3dc9
S		 883 pm_runtime_mark_last_busy(mcspi->dev);
884 pm_runtime_put_autosuspend(mcspi->dev);
ccdc7bf9
SO		 885
886 return ret;
887}
888
889static void omap2_mcspi_cleanup(struct spi_device *spi)
890{
891 struct omap2_mcspi *mcspi;
892 struct omap2_mcspi_dma *mcspi_dma;
89c05372 893 struct omap2_mcspi_cs *cs;
ccdc7bf9
SO		 894
895 mcspi = spi_master_get_devdata(spi->master);
ccdc7bf9 896
5e774943
SE		 897 if (spi->controller_state) {
898 /* Unlink controller state from context save list */
899 cs = spi->controller_state;
900 list_del(&cs->node);
89c05372 901
10aa5a35 902 kfree(cs);
5e774943 903 }
ccdc7bf9 904
99f1a43f
SE		 905 if (spi->chip_select < spi->master->num_chipselect) {
906 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
907
53741ed8
RK		 908 if (mcspi_dma->dma_rx) {
909 dma_release_channel(mcspi_dma->dma_rx);
910 mcspi_dma->dma_rx = NULL;
99f1a43f 911 }
53741ed8
RK		 912 if (mcspi_dma->dma_tx) {
913 dma_release_channel(mcspi_dma->dma_tx);
914 mcspi_dma->dma_tx = NULL;
99f1a43f 915 }
ccdc7bf9
SO		 916 }
917}
918
5fda88f5 919static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
ccdc7bf9 920{
ccdc7bf9
SO		 921
922 /* We only enable one channel at a time -- the one whose message is
5fda88f5 923 * -- although this controller would gladly
ccdc7bf9
SO		 924 * arbitrate among multiple channels. This corresponds to "single
925 * channel" master mode. As a side effect, we need to manage the
926 * chipselect with the FORCE bit ... CS != channel enable.
927 */
ccdc7bf9 928
5fda88f5
S		 929 struct spi_device *spi;
930 struct spi_transfer *t = NULL;
931 int cs_active = 0;
932 struct omap2_mcspi_cs *cs;
933 struct omap2_mcspi_device_config *cd;
934 int par_override = 0;
935 int status = 0;
936 u32 chconf;
ccdc7bf9 937
5fda88f5
S		 938 spi = m->spi;
939 cs = spi->controller_state;
940 cd = spi->controller_data;
ccdc7bf9 941
5fda88f5
S		 942 omap2_mcspi_set_enable(spi, 1);
943 list_for_each_entry(t, &m->transfers, transfer_list) {
944 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
945 status = -EINVAL;
946 break;
947 }
948 if (par_override || t->speed_hz || t->bits_per_word) {
949 par_override = 1;
950 status = omap2_mcspi_setup_transfer(spi, t);
951 if (status < 0)
952 break;
953 if (!t->speed_hz && !t->bits_per_word)
954 par_override = 0;
955 }
4743a0f8 956
5fda88f5
S		 957 if (!cs_active) {
958 omap2_mcspi_force_cs(spi, 1);
959 cs_active = 1;
960 }
4743a0f8 961
5fda88f5
S		 962 chconf = mcspi_cached_chconf0(spi);
963 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
964 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
ccdc7bf9 965
5fda88f5
S		 966 if (t->tx_buf == NULL)
967 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
968 else if (t->rx_buf == NULL)
969 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
ccdc7bf9 970
5fda88f5
S		 971 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
972 /* Turbo mode is for more than one word */
973 if (t->len > ((cs->word_len + 7) >> 3))
974 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
975 }
ccdc7bf9 976
5fda88f5 977 mcspi_write_chconf0(spi, chconf);
ccdc7bf9 978
5fda88f5
S		 979 if (t->len) {
980 unsigned count;
981
982 /* RX_ONLY mode needs dummy data in TX reg */
983 if (t->tx_buf == NULL)
984 __raw_writel(0, cs->base
985 + OMAP2_MCSPI_TX0);
ccdc7bf9 986
5fda88f5
S		 987 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
988 count = omap2_mcspi_txrx_dma(spi, t);
989 else
990 count = omap2_mcspi_txrx_pio(spi, t);
991 m->actual_length += count;
ccdc7bf9 992
5fda88f5
S		 993 if (count != t->len) {
994 status = -EIO;
995 break;
ccdc7bf9
SO		 996 }
997 }
998
5fda88f5
S		 999 if (t->delay_usecs)
1000 udelay(t->delay_usecs);
ccdc7bf9 1001
5fda88f5
S		 1002 /* ignore the "leave it on after last xfer" hint */
1003 if (t->cs_change) {
ccdc7bf9 1004 omap2_mcspi_force_cs(spi, 0);
5fda88f5
S		 1005 cs_active = 0;
1006 }
1007 }
1008 /* Restore defaults if they were overriden */
1009 if (par_override) {
1010 par_override = 0;
1011 status = omap2_mcspi_setup_transfer(spi, NULL);
1012 }
ccdc7bf9 1013
5fda88f5
S		 1014 if (cs_active)
1015 omap2_mcspi_force_cs(spi, 0);
ccdc7bf9 1016
5fda88f5 1017 omap2_mcspi_set_enable(spi, 0);
ccdc7bf9 1018
5fda88f5 1019 m->status = status;
1f1a4384 1020
ccdc7bf9
SO		 1021}
1022
5fda88f5
S		 1023static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1024 struct spi_message *m)
ccdc7bf9
SO		 1025{
1026 struct omap2_mcspi *mcspi;
ccdc7bf9
SO		 1027 struct spi_transfer *t;
1028
5fda88f5 1029 mcspi = spi_master_get_devdata(master);
ccdc7bf9
SO		 1030 m->actual_length = 0;
1031 m->status = 0;
1032
1033 /* reject invalid messages and transfers */
5fda88f5 1034 if (list_empty(&m->transfers))
ccdc7bf9
SO		 1035 return -EINVAL;
1036 list_for_each_entry(t, &m->transfers, transfer_list) {
1037 const void *tx_buf = t->tx_buf;
1038 void *rx_buf = t->rx_buf;
1039 unsigned len = t->len;
1040
1041 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1042 || (len && !(rx_buf || tx_buf))
1043 || (t->bits_per_word &&
1044 ( t->bits_per_word < 4
1045 || t->bits_per_word > 32))) {
5fda88f5 1046 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
ccdc7bf9
SO		 1047 t->speed_hz,
1048 len,
1049 tx_buf ? "tx" : "",
1050 rx_buf ? "rx" : "",
1051 t->bits_per_word);
1052 return -EINVAL;
1053 }
57d9c10d 1054 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
5fda88f5 1055 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
57d9c10d
HH		 1056 t->speed_hz,
1057 OMAP2_MCSPI_MAX_FREQ >> 15);
ccdc7bf9
SO		 1058 return -EINVAL;
1059 }
1060
1061 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1062 continue;
1063
ccdc7bf9 1064 if (tx_buf != NULL) {
5fda88f5 1065 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
ccdc7bf9 1066 len, DMA_TO_DEVICE);
5fda88f5
S		 1067 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1068 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
ccdc7bf9
SO		 1069 'T', len);
1070 return -EINVAL;
1071 }
1072 }
1073 if (rx_buf != NULL) {
5fda88f5 1074 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
ccdc7bf9 1075 DMA_FROM_DEVICE);
5fda88f5
S		 1076 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1077 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
ccdc7bf9
SO		 1078 'R', len);
1079 if (tx_buf != NULL)
5fda88f5 1080 dma_unmap_single(mcspi->dev, t->tx_dma,
ccdc7bf9
SO		 1081 len, DMA_TO_DEVICE);
1082 return -EINVAL;
1083 }
1084 }
1085 }
1086
5fda88f5
S		 1087 omap2_mcspi_work(mcspi, m);
1088 spi_finalize_current_message(master);
ccdc7bf9
SO		 1089 return 0;
1090}
1091
24ab3275 1092static int __devinit omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
ccdc7bf9
SO		 1093{
1094 struct spi_master *master = mcspi->master;
1bd897f8 1095 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1bd897f8 1096 int ret = 0;
ccdc7bf9 1097
034d3dc9 1098 ret = pm_runtime_get_sync(mcspi->dev);
1f1a4384
G		 1099 if (ret < 0)
1100 return ret;
ddb22195 1101
39f8052d
S		 1102 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1103 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1104 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
ccdc7bf9
SO		 1105
1106 omap2_mcspi_set_master_mode(master);
034d3dc9
S		 1107 pm_runtime_mark_last_busy(mcspi->dev);
1108 pm_runtime_put_autosuspend(mcspi->dev);
ccdc7bf9
SO		 1109 return 0;
1110}
1111
1f1a4384
G		 1112static int omap_mcspi_runtime_resume(struct device *dev)
1113{
1114 struct omap2_mcspi *mcspi;
1115 struct spi_master *master;
1116
1117 master = dev_get_drvdata(dev);
1118 mcspi = spi_master_get_devdata(master);
1119 omap2_mcspi_restore_ctx(mcspi);
1120
1121 return 0;
1122}
1123
d5a80031
BC		 1124static struct omap2_mcspi_platform_config omap2_pdata = {
1125 .regs_offset = 0,
1126};
1127
1128static struct omap2_mcspi_platform_config omap4_pdata = {
1129 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1130};
1131
1132static const struct of_device_id omap_mcspi_of_match[] = {
1133 {
1134 .compatible = "ti,omap2-mcspi",
1135 .data = &omap2_pdata,
1136 },
1137 {
1138 .compatible = "ti,omap4-mcspi",
1139 .data = &omap4_pdata,
1140 },
1141 { },
1142};
1143MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
ccc7baed 1144
7d6b6d83 1145static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
ccdc7bf9
SO		 1146{
1147 struct spi_master *master;
83a01e72 1148 const struct omap2_mcspi_platform_config *pdata;
ccdc7bf9
SO		 1149 struct omap2_mcspi *mcspi;
1150 struct resource *r;
1151 int status = 0, i;
d5a80031
BC		 1152 u32 regs_offset = 0;
1153 static int bus_num = 1;
1154 struct device_node *node = pdev->dev.of_node;
1155 const struct of_device_id *match;
ec155afa 1156 struct pinctrl *pinctrl;
ccdc7bf9
SO		 1157
1158 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1159 if (master == NULL) {
1160 dev_dbg(&pdev->dev, "master allocation failed\n");
1161 return -ENOMEM;
1162 }
1163
e7db06b5
DB		 1164 /* the spi->mode bits understood by this driver: */
1165 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1166
ccdc7bf9 1167 master->setup = omap2_mcspi_setup;
5fda88f5
S		 1168 master->prepare_transfer_hardware = omap2_prepare_transfer;
1169 master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1170 master->transfer_one_message = omap2_mcspi_transfer_one_message;
ccdc7bf9 1171 master->cleanup = omap2_mcspi_cleanup;
d5a80031
BC		 1172 master->dev.of_node = node;
1173
0384e90b
DM		 1174 dev_set_drvdata(&pdev->dev, master);
1175
1176 mcspi = spi_master_get_devdata(master);
1177 mcspi->master = master;
1178
d5a80031
BC		 1179 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1180 if (match) {
1181 u32 num_cs = 1; /* default number of chipselect */
1182 pdata = match->data;
1183
1184 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1185 master->num_chipselect = num_cs;
1186 master->bus_num = bus_num++;
2cd45179
DM		 1187 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1188 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
d5a80031
BC		 1189 } else {
1190 pdata = pdev->dev.platform_data;
1191 master->num_chipselect = pdata->num_cs;
1192 if (pdev->id != -1)
1193 master->bus_num = pdev->id;
0384e90b 1194 mcspi->pin_dir = pdata->pin_dir;
d5a80031
BC		 1195 }
1196 regs_offset = pdata->regs_offset;
ccdc7bf9 1197
ccdc7bf9
SO		 1198 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1199 if (r == NULL) {
1200 status = -ENODEV;
39f1b565 1201 goto free_master;
ccdc7bf9 1202 }
1458d160 1203
d5a80031
BC		 1204 r->start += regs_offset;
1205 r->end += regs_offset;
1458d160 1206 mcspi->phys = r->start;
ccdc7bf9 1207
1a77b127 1208 mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
55c381e4
RK		 1209 if (!mcspi->base) {
1210 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1211 status = -ENOMEM;
1a77b127 1212 goto free_master;
55c381e4 1213 }
ccdc7bf9 1214
1f1a4384 1215 mcspi->dev = &pdev->dev;
ccdc7bf9 1216
1bd897f8 1217 INIT_LIST_HEAD(&mcspi->ctx.cs);
ccdc7bf9 1218
ccdc7bf9
SO		 1219 mcspi->dma_channels = kcalloc(master->num_chipselect,
1220 sizeof(struct omap2_mcspi_dma),
1221 GFP_KERNEL);
1222
1223 if (mcspi->dma_channels == NULL)
1a77b127 1224 goto free_master;
ccdc7bf9 1225
1a5d8190
C		 1226 for (i = 0; i < master->num_chipselect; i++) {
1227 char dma_ch_name[14];
1228 struct resource *dma_res;
1229
1230 sprintf(dma_ch_name, "rx%d", i);
1231 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1232 dma_ch_name);
1233 if (!dma_res) {
1234 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1235 status = -ENODEV;
1236 break;
1237 }
1238
1a5d8190
C		 1239 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1240 sprintf(dma_ch_name, "tx%d", i);
1241 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1242 dma_ch_name);
1243 if (!dma_res) {
1244 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1245 status = -ENODEV;
1246 break;
1247 }
1248
1a5d8190 1249 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
ccdc7bf9
SO		 1250 }
1251
39f1b565
S		 1252 if (status < 0)
1253 goto dma_chnl_free;
1254
ec155afa
MP		 1255 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1256 if (IS_ERR(pinctrl))
1257 dev_warn(&pdev->dev,
1258 "pins are not configured from the driver\n");
1259
27b5284c
S		 1260 pm_runtime_use_autosuspend(&pdev->dev);
1261 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1f1a4384
G		 1262 pm_runtime_enable(&pdev->dev);
1263
1264 if (status || omap2_mcspi_master_setup(mcspi) < 0)
39f1b565 1265 goto disable_pm;
ccdc7bf9
SO		 1266
1267 status = spi_register_master(master);
1268 if (status < 0)
37a2d84a 1269 goto disable_pm;
ccdc7bf9
SO		 1270
1271 return status;
1272
39f1b565 1273disable_pm:
751c925c 1274 pm_runtime_disable(&pdev->dev);
39f1b565 1275dma_chnl_free:
1f1a4384 1276 kfree(mcspi->dma_channels);
39f1b565 1277free_master:
37a2d84a 1278 spi_master_put(master);
ccdc7bf9
SO		 1279 return status;
1280}
1281
7d6b6d83 1282static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
ccdc7bf9
SO		 1283{
1284 struct spi_master *master;
1285 struct omap2_mcspi *mcspi;
1286 struct omap2_mcspi_dma *dma_channels;
ccdc7bf9
SO		 1287
1288 master = dev_get_drvdata(&pdev->dev);
1289 mcspi = spi_master_get_devdata(master);
1290 dma_channels = mcspi->dma_channels;
1291
a93a2029 1292 pm_runtime_put_sync(mcspi->dev);
751c925c 1293 pm_runtime_disable(&pdev->dev);
ccdc7bf9
SO		 1294
1295 spi_unregister_master(master);
1296 kfree(dma_channels);
1297
1298 return 0;
1299}
1300
7e38c3c4
KS		 1301/* work with hotplug and coldplug */
1302MODULE_ALIAS("platform:omap2_mcspi");
1303
42ce7fd6
GC		 1304#ifdef CONFIG_SUSPEND
1305/*
1306 * When SPI wake up from off-mode, CS is in activate state. If it was in
1307 * unactive state when driver was suspend, then force it to unactive state at
1308 * wake up.
1309 */
1310static int omap2_mcspi_resume(struct device *dev)
1311{
1312 struct spi_master *master = dev_get_drvdata(dev);
1313 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1bd897f8
BC		 1314 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1315 struct omap2_mcspi_cs *cs;
42ce7fd6 1316
034d3dc9 1317 pm_runtime_get_sync(mcspi->dev);
1bd897f8 1318 list_for_each_entry(cs, &ctx->cs, node) {
42ce7fd6 1319 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
42ce7fd6
GC		 1320 /*
1321 * We need to toggle CS state for OMAP take this
1322 * change in account.
1323 */
af4e944d 1324 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
42ce7fd6 1325 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
af4e944d 1326 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
42ce7fd6
GC		 1327 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1328 }
1329 }
034d3dc9
S		 1330 pm_runtime_mark_last_busy(mcspi->dev);
1331 pm_runtime_put_autosuspend(mcspi->dev);
42ce7fd6
GC		 1332 return 0;
1333}
1334#else
1335#define omap2_mcspi_resume NULL
1336#endif
1337
1338static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1339 .resume = omap2_mcspi_resume,
1f1a4384 1340 .runtime_resume = omap_mcspi_runtime_resume,
42ce7fd6
GC		 1341};
1342
ccdc7bf9
SO		 1343static struct platform_driver omap2_mcspi_driver = {
1344 .driver = {
1345 .name = "omap2_mcspi",
1346 .owner = THIS_MODULE,
d5a80031
BC		 1347 .pm = &omap2_mcspi_pm_ops,
1348 .of_match_table = omap_mcspi_of_match,
ccdc7bf9 1349 },
7d6b6d83
FB		 1350 .probe = omap2_mcspi_probe,
1351 .remove = __devexit_p(omap2_mcspi_remove),
ccdc7bf9
SO		 1352};
1353
9fdca9df 1354module_platform_driver(omap2_mcspi_driver);
ccdc7bf9 1355MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)