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spi: spi-omap2-mcspi.c: Toggle CS after each word
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi-omap2-mcspi.c
CommitLineData
ccdc7bf9
SO		 1/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
1a5d8190 6 * Juha Yrj�l� <juha.yrjola@nokia.com>
ccdc7bf9
SO		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/device.h>
29#include <linux/delay.h>
30#include <linux/dma-mapping.h>
53741ed8
RK		 31#include <linux/dmaengine.h>
32#include <linux/omap-dma.h>
ccdc7bf9
SO		 33#include <linux/platform_device.h>
34#include <linux/err.h>
35#include <linux/clk.h>
36#include <linux/io.h>
5a0e3ad6 37#include <linux/slab.h>
1f1a4384 38#include <linux/pm_runtime.h>
d5a80031
BC		 39#include <linux/of.h>
40#include <linux/of_device.h>
ec155afa 41#include <linux/pinctrl/consumer.h>
ccdc7bf9
SO		 42
43#include <linux/spi/spi.h>
44
2203747c 45#include <linux/platform_data/spi-omap2-mcspi.h>
ccdc7bf9
SO		 46
47#define OMAP2_MCSPI_MAX_FREQ 48000000
27b5284c 48#define SPI_AUTOSUSPEND_TIMEOUT 2000
ccdc7bf9
SO		 49
50#define OMAP2_MCSPI_REVISION 0x00
ccdc7bf9
SO		 51#define OMAP2_MCSPI_SYSSTATUS 0x14
52#define OMAP2_MCSPI_IRQSTATUS 0x18
53#define OMAP2_MCSPI_IRQENABLE 0x1c
54#define OMAP2_MCSPI_WAKEUPENABLE 0x20
55#define OMAP2_MCSPI_SYST 0x24
56#define OMAP2_MCSPI_MODULCTRL 0x28
57
58/* per-channel banks, 0x14 bytes each, first is: */
59#define OMAP2_MCSPI_CHCONF0 0x2c
60#define OMAP2_MCSPI_CHSTAT0 0x30
61#define OMAP2_MCSPI_CHCTRL0 0x34
62#define OMAP2_MCSPI_TX0 0x38
63#define OMAP2_MCSPI_RX0 0x3c
64
65/* per-register bitmasks: */
66
7a8fa725
JH		 67#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
68#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
69#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
ccdc7bf9 70
7a8fa725
JH		 71#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
72#define OMAP2_MCSPI_CHCONF_POL BIT(1)
ccdc7bf9 73#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
7a8fa725 74#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
ccdc7bf9 75#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
7a8fa725
JH		 76#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
77#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
ccdc7bf9 78#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
7a8fa725
JH		 79#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
80#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
81#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
82#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
83#define OMAP2_MCSPI_CHCONF_IS BIT(18)
84#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
85#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
ccdc7bf9 86
7a8fa725
JH		 87#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
88#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
89#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
ccdc7bf9 90
7a8fa725 91#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
ccdc7bf9 92
7a8fa725 93#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
ccdc7bf9
SO		 94
95/* We have 2 DMA channels per CS, one for RX and one for TX */
96struct omap2_mcspi_dma {
53741ed8
RK		 97 struct dma_chan *dma_tx;
98 struct dma_chan *dma_rx;
ccdc7bf9
SO		 99
100 int dma_tx_sync_dev;
101 int dma_rx_sync_dev;
102
103 struct completion dma_tx_completion;
104 struct completion dma_rx_completion;
105};
106
107/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
108 * cache operations; better heuristics consider wordsize and bitrate.
109 */
8b66c134 110#define DMA_MIN_BYTES 160
ccdc7bf9
SO		 111
112
1bd897f8
BC		 113/*
114 * Used for context save and restore, structure members to be updated whenever
115 * corresponding registers are modified.
116 */
117struct omap2_mcspi_regs {
118 u32 modulctrl;
119 u32 wakeupenable;
120 struct list_head cs;
121};
122
ccdc7bf9 123struct omap2_mcspi {
ccdc7bf9 124 struct spi_master *master;
ccdc7bf9
SO		 125 /* Virtual base address of the controller */
126 void __iomem *base;
e5480b73 127 unsigned long phys;
ccdc7bf9
SO		 128 /* SPI1 has 4 channels, while SPI2 has 2 */
129 struct omap2_mcspi_dma *dma_channels;
1bd897f8 130 struct device *dev;
1bd897f8 131 struct omap2_mcspi_regs ctx;
0384e90b 132 unsigned int pin_dir:1;
ccdc7bf9
SO		 133};
134
135struct omap2_mcspi_cs {
136 void __iomem *base;
e5480b73 137 unsigned long phys;
ccdc7bf9 138 int word_len;
89c05372 139 struct list_head node;
a41ae1ad
H		 140 /* Context save and restore shadow register */
141 u32 chconf0;
142};
143
ccdc7bf9
SO		 144static inline void mcspi_write_reg(struct spi_master *master,
145 int idx, u32 val)
146{
147 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
148
149 __raw_writel(val, mcspi->base + idx);
150}
151
152static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
153{
154 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
155
156 return __raw_readl(mcspi->base + idx);
157}
158
159static inline void mcspi_write_cs_reg(const struct spi_device *spi,
160 int idx, u32 val)
161{
162 struct omap2_mcspi_cs *cs = spi->controller_state;
163
164 __raw_writel(val, cs->base + idx);
165}
166
167static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
168{
169 struct omap2_mcspi_cs *cs = spi->controller_state;
170
171 return __raw_readl(cs->base + idx);
172}
173
a41ae1ad
H		 174static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
175{
176 struct omap2_mcspi_cs *cs = spi->controller_state;
177
178 return cs->chconf0;
179}
180
181static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
182{
183 struct omap2_mcspi_cs *cs = spi->controller_state;
184
185 cs->chconf0 = val;
186 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
a330ce20 187 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
a41ae1ad
H		 188}
189
ccdc7bf9
SO		 190static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
191 int is_read, int enable)
192{
193 u32 l, rw;
194
a41ae1ad 195 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 196
197 if (is_read) /* 1 is read, 0 write */
198 rw = OMAP2_MCSPI_CHCONF_DMAR;
199 else
200 rw = OMAP2_MCSPI_CHCONF_DMAW;
201
af4e944d
S		 202 if (enable)
203 l |= rw;
204 else
205 l &= ~rw;
206
a41ae1ad 207 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 208}
209
210static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
211{
212 u32 l;
213
214 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
215 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
4743a0f8
RT		 216 /* Flash post-writes */
217 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
ccdc7bf9
SO		 218}
219
220static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
221{
222 u32 l;
223
a41ae1ad 224 l = mcspi_cached_chconf0(spi);
af4e944d
S		 225 if (cs_active)
226 l |= OMAP2_MCSPI_CHCONF_FORCE;
227 else
228 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
229
a41ae1ad 230 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 231}
232
233static void omap2_mcspi_set_master_mode(struct spi_master *master)
234{
1bd897f8
BC		 235 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
236 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
ccdc7bf9
SO		 237 u32 l;
238
1bd897f8
BC		 239 /*
240 * Setup when switching from (reset default) slave mode
ccdc7bf9
SO		 241 * to single-channel master mode
242 */
243 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
af4e944d
S		 244 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
245 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
ccdc7bf9 246 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
a41ae1ad 247
1bd897f8 248 ctx->modulctrl = l;
a41ae1ad
H		 249}
250
251static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
252{
1bd897f8
BC		 253 struct spi_master *spi_cntrl = mcspi->master;
254 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
255 struct omap2_mcspi_cs *cs;
a41ae1ad
H		 256
257 /* McSPI: context restore */
1bd897f8
BC		 258 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
259 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
a41ae1ad 260
1bd897f8 261 list_for_each_entry(cs, &ctx->cs, node)
89c05372 262 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
a41ae1ad 263}
ccdc7bf9 264
5fda88f5
S		 265static int omap2_prepare_transfer(struct spi_master *master)
266{
267 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
268
269 pm_runtime_get_sync(mcspi->dev);
270 return 0;
271}
272
273static int omap2_unprepare_transfer(struct spi_master *master)
274{
275 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
276
277 pm_runtime_mark_last_busy(mcspi->dev);
278 pm_runtime_put_autosuspend(mcspi->dev);
279 return 0;
280}
281
2764c500
IK		 282static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
283{
284 unsigned long timeout;
285
286 timeout = jiffies + msecs_to_jiffies(1000);
287 while (!(__raw_readl(reg) & bit)) {
288 if (time_after(jiffies, timeout))
289 return -1;
290 cpu_relax();
291 }
292 return 0;
293}
294
53741ed8
RK		 295static void omap2_mcspi_rx_callback(void *data)
296{
297 struct spi_device *spi = data;
298 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
299 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
300
301 complete(&mcspi_dma->dma_rx_completion);
302
303 /* We must disable the DMA RX request */
304 omap2_mcspi_set_dma_req(spi, 1, 0);
305}
306
307static void omap2_mcspi_tx_callback(void *data)
308{
309 struct spi_device *spi = data;
310 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
311 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
312
313 complete(&mcspi_dma->dma_tx_completion);
314
315 /* We must disable the DMA TX request */
316 omap2_mcspi_set_dma_req(spi, 0, 0);
317}
318
d7b4394e
S		 319static void omap2_mcspi_tx_dma(struct spi_device *spi,
320 struct spi_transfer *xfer,
321 struct dma_slave_config cfg)
ccdc7bf9
SO		 322{
323 struct omap2_mcspi *mcspi;
ccdc7bf9 324 struct omap2_mcspi_dma *mcspi_dma;
8c7494a5 325 unsigned int count;
ccdc7bf9
SO		 326
327 mcspi = spi_master_get_devdata(spi->master);
328 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
d7b4394e 329 count = xfer->len;
ccdc7bf9 330
d7b4394e 331 if (mcspi_dma->dma_tx) {
53741ed8
RK		 332 struct dma_async_tx_descriptor *tx;
333 struct scatterlist sg;
334
335 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
336
337 sg_init_table(&sg, 1);
338 sg_dma_address(&sg) = xfer->tx_dma;
339 sg_dma_len(&sg) = xfer->len;
340
341 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
d7b4394e 342 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
53741ed8
RK		 343 if (tx) {
344 tx->callback = omap2_mcspi_tx_callback;
345 tx->callback_param = spi;
346 dmaengine_submit(tx);
347 } else {
348 /* FIXME: fall back to PIO? */
349 }
350 }
d7b4394e
S		 351 dma_async_issue_pending(mcspi_dma->dma_tx);
352 omap2_mcspi_set_dma_req(spi, 0, 1);
353
d7b4394e 354}
53741ed8 355
d7b4394e
S		 356static unsigned
357omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
358 struct dma_slave_config cfg,
359 unsigned es)
360{
361 struct omap2_mcspi *mcspi;
362 struct omap2_mcspi_dma *mcspi_dma;
363 unsigned int count;
364 u32 l;
365 int elements = 0;
366 int word_len, element_count;
367 struct omap2_mcspi_cs *cs = spi->controller_state;
368 mcspi = spi_master_get_devdata(spi->master);
369 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
370 count = xfer->len;
371 word_len = cs->word_len;
372 l = mcspi_cached_chconf0(spi);
53741ed8 373
d7b4394e
S		 374 if (word_len <= 8)
375 element_count = count;
376 else if (word_len <= 16)
377 element_count = count >> 1;
378 else /* word_len <= 32 */
379 element_count = count >> 2;
380
381 if (mcspi_dma->dma_rx) {
53741ed8
RK		 382 struct dma_async_tx_descriptor *tx;
383 struct scatterlist sg;
384 size_t len = xfer->len - es;
385
386 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
387
388 if (l & OMAP2_MCSPI_CHCONF_TURBO)
389 len -= es;
390
391 sg_init_table(&sg, 1);
392 sg_dma_address(&sg) = xfer->rx_dma;
393 sg_dma_len(&sg) = len;
394
395 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
d7b4394e
S		 396 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
397 DMA_CTRL_ACK);
53741ed8
RK		 398 if (tx) {
399 tx->callback = omap2_mcspi_rx_callback;
400 tx->callback_param = spi;
401 dmaengine_submit(tx);
402 } else {
d7b4394e 403 /* FIXME: fall back to PIO? */
2764c500 404 }
ccdc7bf9
SO		 405 }
406
d7b4394e
S		 407 dma_async_issue_pending(mcspi_dma->dma_rx);
408 omap2_mcspi_set_dma_req(spi, 1, 1);
4743a0f8 409
d7b4394e
S		 410 wait_for_completion(&mcspi_dma->dma_rx_completion);
411 dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
412 DMA_FROM_DEVICE);
413 omap2_mcspi_set_enable(spi, 0);
53741ed8 414
d7b4394e 415 elements = element_count - 1;
4743a0f8 416
d7b4394e
S		 417 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
418 elements--;
4743a0f8 419
57c5c28d 420 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
d7b4394e 421 & OMAP2_MCSPI_CHSTAT_RXS)) {
57c5c28d
EN		 422 u32 w;
423
424 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
425 if (word_len <= 8)
d7b4394e 426 ((u8 *)xfer->rx_buf)[elements++] = w;
57c5c28d 427 else if (word_len <= 16)
d7b4394e 428 ((u16 *)xfer->rx_buf)[elements++] = w;
57c5c28d 429 else /* word_len <= 32 */
d7b4394e 430 ((u32 *)xfer->rx_buf)[elements++] = w;
57c5c28d 431 } else {
d7b4394e
S		 432 dev_err(&spi->dev, "DMA RX penultimate word empty");
433 count -= (word_len <= 8) ? 2 :
434 (word_len <= 16) ? 4 :
435 /* word_len <= 32 */ 8;
436 omap2_mcspi_set_enable(spi, 1);
437 return count;
57c5c28d 438 }
ccdc7bf9 439 }
d7b4394e
S		 440 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
441 & OMAP2_MCSPI_CHSTAT_RXS)) {
442 u32 w;
443
444 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
445 if (word_len <= 8)
446 ((u8 *)xfer->rx_buf)[elements] = w;
447 else if (word_len <= 16)
448 ((u16 *)xfer->rx_buf)[elements] = w;
449 else /* word_len <= 32 */
450 ((u32 *)xfer->rx_buf)[elements] = w;
451 } else {
452 dev_err(&spi->dev, "DMA RX last word empty");
453 count -= (word_len <= 8) ? 1 :
454 (word_len <= 16) ? 2 :
455 /* word_len <= 32 */ 4;
456 }
457 omap2_mcspi_set_enable(spi, 1);
458 return count;
459}
460
461static unsigned
462omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
463{
464 struct omap2_mcspi *mcspi;
465 struct omap2_mcspi_cs *cs = spi->controller_state;
466 struct omap2_mcspi_dma *mcspi_dma;
467 unsigned int count;
468 u32 l;
469 u8 *rx;
470 const u8 *tx;
471 struct dma_slave_config cfg;
472 enum dma_slave_buswidth width;
473 unsigned es;
e47a682a 474 void __iomem *chstat_reg;
d7b4394e
S		 475
476 mcspi = spi_master_get_devdata(spi->master);
477 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
478 l = mcspi_cached_chconf0(spi);
479
480
481 if (cs->word_len <= 8) {
482 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
483 es = 1;
484 } else if (cs->word_len <= 16) {
485 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
486 es = 2;
487 } else {
488 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
489 es = 4;
490 }
491
492 memset(&cfg, 0, sizeof(cfg));
493 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
494 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
495 cfg.src_addr_width = width;
496 cfg.dst_addr_width = width;
497 cfg.src_maxburst = 1;
498 cfg.dst_maxburst = 1;
499
500 rx = xfer->rx_buf;
501 tx = xfer->tx_buf;
502
503 count = xfer->len;
504
505 if (tx != NULL)
506 omap2_mcspi_tx_dma(spi, xfer, cfg);
507
508 if (rx != NULL)
e47a682a
S		 509 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
510
511 if (tx != NULL) {
512 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
513 wait_for_completion(&mcspi_dma->dma_tx_completion);
514 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
515 DMA_TO_DEVICE);
516
517 /* for TX_ONLY mode, be sure all words have shifted out */
518 if (rx == NULL) {
519 if (mcspi_wait_for_reg_bit(chstat_reg,
520 OMAP2_MCSPI_CHSTAT_TXS) < 0)
521 dev_err(&spi->dev, "TXS timed out\n");
522 else if (mcspi_wait_for_reg_bit(chstat_reg,
523 OMAP2_MCSPI_CHSTAT_EOT) < 0)
524 dev_err(&spi->dev, "EOT timed out\n");
525 }
526 }
ccdc7bf9
SO		 527 return count;
528}
529
ccdc7bf9
SO		 530static unsigned
531omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
532{
533 struct omap2_mcspi *mcspi;
534 struct omap2_mcspi_cs *cs = spi->controller_state;
535 unsigned int count, c;
536 u32 l;
537 void __iomem *base = cs->base;
538 void __iomem *tx_reg;
539 void __iomem *rx_reg;
540 void __iomem *chstat_reg;
541 int word_len;
542
543 mcspi = spi_master_get_devdata(spi->master);
544 count = xfer->len;
545 c = count;
546 word_len = cs->word_len;
547
a41ae1ad 548 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 549
550 /* We store the pre-calculated register addresses on stack to speed
551 * up the transfer loop. */
552 tx_reg = base + OMAP2_MCSPI_TX0;
553 rx_reg = base + OMAP2_MCSPI_RX0;
554 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
555
adef658d
MJ		 556 if (c < (word_len>>3))
557 return 0;
558
ccdc7bf9
SO		 559 if (word_len <= 8) {
560 u8 *rx;
561 const u8 *tx;
562
563 rx = xfer->rx_buf;
564 tx = xfer->tx_buf;
565
566 do {
feed9bab 567 c -= 1;
ccdc7bf9
SO		 568 if (tx != NULL) {
569 if (mcspi_wait_for_reg_bit(chstat_reg,
570 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
571 dev_err(&spi->dev, "TXS timed out\n");
572 goto out;
573 }
079a176d 574 dev_vdbg(&spi->dev, "write-%d %02x\n",
ccdc7bf9 575 word_len, *tx);
ccdc7bf9
SO		 576 __raw_writel(*tx++, tx_reg);
577 }
578 if (rx != NULL) {
579 if (mcspi_wait_for_reg_bit(chstat_reg,
580 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
581 dev_err(&spi->dev, "RXS timed out\n");
582 goto out;
583 }
4743a0f8
RT		 584
585 if (c == 1 && tx == NULL &&
586 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
587 omap2_mcspi_set_enable(spi, 0);
588 *rx++ = __raw_readl(rx_reg);
079a176d 589 dev_vdbg(&spi->dev, "read-%d %02x\n",
4743a0f8 590 word_len, *(rx - 1));
4743a0f8
RT		 591 if (mcspi_wait_for_reg_bit(chstat_reg,
592 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
593 dev_err(&spi->dev,
594 "RXS timed out\n");
595 goto out;
596 }
597 c = 0;
598 } else if (c == 0 && tx == NULL) {
599 omap2_mcspi_set_enable(spi, 0);
600 }
601
ccdc7bf9 602 *rx++ = __raw_readl(rx_reg);
079a176d 603 dev_vdbg(&spi->dev, "read-%d %02x\n",
ccdc7bf9 604 word_len, *(rx - 1));
ccdc7bf9 605 }
95c5c3ab 606 } while (c);
ccdc7bf9
SO		 607 } else if (word_len <= 16) {
608 u16 *rx;
609 const u16 *tx;
610
611 rx = xfer->rx_buf;
612 tx = xfer->tx_buf;
613 do {
feed9bab 614 c -= 2;
ccdc7bf9
SO		 615 if (tx != NULL) {
616 if (mcspi_wait_for_reg_bit(chstat_reg,
617 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
618 dev_err(&spi->dev, "TXS timed out\n");
619 goto out;
620 }
079a176d 621 dev_vdbg(&spi->dev, "write-%d %04x\n",
ccdc7bf9 622 word_len, *tx);
ccdc7bf9
SO		 623 __raw_writel(*tx++, tx_reg);
624 }
625 if (rx != NULL) {
626 if (mcspi_wait_for_reg_bit(chstat_reg,
627 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
628 dev_err(&spi->dev, "RXS timed out\n");
629 goto out;
630 }
4743a0f8
RT		 631
632 if (c == 2 && tx == NULL &&
633 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
634 omap2_mcspi_set_enable(spi, 0);
635 *rx++ = __raw_readl(rx_reg);
079a176d 636 dev_vdbg(&spi->dev, "read-%d %04x\n",
4743a0f8 637 word_len, *(rx - 1));
4743a0f8
RT		 638 if (mcspi_wait_for_reg_bit(chstat_reg,
639 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
640 dev_err(&spi->dev,
641 "RXS timed out\n");
642 goto out;
643 }
644 c = 0;
645 } else if (c == 0 && tx == NULL) {
646 omap2_mcspi_set_enable(spi, 0);
647 }
648
ccdc7bf9 649 *rx++ = __raw_readl(rx_reg);
079a176d 650 dev_vdbg(&spi->dev, "read-%d %04x\n",
ccdc7bf9 651 word_len, *(rx - 1));
ccdc7bf9 652 }
95c5c3ab 653 } while (c >= 2);
ccdc7bf9
SO		 654 } else if (word_len <= 32) {
655 u32 *rx;
656 const u32 *tx;
657
658 rx = xfer->rx_buf;
659 tx = xfer->tx_buf;
660 do {
feed9bab 661 c -= 4;
ccdc7bf9
SO		 662 if (tx != NULL) {
663 if (mcspi_wait_for_reg_bit(chstat_reg,
664 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
665 dev_err(&spi->dev, "TXS timed out\n");
666 goto out;
667 }
079a176d 668 dev_vdbg(&spi->dev, "write-%d %08x\n",
ccdc7bf9 669 word_len, *tx);
ccdc7bf9
SO		 670 __raw_writel(*tx++, tx_reg);
671 }
672 if (rx != NULL) {
673 if (mcspi_wait_for_reg_bit(chstat_reg,
674 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
675 dev_err(&spi->dev, "RXS timed out\n");
676 goto out;
677 }
4743a0f8
RT		 678
679 if (c == 4 && tx == NULL &&
680 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
681 omap2_mcspi_set_enable(spi, 0);
682 *rx++ = __raw_readl(rx_reg);
079a176d 683 dev_vdbg(&spi->dev, "read-%d %08x\n",
4743a0f8 684 word_len, *(rx - 1));
4743a0f8
RT		 685 if (mcspi_wait_for_reg_bit(chstat_reg,
686 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
687 dev_err(&spi->dev,
688 "RXS timed out\n");
689 goto out;
690 }
691 c = 0;
692 } else if (c == 0 && tx == NULL) {
693 omap2_mcspi_set_enable(spi, 0);
694 }
695
ccdc7bf9 696 *rx++ = __raw_readl(rx_reg);
079a176d 697 dev_vdbg(&spi->dev, "read-%d %08x\n",
ccdc7bf9 698 word_len, *(rx - 1));
ccdc7bf9 699 }
95c5c3ab 700 } while (c >= 4);
ccdc7bf9
SO		 701 }
702
703 /* for TX_ONLY mode, be sure all words have shifted out */
704 if (xfer->rx_buf == NULL) {
705 if (mcspi_wait_for_reg_bit(chstat_reg,
706 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
707 dev_err(&spi->dev, "TXS timed out\n");
708 } else if (mcspi_wait_for_reg_bit(chstat_reg,
709 OMAP2_MCSPI_CHSTAT_EOT) < 0)
710 dev_err(&spi->dev, "EOT timed out\n");
e1993ed6
JW		 711
712 /* disable chan to purge rx datas received in TX_ONLY transfer,
713 * otherwise these rx datas will affect the direct following
714 * RX_ONLY transfer.
715 */
716 omap2_mcspi_set_enable(spi, 0);
ccdc7bf9
SO		 717 }
718out:
4743a0f8 719 omap2_mcspi_set_enable(spi, 1);
ccdc7bf9
SO		 720 return count - c;
721}
722
57d9c10d
HH		 723static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
724{
725 u32 div;
726
727 for (div = 0; div < 15; div++)
728 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
729 return div;
730
731 return 15;
732}
733
ccdc7bf9
SO		 734/* called only when no transfer is active to this device */
735static int omap2_mcspi_setup_transfer(struct spi_device *spi,
736 struct spi_transfer *t)
737{
738 struct omap2_mcspi_cs *cs = spi->controller_state;
739 struct omap2_mcspi *mcspi;
a41ae1ad 740 struct spi_master *spi_cntrl;
ccdc7bf9
SO		 741 u32 l = 0, div = 0;
742 u8 word_len = spi->bits_per_word;
9bd4517d 743 u32 speed_hz = spi->max_speed_hz;
ccdc7bf9
SO		 744
745 mcspi = spi_master_get_devdata(spi->master);
a41ae1ad 746 spi_cntrl = mcspi->master;
ccdc7bf9
SO		 747
748 if (t != NULL && t->bits_per_word)
749 word_len = t->bits_per_word;
750
751 cs->word_len = word_len;
752
9bd4517d
SE		 753 if (t && t->speed_hz)
754 speed_hz = t->speed_hz;
755
57d9c10d
HH		 756 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
757 div = omap2_mcspi_calc_divisor(speed_hz);
ccdc7bf9 758
a41ae1ad 759 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 760
761 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
762 * REVISIT: this controller could support SPI_3WIRE mode.
763 */
2cd45179 764 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
0384e90b
DM		 765 l &= ~OMAP2_MCSPI_CHCONF_IS;
766 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
767 l |= OMAP2_MCSPI_CHCONF_DPE0;
768 } else {
769 l |= OMAP2_MCSPI_CHCONF_IS;
770 l |= OMAP2_MCSPI_CHCONF_DPE1;
771 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
772 }
ccdc7bf9
SO		 773
774 /* wordlength */
775 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
776 l |= (word_len - 1) << 7;
777
778 /* set chipselect polarity; manage with FORCE */
779 if (!(spi->mode & SPI_CS_HIGH))
780 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
781 else
782 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
783
784 /* set clock divisor */
785 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
786 l |= div << 2;
787
788 /* set SPI mode 0..3 */
789 if (spi->mode & SPI_CPOL)
790 l |= OMAP2_MCSPI_CHCONF_POL;
791 else
792 l &= ~OMAP2_MCSPI_CHCONF_POL;
793 if (spi->mode & SPI_CPHA)
794 l |= OMAP2_MCSPI_CHCONF_PHA;
795 else
796 l &= ~OMAP2_MCSPI_CHCONF_PHA;
797
a41ae1ad 798 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 799
800 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
57d9c10d 801 OMAP2_MCSPI_MAX_FREQ >> div,
ccdc7bf9
SO		 802 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
803 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
804
805 return 0;
806}
807
ccdc7bf9
SO		 808static int omap2_mcspi_request_dma(struct spi_device *spi)
809{
810 struct spi_master *master = spi->master;
811 struct omap2_mcspi *mcspi;
812 struct omap2_mcspi_dma *mcspi_dma;
53741ed8
RK		 813 dma_cap_mask_t mask;
814 unsigned sig;
ccdc7bf9
SO		 815
816 mcspi = spi_master_get_devdata(master);
817 mcspi_dma = mcspi->dma_channels + spi->chip_select;
818
53741ed8
RK		 819 init_completion(&mcspi_dma->dma_rx_completion);
820 init_completion(&mcspi_dma->dma_tx_completion);
821
822 dma_cap_zero(mask);
823 dma_cap_set(DMA_SLAVE, mask);
53741ed8
RK		 824 sig = mcspi_dma->dma_rx_sync_dev;
825 mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
826 if (!mcspi_dma->dma_rx) {
827 dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
ccdc7bf9
SO		 828 return -EAGAIN;
829 }
830
53741ed8
RK		 831 sig = mcspi_dma->dma_tx_sync_dev;
832 mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
833 if (!mcspi_dma->dma_tx) {
834 dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n");
835 dma_release_channel(mcspi_dma->dma_rx);
836 mcspi_dma->dma_rx = NULL;
ccdc7bf9
SO		 837 return -EAGAIN;
838 }
839
ccdc7bf9
SO		 840 return 0;
841}
842
ccdc7bf9
SO		 843static int omap2_mcspi_setup(struct spi_device *spi)
844{
845 int ret;
1bd897f8
BC		 846 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
847 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
ccdc7bf9
SO		 848 struct omap2_mcspi_dma *mcspi_dma;
849 struct omap2_mcspi_cs *cs = spi->controller_state;
850
7d077197 851 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
ccdc7bf9
SO		 852 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
853 spi->bits_per_word);
854 return -EINVAL;
855 }
856
ccdc7bf9
SO		 857 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
858
859 if (!cs) {
10aa5a35 860 cs = kzalloc(sizeof *cs, GFP_KERNEL);
ccdc7bf9
SO		 861 if (!cs)
862 return -ENOMEM;
863 cs->base = mcspi->base + spi->chip_select * 0x14;
e5480b73 864 cs->phys = mcspi->phys + spi->chip_select * 0x14;
a41ae1ad 865 cs->chconf0 = 0;
ccdc7bf9 866 spi->controller_state = cs;
89c05372 867 /* Link this to context save list */
1bd897f8 868 list_add_tail(&cs->node, &ctx->cs);
ccdc7bf9
SO		 869 }
870
8c7494a5 871 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
ccdc7bf9
SO		 872 ret = omap2_mcspi_request_dma(spi);
873 if (ret < 0)
874 return ret;
875 }
876
034d3dc9 877 ret = pm_runtime_get_sync(mcspi->dev);
1f1a4384
G		 878 if (ret < 0)
879 return ret;
a41ae1ad 880
86eeb6fe 881 ret = omap2_mcspi_setup_transfer(spi, NULL);
034d3dc9
S		 882 pm_runtime_mark_last_busy(mcspi->dev);
883 pm_runtime_put_autosuspend(mcspi->dev);
ccdc7bf9
SO		 884
885 return ret;
886}
887
888static void omap2_mcspi_cleanup(struct spi_device *spi)
889{
890 struct omap2_mcspi *mcspi;
891 struct omap2_mcspi_dma *mcspi_dma;
89c05372 892 struct omap2_mcspi_cs *cs;
ccdc7bf9
SO		 893
894 mcspi = spi_master_get_devdata(spi->master);
ccdc7bf9 895
5e774943
SE		 896 if (spi->controller_state) {
897 /* Unlink controller state from context save list */
898 cs = spi->controller_state;
899 list_del(&cs->node);
89c05372 900
10aa5a35 901 kfree(cs);
5e774943 902 }
ccdc7bf9 903
99f1a43f
SE		 904 if (spi->chip_select < spi->master->num_chipselect) {
905 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
906
53741ed8
RK		 907 if (mcspi_dma->dma_rx) {
908 dma_release_channel(mcspi_dma->dma_rx);
909 mcspi_dma->dma_rx = NULL;
99f1a43f 910 }
53741ed8
RK		 911 if (mcspi_dma->dma_tx) {
912 dma_release_channel(mcspi_dma->dma_tx);
913 mcspi_dma->dma_tx = NULL;
99f1a43f 914 }
ccdc7bf9
SO		 915 }
916}
917
5fda88f5 918static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
ccdc7bf9 919{
ccdc7bf9
SO		 920
921 /* We only enable one channel at a time -- the one whose message is
5fda88f5 922 * -- although this controller would gladly
ccdc7bf9
SO		 923 * arbitrate among multiple channels. This corresponds to "single
924 * channel" master mode. As a side effect, we need to manage the
925 * chipselect with the FORCE bit ... CS != channel enable.
926 */
ccdc7bf9 927
5fda88f5
S		 928 struct spi_device *spi;
929 struct spi_transfer *t = NULL;
5cbc7ca9 930 struct spi_master *master;
5fda88f5
S		 931 int cs_active = 0;
932 struct omap2_mcspi_cs *cs;
933 struct omap2_mcspi_device_config *cd;
934 int par_override = 0;
935 int status = 0;
936 u32 chconf;
ccdc7bf9 937
5fda88f5 938 spi = m->spi;
5cbc7ca9 939 master = spi->master;
5fda88f5
S		 940 cs = spi->controller_state;
941 cd = spi->controller_data;
ccdc7bf9 942
5fda88f5
S		 943 omap2_mcspi_set_enable(spi, 1);
944 list_for_each_entry(t, &m->transfers, transfer_list) {
945 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
946 status = -EINVAL;
947 break;
948 }
949 if (par_override || t->speed_hz || t->bits_per_word) {
950 par_override = 1;
951 status = omap2_mcspi_setup_transfer(spi, t);
952 if (status < 0)
953 break;
954 if (!t->speed_hz && !t->bits_per_word)
955 par_override = 0;
956 }
5cbc7ca9
MB		 957 if (cd && cd->cs_per_word) {
958 chconf = mcspi->ctx.modulctrl;
959 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
960 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
961 mcspi->ctx.modulctrl =
962 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
963 }
964
4743a0f8 965
5fda88f5
S		 966 if (!cs_active) {
967 omap2_mcspi_force_cs(spi, 1);
968 cs_active = 1;
969 }
4743a0f8 970
5fda88f5
S		 971 chconf = mcspi_cached_chconf0(spi);
972 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
973 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
ccdc7bf9 974
5fda88f5
S		 975 if (t->tx_buf == NULL)
976 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
977 else if (t->rx_buf == NULL)
978 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
ccdc7bf9 979
5fda88f5
S		 980 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
981 /* Turbo mode is for more than one word */
982 if (t->len > ((cs->word_len + 7) >> 3))
983 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
984 }
ccdc7bf9 985
5fda88f5 986 mcspi_write_chconf0(spi, chconf);
ccdc7bf9 987
5fda88f5
S		 988 if (t->len) {
989 unsigned count;
990
991 /* RX_ONLY mode needs dummy data in TX reg */
992 if (t->tx_buf == NULL)
993 __raw_writel(0, cs->base
994 + OMAP2_MCSPI_TX0);
ccdc7bf9 995
5fda88f5
S		 996 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
997 count = omap2_mcspi_txrx_dma(spi, t);
998 else
999 count = omap2_mcspi_txrx_pio(spi, t);
1000 m->actual_length += count;
ccdc7bf9 1001
5fda88f5
S		 1002 if (count != t->len) {
1003 status = -EIO;
1004 break;
ccdc7bf9
SO		 1005 }
1006 }
1007
5fda88f5
S		 1008 if (t->delay_usecs)
1009 udelay(t->delay_usecs);
ccdc7bf9 1010
5fda88f5
S		 1011 /* ignore the "leave it on after last xfer" hint */
1012 if (t->cs_change) {
ccdc7bf9 1013 omap2_mcspi_force_cs(spi, 0);
5fda88f5
S		 1014 cs_active = 0;
1015 }
1016 }
1017 /* Restore defaults if they were overriden */
1018 if (par_override) {
1019 par_override = 0;
1020 status = omap2_mcspi_setup_transfer(spi, NULL);
1021 }
ccdc7bf9 1022
5fda88f5
S		 1023 if (cs_active)
1024 omap2_mcspi_force_cs(spi, 0);
ccdc7bf9 1025
5cbc7ca9
MB		 1026 if (cd && cd->cs_per_word) {
1027 chconf = mcspi->ctx.modulctrl;
1028 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1029 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1030 mcspi->ctx.modulctrl =
1031 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1032 }
1033
5fda88f5 1034 omap2_mcspi_set_enable(spi, 0);
ccdc7bf9 1035
5fda88f5 1036 m->status = status;
1f1a4384 1037
ccdc7bf9
SO		 1038}
1039
5fda88f5 1040static int omap2_mcspi_transfer_one_message(struct spi_master *master,
18dd6199 1041 struct spi_message *m)
ccdc7bf9
SO		 1042{
1043 struct omap2_mcspi *mcspi;
ccdc7bf9
SO		 1044 struct spi_transfer *t;
1045
5fda88f5 1046 mcspi = spi_master_get_devdata(master);
ccdc7bf9
SO		 1047 m->actual_length = 0;
1048 m->status = 0;
1049
1050 /* reject invalid messages and transfers */
5fda88f5 1051 if (list_empty(&m->transfers))
ccdc7bf9
SO		 1052 return -EINVAL;
1053 list_for_each_entry(t, &m->transfers, transfer_list) {
1054 const void *tx_buf = t->tx_buf;
1055 void *rx_buf = t->rx_buf;
1056 unsigned len = t->len;
1057
1058 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1059 || (len && !(rx_buf || tx_buf))
1060 || (t->bits_per_word &&
1061 ( t->bits_per_word < 4
18dd6199 1062 || t->bits_per_word > 32))) {
5fda88f5 1063 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
ccdc7bf9
SO		 1064 t->speed_hz,
1065 len,
1066 tx_buf ? "tx" : "",
1067 rx_buf ? "rx" : "",
1068 t->bits_per_word);
1069 return -EINVAL;
1070 }
57d9c10d 1071 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
5fda88f5 1072 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
18dd6199
MB		 1073 t->speed_hz,
1074 OMAP2_MCSPI_MAX_FREQ >> 15);
ccdc7bf9
SO		 1075 return -EINVAL;
1076 }
1077
1078 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1079 continue;
1080
ccdc7bf9 1081 if (tx_buf != NULL) {
5fda88f5 1082 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
ccdc7bf9 1083 len, DMA_TO_DEVICE);
5fda88f5
S		 1084 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1085 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
ccdc7bf9
SO		 1086 'T', len);
1087 return -EINVAL;
1088 }
1089 }
1090 if (rx_buf != NULL) {
5fda88f5 1091 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
ccdc7bf9 1092 DMA_FROM_DEVICE);
5fda88f5
S		 1093 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1094 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
ccdc7bf9
SO		 1095 'R', len);
1096 if (tx_buf != NULL)
5fda88f5 1097 dma_unmap_single(mcspi->dev, t->tx_dma,
ccdc7bf9
SO		 1098 len, DMA_TO_DEVICE);
1099 return -EINVAL;
1100 }
1101 }
1102 }
1103
5fda88f5
S		 1104 omap2_mcspi_work(mcspi, m);
1105 spi_finalize_current_message(master);
ccdc7bf9
SO		 1106 return 0;
1107}
1108
fd4a319b 1109static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
ccdc7bf9
SO		 1110{
1111 struct spi_master *master = mcspi->master;
1bd897f8 1112 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1bd897f8 1113 int ret = 0;
ccdc7bf9 1114
034d3dc9 1115 ret = pm_runtime_get_sync(mcspi->dev);
1f1a4384
G		 1116 if (ret < 0)
1117 return ret;
ddb22195 1118
39f8052d 1119 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
18dd6199 1120 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
39f8052d 1121 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
ccdc7bf9
SO		 1122
1123 omap2_mcspi_set_master_mode(master);
034d3dc9
S		 1124 pm_runtime_mark_last_busy(mcspi->dev);
1125 pm_runtime_put_autosuspend(mcspi->dev);
ccdc7bf9
SO		 1126 return 0;
1127}
1128
1f1a4384
G		 1129static int omap_mcspi_runtime_resume(struct device *dev)
1130{
1131 struct omap2_mcspi *mcspi;
1132 struct spi_master *master;
1133
1134 master = dev_get_drvdata(dev);
1135 mcspi = spi_master_get_devdata(master);
1136 omap2_mcspi_restore_ctx(mcspi);
1137
1138 return 0;
1139}
1140
d5a80031
BC		 1141static struct omap2_mcspi_platform_config omap2_pdata = {
1142 .regs_offset = 0,
1143};
1144
1145static struct omap2_mcspi_platform_config omap4_pdata = {
1146 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1147};
1148
1149static const struct of_device_id omap_mcspi_of_match[] = {
1150 {
1151 .compatible = "ti,omap2-mcspi",
1152 .data = &omap2_pdata,
1153 },
1154 {
1155 .compatible = "ti,omap4-mcspi",
1156 .data = &omap4_pdata,
1157 },
1158 { },
1159};
1160MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
ccc7baed 1161
fd4a319b 1162static int omap2_mcspi_probe(struct platform_device *pdev)
ccdc7bf9
SO		 1163{
1164 struct spi_master *master;
83a01e72 1165 const struct omap2_mcspi_platform_config *pdata;
ccdc7bf9
SO		 1166 struct omap2_mcspi *mcspi;
1167 struct resource *r;
1168 int status = 0, i;
d5a80031
BC		 1169 u32 regs_offset = 0;
1170 static int bus_num = 1;
1171 struct device_node *node = pdev->dev.of_node;
1172 const struct of_device_id *match;
ec155afa 1173 struct pinctrl *pinctrl;
ccdc7bf9
SO		 1174
1175 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1176 if (master == NULL) {
1177 dev_dbg(&pdev->dev, "master allocation failed\n");
1178 return -ENOMEM;
1179 }
1180
e7db06b5
DB		 1181 /* the spi->mode bits understood by this driver: */
1182 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1183
ccdc7bf9 1184 master->setup = omap2_mcspi_setup;
5fda88f5
S		 1185 master->prepare_transfer_hardware = omap2_prepare_transfer;
1186 master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1187 master->transfer_one_message = omap2_mcspi_transfer_one_message;
ccdc7bf9 1188 master->cleanup = omap2_mcspi_cleanup;
d5a80031
BC		 1189 master->dev.of_node = node;
1190
0384e90b
DM		 1191 dev_set_drvdata(&pdev->dev, master);
1192
1193 mcspi = spi_master_get_devdata(master);
1194 mcspi->master = master;
1195
d5a80031
BC		 1196 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1197 if (match) {
1198 u32 num_cs = 1; /* default number of chipselect */
1199 pdata = match->data;
1200
1201 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1202 master->num_chipselect = num_cs;
1203 master->bus_num = bus_num++;
2cd45179
DM		 1204 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1205 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
d5a80031
BC		 1206 } else {
1207 pdata = pdev->dev.platform_data;
1208 master->num_chipselect = pdata->num_cs;
1209 if (pdev->id != -1)
1210 master->bus_num = pdev->id;
0384e90b 1211 mcspi->pin_dir = pdata->pin_dir;
d5a80031
BC		 1212 }
1213 regs_offset = pdata->regs_offset;
ccdc7bf9 1214
ccdc7bf9
SO		 1215 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1216 if (r == NULL) {
1217 status = -ENODEV;
39f1b565 1218 goto free_master;
ccdc7bf9 1219 }
1458d160 1220
d5a80031
BC		 1221 r->start += regs_offset;
1222 r->end += regs_offset;
1458d160 1223 mcspi->phys = r->start;
ccdc7bf9 1224
1a77b127 1225 mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
55c381e4
RK		 1226 if (!mcspi->base) {
1227 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1228 status = -ENOMEM;
1a77b127 1229 goto free_master;
55c381e4 1230 }
ccdc7bf9 1231
1f1a4384 1232 mcspi->dev = &pdev->dev;
ccdc7bf9 1233
1bd897f8 1234 INIT_LIST_HEAD(&mcspi->ctx.cs);
ccdc7bf9 1235
ccdc7bf9
SO		 1236 mcspi->dma_channels = kcalloc(master->num_chipselect,
1237 sizeof(struct omap2_mcspi_dma),
1238 GFP_KERNEL);
1239
1240 if (mcspi->dma_channels == NULL)
1a77b127 1241 goto free_master;
ccdc7bf9 1242
1a5d8190
C		 1243 for (i = 0; i < master->num_chipselect; i++) {
1244 char dma_ch_name[14];
1245 struct resource *dma_res;
1246
1247 sprintf(dma_ch_name, "rx%d", i);
1248 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
18dd6199 1249 dma_ch_name);
1a5d8190
C		 1250 if (!dma_res) {
1251 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1252 status = -ENODEV;
1253 break;
1254 }
1255
1a5d8190
C		 1256 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1257 sprintf(dma_ch_name, "tx%d", i);
1258 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
18dd6199 1259 dma_ch_name);
1a5d8190
C		 1260 if (!dma_res) {
1261 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1262 status = -ENODEV;
1263 break;
1264 }
1265
1a5d8190 1266 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
ccdc7bf9
SO		 1267 }
1268
39f1b565
S		 1269 if (status < 0)
1270 goto dma_chnl_free;
1271
ec155afa
MP		 1272 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1273 if (IS_ERR(pinctrl))
1274 dev_warn(&pdev->dev,
18dd6199 1275 "pins are not configured from the driver\n");
ec155afa 1276
27b5284c
S		 1277 pm_runtime_use_autosuspend(&pdev->dev);
1278 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1f1a4384
G		 1279 pm_runtime_enable(&pdev->dev);
1280
1281 if (status || omap2_mcspi_master_setup(mcspi) < 0)
39f1b565 1282 goto disable_pm;
ccdc7bf9
SO		 1283
1284 status = spi_register_master(master);
1285 if (status < 0)
37a2d84a 1286 goto disable_pm;
ccdc7bf9
SO		 1287
1288 return status;
1289
39f1b565 1290disable_pm:
751c925c 1291 pm_runtime_disable(&pdev->dev);
39f1b565 1292dma_chnl_free:
1f1a4384 1293 kfree(mcspi->dma_channels);
39f1b565 1294free_master:
37a2d84a 1295 spi_master_put(master);
ccdc7bf9
SO		 1296 return status;
1297}
1298
fd4a319b 1299static int omap2_mcspi_remove(struct platform_device *pdev)
ccdc7bf9
SO		 1300{
1301 struct spi_master *master;
1302 struct omap2_mcspi *mcspi;
1303 struct omap2_mcspi_dma *dma_channels;
ccdc7bf9
SO		 1304
1305 master = dev_get_drvdata(&pdev->dev);
1306 mcspi = spi_master_get_devdata(master);
1307 dma_channels = mcspi->dma_channels;
1308
a93a2029 1309 pm_runtime_put_sync(mcspi->dev);
751c925c 1310 pm_runtime_disable(&pdev->dev);
ccdc7bf9
SO		 1311
1312 spi_unregister_master(master);
1313 kfree(dma_channels);
1314
1315 return 0;
1316}
1317
7e38c3c4
KS		 1318/* work with hotplug and coldplug */
1319MODULE_ALIAS("platform:omap2_mcspi");
1320
42ce7fd6
GC		 1321#ifdef CONFIG_SUSPEND
1322/*
1323 * When SPI wake up from off-mode, CS is in activate state. If it was in
1324 * unactive state when driver was suspend, then force it to unactive state at
1325 * wake up.
1326 */
1327static int omap2_mcspi_resume(struct device *dev)
1328{
1329 struct spi_master *master = dev_get_drvdata(dev);
1330 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1bd897f8
BC		 1331 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1332 struct omap2_mcspi_cs *cs;
42ce7fd6 1333
034d3dc9 1334 pm_runtime_get_sync(mcspi->dev);
1bd897f8 1335 list_for_each_entry(cs, &ctx->cs, node) {
42ce7fd6 1336 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
42ce7fd6
GC		 1337 /*
1338 * We need to toggle CS state for OMAP take this
1339 * change in account.
1340 */
af4e944d 1341 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
42ce7fd6 1342 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
af4e944d 1343 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
42ce7fd6
GC		 1344 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1345 }
1346 }
034d3dc9
S		 1347 pm_runtime_mark_last_busy(mcspi->dev);
1348 pm_runtime_put_autosuspend(mcspi->dev);
42ce7fd6
GC		 1349 return 0;
1350}
1351#else
1352#define omap2_mcspi_resume NULL
1353#endif
1354
1355static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1356 .resume = omap2_mcspi_resume,
1f1a4384 1357 .runtime_resume = omap_mcspi_runtime_resume,
42ce7fd6
GC		 1358};
1359
ccdc7bf9
SO		 1360static struct platform_driver omap2_mcspi_driver = {
1361 .driver = {
1362 .name = "omap2_mcspi",
1363 .owner = THIS_MODULE,
d5a80031
BC		 1364 .pm = &omap2_mcspi_pm_ops,
1365 .of_match_table = omap_mcspi_of_match,
ccdc7bf9 1366 },
7d6b6d83 1367 .probe = omap2_mcspi_probe,
fd4a319b 1368 .remove = omap2_mcspi_remove,
ccdc7bf9
SO		 1369};
1370
9fdca9df 1371module_platform_driver(omap2_mcspi_driver);
ccdc7bf9 1372MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)