Commit | Line | Data |
---|---|---|
ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/dma-mapping.h> | |
53741ed8 RK |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/omap-dma.h> | |
ccdc7bf9 SO |
33 | #include <linux/platform_device.h> |
34 | #include <linux/err.h> | |
35 | #include <linux/clk.h> | |
36 | #include <linux/io.h> | |
5a0e3ad6 | 37 | #include <linux/slab.h> |
1f1a4384 | 38 | #include <linux/pm_runtime.h> |
d5a80031 BC |
39 | #include <linux/of.h> |
40 | #include <linux/of_device.h> | |
ccdc7bf9 SO |
41 | |
42 | #include <linux/spi/spi.h> | |
43 | ||
2203747c | 44 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
45 | |
46 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
27b5284c | 47 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
48 | |
49 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
50 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
51 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
52 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
53 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
54 | #define OMAP2_MCSPI_SYST 0x24 | |
55 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
56 | ||
57 | /* per-channel banks, 0x14 bytes each, first is: */ | |
58 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
59 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
60 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
61 | #define OMAP2_MCSPI_TX0 0x38 | |
62 | #define OMAP2_MCSPI_RX0 0x3c | |
63 | ||
64 | /* per-register bitmasks: */ | |
65 | ||
7a8fa725 JH |
66 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
67 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
68 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 69 | |
7a8fa725 JH |
70 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
71 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 72 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 73 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 74 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
75 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
76 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 77 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
78 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
79 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
80 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
81 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
82 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
83 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
84 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
ccdc7bf9 | 85 | |
7a8fa725 JH |
86 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
87 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
88 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
ccdc7bf9 | 89 | |
7a8fa725 | 90 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
ccdc7bf9 | 91 | |
7a8fa725 | 92 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
93 | |
94 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
95 | struct omap2_mcspi_dma { | |
53741ed8 RK |
96 | struct dma_chan *dma_tx; |
97 | struct dma_chan *dma_rx; | |
ccdc7bf9 SO |
98 | |
99 | int dma_tx_sync_dev; | |
100 | int dma_rx_sync_dev; | |
101 | ||
102 | struct completion dma_tx_completion; | |
103 | struct completion dma_rx_completion; | |
104 | }; | |
105 | ||
106 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
107 | * cache operations; better heuristics consider wordsize and bitrate. | |
108 | */ | |
8b66c134 | 109 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
110 | |
111 | ||
1bd897f8 BC |
112 | /* |
113 | * Used for context save and restore, structure members to be updated whenever | |
114 | * corresponding registers are modified. | |
115 | */ | |
116 | struct omap2_mcspi_regs { | |
117 | u32 modulctrl; | |
118 | u32 wakeupenable; | |
119 | struct list_head cs; | |
120 | }; | |
121 | ||
ccdc7bf9 | 122 | struct omap2_mcspi { |
ccdc7bf9 | 123 | struct spi_master *master; |
ccdc7bf9 SO |
124 | /* Virtual base address of the controller */ |
125 | void __iomem *base; | |
e5480b73 | 126 | unsigned long phys; |
ccdc7bf9 SO |
127 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
128 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 129 | struct device *dev; |
1bd897f8 | 130 | struct omap2_mcspi_regs ctx; |
ccdc7bf9 SO |
131 | }; |
132 | ||
133 | struct omap2_mcspi_cs { | |
134 | void __iomem *base; | |
e5480b73 | 135 | unsigned long phys; |
ccdc7bf9 | 136 | int word_len; |
89c05372 | 137 | struct list_head node; |
a41ae1ad H |
138 | /* Context save and restore shadow register */ |
139 | u32 chconf0; | |
140 | }; | |
141 | ||
ccdc7bf9 SO |
142 | #define MOD_REG_BIT(val, mask, set) do { \ |
143 | if (set) \ | |
144 | val |= mask; \ | |
145 | else \ | |
146 | val &= ~mask; \ | |
147 | } while (0) | |
148 | ||
149 | static inline void mcspi_write_reg(struct spi_master *master, | |
150 | int idx, u32 val) | |
151 | { | |
152 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
153 | ||
154 | __raw_writel(val, mcspi->base + idx); | |
155 | } | |
156 | ||
157 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
158 | { | |
159 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
160 | ||
161 | return __raw_readl(mcspi->base + idx); | |
162 | } | |
163 | ||
164 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
165 | int idx, u32 val) | |
166 | { | |
167 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
168 | ||
169 | __raw_writel(val, cs->base + idx); | |
170 | } | |
171 | ||
172 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
173 | { | |
174 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
175 | ||
176 | return __raw_readl(cs->base + idx); | |
177 | } | |
178 | ||
a41ae1ad H |
179 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
180 | { | |
181 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
182 | ||
183 | return cs->chconf0; | |
184 | } | |
185 | ||
186 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
187 | { | |
188 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
189 | ||
190 | cs->chconf0 = val; | |
191 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 192 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
193 | } |
194 | ||
ccdc7bf9 SO |
195 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
196 | int is_read, int enable) | |
197 | { | |
198 | u32 l, rw; | |
199 | ||
a41ae1ad | 200 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
201 | |
202 | if (is_read) /* 1 is read, 0 write */ | |
203 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
204 | else | |
205 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
206 | ||
207 | MOD_REG_BIT(l, rw, enable); | |
a41ae1ad | 208 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
209 | } |
210 | ||
211 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
212 | { | |
213 | u32 l; | |
214 | ||
215 | l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; | |
216 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); | |
4743a0f8 RT |
217 | /* Flash post-writes */ |
218 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
219 | } |
220 | ||
221 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) | |
222 | { | |
223 | u32 l; | |
224 | ||
a41ae1ad | 225 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 | 226 | MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active); |
a41ae1ad | 227 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
228 | } |
229 | ||
230 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
231 | { | |
1bd897f8 BC |
232 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
233 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
234 | u32 l; |
235 | ||
1bd897f8 BC |
236 | /* |
237 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
238 | * to single-channel master mode |
239 | */ | |
240 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
241 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0); | |
242 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0); | |
243 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1); | |
244 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); | |
a41ae1ad | 245 | |
1bd897f8 | 246 | ctx->modulctrl = l; |
a41ae1ad H |
247 | } |
248 | ||
249 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) | |
250 | { | |
1bd897f8 BC |
251 | struct spi_master *spi_cntrl = mcspi->master; |
252 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
253 | struct omap2_mcspi_cs *cs; | |
a41ae1ad H |
254 | |
255 | /* McSPI: context restore */ | |
1bd897f8 BC |
256 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
257 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
a41ae1ad | 258 | |
1bd897f8 | 259 | list_for_each_entry(cs, &ctx->cs, node) |
89c05372 | 260 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
261 | } |
262 | static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) | |
263 | { | |
27b5284c S |
264 | pm_runtime_mark_last_busy(mcspi->dev); |
265 | pm_runtime_put_autosuspend(mcspi->dev); | |
a41ae1ad H |
266 | } |
267 | ||
268 | static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) | |
269 | { | |
1f1a4384 | 270 | return pm_runtime_get_sync(mcspi->dev); |
ccdc7bf9 SO |
271 | } |
272 | ||
5fda88f5 S |
273 | static int omap2_prepare_transfer(struct spi_master *master) |
274 | { | |
275 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
276 | ||
277 | pm_runtime_get_sync(mcspi->dev); | |
278 | return 0; | |
279 | } | |
280 | ||
281 | static int omap2_unprepare_transfer(struct spi_master *master) | |
282 | { | |
283 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
284 | ||
285 | pm_runtime_mark_last_busy(mcspi->dev); | |
286 | pm_runtime_put_autosuspend(mcspi->dev); | |
287 | return 0; | |
288 | } | |
289 | ||
2764c500 IK |
290 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
291 | { | |
292 | unsigned long timeout; | |
293 | ||
294 | timeout = jiffies + msecs_to_jiffies(1000); | |
295 | while (!(__raw_readl(reg) & bit)) { | |
296 | if (time_after(jiffies, timeout)) | |
297 | return -1; | |
298 | cpu_relax(); | |
299 | } | |
300 | return 0; | |
301 | } | |
302 | ||
53741ed8 RK |
303 | static void omap2_mcspi_rx_callback(void *data) |
304 | { | |
305 | struct spi_device *spi = data; | |
306 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
307 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
308 | ||
309 | complete(&mcspi_dma->dma_rx_completion); | |
310 | ||
311 | /* We must disable the DMA RX request */ | |
312 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
313 | } | |
314 | ||
315 | static void omap2_mcspi_tx_callback(void *data) | |
316 | { | |
317 | struct spi_device *spi = data; | |
318 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
319 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
320 | ||
321 | complete(&mcspi_dma->dma_tx_completion); | |
322 | ||
323 | /* We must disable the DMA TX request */ | |
324 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
325 | } | |
326 | ||
ccdc7bf9 SO |
327 | static unsigned |
328 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
329 | { | |
330 | struct omap2_mcspi *mcspi; | |
331 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
332 | struct omap2_mcspi_dma *mcspi_dma; | |
8c7494a5 RK |
333 | unsigned int count; |
334 | int word_len, element_count; | |
8b20c8cb | 335 | int elements = 0; |
4743a0f8 | 336 | u32 l; |
ccdc7bf9 SO |
337 | u8 * rx; |
338 | const u8 * tx; | |
2764c500 | 339 | void __iomem *chstat_reg; |
53741ed8 RK |
340 | struct dma_slave_config cfg; |
341 | enum dma_slave_buswidth width; | |
342 | unsigned es; | |
ccdc7bf9 SO |
343 | |
344 | mcspi = spi_master_get_devdata(spi->master); | |
345 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
4743a0f8 | 346 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 | 347 | |
2764c500 IK |
348 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
349 | ||
53741ed8 RK |
350 | if (cs->word_len <= 8) { |
351 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
352 | es = 1; | |
353 | } else if (cs->word_len <= 16) { | |
354 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
355 | es = 2; | |
356 | } else { | |
357 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
358 | es = 4; | |
359 | } | |
360 | ||
361 | memset(&cfg, 0, sizeof(cfg)); | |
362 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
363 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
364 | cfg.src_addr_width = width; | |
365 | cfg.dst_addr_width = width; | |
366 | cfg.src_maxburst = 1; | |
367 | cfg.dst_maxburst = 1; | |
368 | ||
369 | if (xfer->tx_buf && mcspi_dma->dma_tx) { | |
370 | struct dma_async_tx_descriptor *tx; | |
371 | struct scatterlist sg; | |
372 | ||
373 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
374 | ||
375 | sg_init_table(&sg, 1); | |
376 | sg_dma_address(&sg) = xfer->tx_dma; | |
377 | sg_dma_len(&sg) = xfer->len; | |
378 | ||
379 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, | |
380 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
381 | if (tx) { | |
382 | tx->callback = omap2_mcspi_tx_callback; | |
383 | tx->callback_param = spi; | |
384 | dmaengine_submit(tx); | |
385 | } else { | |
386 | /* FIXME: fall back to PIO? */ | |
387 | } | |
388 | } | |
389 | ||
390 | if (xfer->rx_buf && mcspi_dma->dma_rx) { | |
391 | struct dma_async_tx_descriptor *tx; | |
392 | struct scatterlist sg; | |
393 | size_t len = xfer->len - es; | |
394 | ||
395 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
396 | ||
397 | if (l & OMAP2_MCSPI_CHCONF_TURBO) | |
398 | len -= es; | |
399 | ||
400 | sg_init_table(&sg, 1); | |
401 | sg_dma_address(&sg) = xfer->rx_dma; | |
402 | sg_dma_len(&sg) = len; | |
403 | ||
404 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, | |
405 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
406 | if (tx) { | |
407 | tx->callback = omap2_mcspi_rx_callback; | |
408 | tx->callback_param = spi; | |
409 | dmaengine_submit(tx); | |
410 | } else { | |
411 | /* FIXME: fall back to PIO? */ | |
412 | } | |
413 | } | |
414 | ||
ccdc7bf9 | 415 | count = xfer->len; |
ccdc7bf9 SO |
416 | word_len = cs->word_len; |
417 | ||
ccdc7bf9 SO |
418 | rx = xfer->rx_buf; |
419 | tx = xfer->tx_buf; | |
420 | ||
421 | if (word_len <= 8) { | |
ccdc7bf9 SO |
422 | element_count = count; |
423 | } else if (word_len <= 16) { | |
ccdc7bf9 SO |
424 | element_count = count >> 1; |
425 | } else /* word_len <= 32 */ { | |
ccdc7bf9 SO |
426 | element_count = count >> 2; |
427 | } | |
428 | ||
429 | if (tx != NULL) { | |
8c7494a5 | 430 | dma_async_issue_pending(mcspi_dma->dma_tx); |
ccdc7bf9 SO |
431 | omap2_mcspi_set_dma_req(spi, 0, 1); |
432 | } | |
433 | ||
434 | if (rx != NULL) { | |
8c7494a5 | 435 | dma_async_issue_pending(mcspi_dma->dma_rx); |
ccdc7bf9 SO |
436 | omap2_mcspi_set_dma_req(spi, 1, 1); |
437 | } | |
438 | ||
439 | if (tx != NULL) { | |
440 | wait_for_completion(&mcspi_dma->dma_tx_completion); | |
a3ce9a80 S |
441 | dma_unmap_single(mcspi->dev, xfer->tx_dma, count, |
442 | DMA_TO_DEVICE); | |
2764c500 IK |
443 | |
444 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
445 | if (rx == NULL) { | |
446 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
447 | OMAP2_MCSPI_CHSTAT_TXS) < 0) | |
448 | dev_err(&spi->dev, "TXS timed out\n"); | |
449 | else if (mcspi_wait_for_reg_bit(chstat_reg, | |
450 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
451 | dev_err(&spi->dev, "EOT timed out\n"); | |
452 | } | |
ccdc7bf9 SO |
453 | } |
454 | ||
455 | if (rx != NULL) { | |
456 | wait_for_completion(&mcspi_dma->dma_rx_completion); | |
a3ce9a80 S |
457 | dma_unmap_single(mcspi->dev, xfer->rx_dma, count, |
458 | DMA_FROM_DEVICE); | |
57c5c28d | 459 | omap2_mcspi_set_enable(spi, 0); |
4743a0f8 | 460 | |
53741ed8 RK |
461 | elements = element_count - 1; |
462 | ||
4743a0f8 | 463 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
53741ed8 | 464 | elements--; |
4743a0f8 RT |
465 | |
466 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) | |
467 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
468 | u32 w; | |
469 | ||
470 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
471 | if (word_len <= 8) | |
472 | ((u8 *)xfer->rx_buf)[elements++] = w; | |
473 | else if (word_len <= 16) | |
474 | ((u16 *)xfer->rx_buf)[elements++] = w; | |
475 | else /* word_len <= 32 */ | |
476 | ((u32 *)xfer->rx_buf)[elements++] = w; | |
477 | } else { | |
478 | dev_err(&spi->dev, | |
479 | "DMA RX penultimate word empty"); | |
480 | count -= (word_len <= 8) ? 2 : | |
481 | (word_len <= 16) ? 4 : | |
482 | /* word_len <= 32 */ 8; | |
483 | omap2_mcspi_set_enable(spi, 1); | |
484 | return count; | |
485 | } | |
486 | } | |
487 | ||
57c5c28d EN |
488 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
489 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
490 | u32 w; | |
491 | ||
492 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
493 | if (word_len <= 8) | |
4743a0f8 | 494 | ((u8 *)xfer->rx_buf)[elements] = w; |
57c5c28d | 495 | else if (word_len <= 16) |
4743a0f8 | 496 | ((u16 *)xfer->rx_buf)[elements] = w; |
57c5c28d | 497 | else /* word_len <= 32 */ |
4743a0f8 | 498 | ((u32 *)xfer->rx_buf)[elements] = w; |
57c5c28d EN |
499 | } else { |
500 | dev_err(&spi->dev, "DMA RX last word empty"); | |
501 | count -= (word_len <= 8) ? 1 : | |
502 | (word_len <= 16) ? 2 : | |
503 | /* word_len <= 32 */ 4; | |
504 | } | |
505 | omap2_mcspi_set_enable(spi, 1); | |
ccdc7bf9 SO |
506 | } |
507 | return count; | |
508 | } | |
509 | ||
ccdc7bf9 SO |
510 | static unsigned |
511 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
512 | { | |
513 | struct omap2_mcspi *mcspi; | |
514 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
515 | unsigned int count, c; | |
516 | u32 l; | |
517 | void __iomem *base = cs->base; | |
518 | void __iomem *tx_reg; | |
519 | void __iomem *rx_reg; | |
520 | void __iomem *chstat_reg; | |
521 | int word_len; | |
522 | ||
523 | mcspi = spi_master_get_devdata(spi->master); | |
524 | count = xfer->len; | |
525 | c = count; | |
526 | word_len = cs->word_len; | |
527 | ||
a41ae1ad | 528 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
529 | |
530 | /* We store the pre-calculated register addresses on stack to speed | |
531 | * up the transfer loop. */ | |
532 | tx_reg = base + OMAP2_MCSPI_TX0; | |
533 | rx_reg = base + OMAP2_MCSPI_RX0; | |
534 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
535 | ||
adef658d MJ |
536 | if (c < (word_len>>3)) |
537 | return 0; | |
538 | ||
ccdc7bf9 SO |
539 | if (word_len <= 8) { |
540 | u8 *rx; | |
541 | const u8 *tx; | |
542 | ||
543 | rx = xfer->rx_buf; | |
544 | tx = xfer->tx_buf; | |
545 | ||
546 | do { | |
feed9bab | 547 | c -= 1; |
ccdc7bf9 SO |
548 | if (tx != NULL) { |
549 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
550 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
551 | dev_err(&spi->dev, "TXS timed out\n"); | |
552 | goto out; | |
553 | } | |
079a176d | 554 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 555 | word_len, *tx); |
ccdc7bf9 SO |
556 | __raw_writel(*tx++, tx_reg); |
557 | } | |
558 | if (rx != NULL) { | |
559 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
560 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
561 | dev_err(&spi->dev, "RXS timed out\n"); | |
562 | goto out; | |
563 | } | |
4743a0f8 RT |
564 | |
565 | if (c == 1 && tx == NULL && | |
566 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
567 | omap2_mcspi_set_enable(spi, 0); | |
568 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 569 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 570 | word_len, *(rx - 1)); |
4743a0f8 RT |
571 | if (mcspi_wait_for_reg_bit(chstat_reg, |
572 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
573 | dev_err(&spi->dev, | |
574 | "RXS timed out\n"); | |
575 | goto out; | |
576 | } | |
577 | c = 0; | |
578 | } else if (c == 0 && tx == NULL) { | |
579 | omap2_mcspi_set_enable(spi, 0); | |
580 | } | |
581 | ||
ccdc7bf9 | 582 | *rx++ = __raw_readl(rx_reg); |
079a176d | 583 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 584 | word_len, *(rx - 1)); |
ccdc7bf9 | 585 | } |
95c5c3ab | 586 | } while (c); |
ccdc7bf9 SO |
587 | } else if (word_len <= 16) { |
588 | u16 *rx; | |
589 | const u16 *tx; | |
590 | ||
591 | rx = xfer->rx_buf; | |
592 | tx = xfer->tx_buf; | |
593 | do { | |
feed9bab | 594 | c -= 2; |
ccdc7bf9 SO |
595 | if (tx != NULL) { |
596 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
597 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
598 | dev_err(&spi->dev, "TXS timed out\n"); | |
599 | goto out; | |
600 | } | |
079a176d | 601 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 602 | word_len, *tx); |
ccdc7bf9 SO |
603 | __raw_writel(*tx++, tx_reg); |
604 | } | |
605 | if (rx != NULL) { | |
606 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
607 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
608 | dev_err(&spi->dev, "RXS timed out\n"); | |
609 | goto out; | |
610 | } | |
4743a0f8 RT |
611 | |
612 | if (c == 2 && tx == NULL && | |
613 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
614 | omap2_mcspi_set_enable(spi, 0); | |
615 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 616 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 617 | word_len, *(rx - 1)); |
4743a0f8 RT |
618 | if (mcspi_wait_for_reg_bit(chstat_reg, |
619 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
620 | dev_err(&spi->dev, | |
621 | "RXS timed out\n"); | |
622 | goto out; | |
623 | } | |
624 | c = 0; | |
625 | } else if (c == 0 && tx == NULL) { | |
626 | omap2_mcspi_set_enable(spi, 0); | |
627 | } | |
628 | ||
ccdc7bf9 | 629 | *rx++ = __raw_readl(rx_reg); |
079a176d | 630 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 631 | word_len, *(rx - 1)); |
ccdc7bf9 | 632 | } |
95c5c3ab | 633 | } while (c >= 2); |
ccdc7bf9 SO |
634 | } else if (word_len <= 32) { |
635 | u32 *rx; | |
636 | const u32 *tx; | |
637 | ||
638 | rx = xfer->rx_buf; | |
639 | tx = xfer->tx_buf; | |
640 | do { | |
feed9bab | 641 | c -= 4; |
ccdc7bf9 SO |
642 | if (tx != NULL) { |
643 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
644 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
645 | dev_err(&spi->dev, "TXS timed out\n"); | |
646 | goto out; | |
647 | } | |
079a176d | 648 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 649 | word_len, *tx); |
ccdc7bf9 SO |
650 | __raw_writel(*tx++, tx_reg); |
651 | } | |
652 | if (rx != NULL) { | |
653 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
654 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
655 | dev_err(&spi->dev, "RXS timed out\n"); | |
656 | goto out; | |
657 | } | |
4743a0f8 RT |
658 | |
659 | if (c == 4 && tx == NULL && | |
660 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
661 | omap2_mcspi_set_enable(spi, 0); | |
662 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 663 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 664 | word_len, *(rx - 1)); |
4743a0f8 RT |
665 | if (mcspi_wait_for_reg_bit(chstat_reg, |
666 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
667 | dev_err(&spi->dev, | |
668 | "RXS timed out\n"); | |
669 | goto out; | |
670 | } | |
671 | c = 0; | |
672 | } else if (c == 0 && tx == NULL) { | |
673 | omap2_mcspi_set_enable(spi, 0); | |
674 | } | |
675 | ||
ccdc7bf9 | 676 | *rx++ = __raw_readl(rx_reg); |
079a176d | 677 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 678 | word_len, *(rx - 1)); |
ccdc7bf9 | 679 | } |
95c5c3ab | 680 | } while (c >= 4); |
ccdc7bf9 SO |
681 | } |
682 | ||
683 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
684 | if (xfer->rx_buf == NULL) { | |
685 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
686 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
687 | dev_err(&spi->dev, "TXS timed out\n"); | |
688 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
689 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
690 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
691 | |
692 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
693 | * otherwise these rx datas will affect the direct following | |
694 | * RX_ONLY transfer. | |
695 | */ | |
696 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
697 | } |
698 | out: | |
4743a0f8 | 699 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
700 | return count - c; |
701 | } | |
702 | ||
57d9c10d HH |
703 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
704 | { | |
705 | u32 div; | |
706 | ||
707 | for (div = 0; div < 15; div++) | |
708 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
709 | return div; | |
710 | ||
711 | return 15; | |
712 | } | |
713 | ||
ccdc7bf9 SO |
714 | /* called only when no transfer is active to this device */ |
715 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
716 | struct spi_transfer *t) | |
717 | { | |
718 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
719 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 720 | struct spi_master *spi_cntrl; |
ccdc7bf9 SO |
721 | u32 l = 0, div = 0; |
722 | u8 word_len = spi->bits_per_word; | |
9bd4517d | 723 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
724 | |
725 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 726 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
727 | |
728 | if (t != NULL && t->bits_per_word) | |
729 | word_len = t->bits_per_word; | |
730 | ||
731 | cs->word_len = word_len; | |
732 | ||
9bd4517d SE |
733 | if (t && t->speed_hz) |
734 | speed_hz = t->speed_hz; | |
735 | ||
57d9c10d HH |
736 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
737 | div = omap2_mcspi_calc_divisor(speed_hz); | |
ccdc7bf9 | 738 | |
a41ae1ad | 739 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
740 | |
741 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
742 | * REVISIT: this controller could support SPI_3WIRE mode. | |
743 | */ | |
744 | l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1); | |
745 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
746 | ||
747 | /* wordlength */ | |
748 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
749 | l |= (word_len - 1) << 7; | |
750 | ||
751 | /* set chipselect polarity; manage with FORCE */ | |
752 | if (!(spi->mode & SPI_CS_HIGH)) | |
753 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
754 | else | |
755 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
756 | ||
757 | /* set clock divisor */ | |
758 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
759 | l |= div << 2; | |
760 | ||
761 | /* set SPI mode 0..3 */ | |
762 | if (spi->mode & SPI_CPOL) | |
763 | l |= OMAP2_MCSPI_CHCONF_POL; | |
764 | else | |
765 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
766 | if (spi->mode & SPI_CPHA) | |
767 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
768 | else | |
769 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
770 | ||
a41ae1ad | 771 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
772 | |
773 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", | |
57d9c10d | 774 | OMAP2_MCSPI_MAX_FREQ >> div, |
ccdc7bf9 SO |
775 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
776 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
ccdc7bf9 SO |
781 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
782 | { | |
783 | struct spi_master *master = spi->master; | |
784 | struct omap2_mcspi *mcspi; | |
785 | struct omap2_mcspi_dma *mcspi_dma; | |
53741ed8 RK |
786 | dma_cap_mask_t mask; |
787 | unsigned sig; | |
ccdc7bf9 SO |
788 | |
789 | mcspi = spi_master_get_devdata(master); | |
790 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
791 | ||
53741ed8 RK |
792 | init_completion(&mcspi_dma->dma_rx_completion); |
793 | init_completion(&mcspi_dma->dma_tx_completion); | |
794 | ||
795 | dma_cap_zero(mask); | |
796 | dma_cap_set(DMA_SLAVE, mask); | |
53741ed8 RK |
797 | sig = mcspi_dma->dma_rx_sync_dev; |
798 | mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
799 | if (!mcspi_dma->dma_rx) { | |
800 | dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n"); | |
ccdc7bf9 SO |
801 | return -EAGAIN; |
802 | } | |
803 | ||
53741ed8 RK |
804 | sig = mcspi_dma->dma_tx_sync_dev; |
805 | mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
806 | if (!mcspi_dma->dma_tx) { | |
807 | dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n"); | |
808 | dma_release_channel(mcspi_dma->dma_rx); | |
809 | mcspi_dma->dma_rx = NULL; | |
ccdc7bf9 SO |
810 | return -EAGAIN; |
811 | } | |
812 | ||
ccdc7bf9 SO |
813 | return 0; |
814 | } | |
815 | ||
ccdc7bf9 SO |
816 | static int omap2_mcspi_setup(struct spi_device *spi) |
817 | { | |
818 | int ret; | |
1bd897f8 BC |
819 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
820 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
821 | struct omap2_mcspi_dma *mcspi_dma; |
822 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
823 | ||
7d077197 | 824 | if (spi->bits_per_word < 4 || spi->bits_per_word > 32) { |
ccdc7bf9 SO |
825 | dev_dbg(&spi->dev, "setup: unsupported %d bit words\n", |
826 | spi->bits_per_word); | |
827 | return -EINVAL; | |
828 | } | |
829 | ||
ccdc7bf9 SO |
830 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
831 | ||
832 | if (!cs) { | |
10aa5a35 | 833 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
834 | if (!cs) |
835 | return -ENOMEM; | |
836 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 837 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
a41ae1ad | 838 | cs->chconf0 = 0; |
ccdc7bf9 | 839 | spi->controller_state = cs; |
89c05372 | 840 | /* Link this to context save list */ |
1bd897f8 | 841 | list_add_tail(&cs->node, &ctx->cs); |
ccdc7bf9 SO |
842 | } |
843 | ||
8c7494a5 | 844 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 SO |
845 | ret = omap2_mcspi_request_dma(spi); |
846 | if (ret < 0) | |
847 | return ret; | |
848 | } | |
849 | ||
1f1a4384 G |
850 | ret = omap2_mcspi_enable_clocks(mcspi); |
851 | if (ret < 0) | |
852 | return ret; | |
a41ae1ad | 853 | |
86eeb6fe | 854 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
a41ae1ad | 855 | omap2_mcspi_disable_clocks(mcspi); |
ccdc7bf9 SO |
856 | |
857 | return ret; | |
858 | } | |
859 | ||
860 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
861 | { | |
862 | struct omap2_mcspi *mcspi; | |
863 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 864 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
865 | |
866 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 867 | |
5e774943 SE |
868 | if (spi->controller_state) { |
869 | /* Unlink controller state from context save list */ | |
870 | cs = spi->controller_state; | |
871 | list_del(&cs->node); | |
89c05372 | 872 | |
10aa5a35 | 873 | kfree(cs); |
5e774943 | 874 | } |
ccdc7bf9 | 875 | |
99f1a43f SE |
876 | if (spi->chip_select < spi->master->num_chipselect) { |
877 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
878 | ||
53741ed8 RK |
879 | if (mcspi_dma->dma_rx) { |
880 | dma_release_channel(mcspi_dma->dma_rx); | |
881 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 882 | } |
53741ed8 RK |
883 | if (mcspi_dma->dma_tx) { |
884 | dma_release_channel(mcspi_dma->dma_tx); | |
885 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 886 | } |
ccdc7bf9 SO |
887 | } |
888 | } | |
889 | ||
5fda88f5 | 890 | static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) |
ccdc7bf9 | 891 | { |
ccdc7bf9 SO |
892 | |
893 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 894 | * -- although this controller would gladly |
ccdc7bf9 SO |
895 | * arbitrate among multiple channels. This corresponds to "single |
896 | * channel" master mode. As a side effect, we need to manage the | |
897 | * chipselect with the FORCE bit ... CS != channel enable. | |
898 | */ | |
ccdc7bf9 | 899 | |
5fda88f5 S |
900 | struct spi_device *spi; |
901 | struct spi_transfer *t = NULL; | |
902 | int cs_active = 0; | |
903 | struct omap2_mcspi_cs *cs; | |
904 | struct omap2_mcspi_device_config *cd; | |
905 | int par_override = 0; | |
906 | int status = 0; | |
907 | u32 chconf; | |
ccdc7bf9 | 908 | |
5fda88f5 S |
909 | spi = m->spi; |
910 | cs = spi->controller_state; | |
911 | cd = spi->controller_data; | |
ccdc7bf9 | 912 | |
5fda88f5 S |
913 | omap2_mcspi_set_enable(spi, 1); |
914 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
915 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { | |
916 | status = -EINVAL; | |
917 | break; | |
918 | } | |
919 | if (par_override || t->speed_hz || t->bits_per_word) { | |
920 | par_override = 1; | |
921 | status = omap2_mcspi_setup_transfer(spi, t); | |
922 | if (status < 0) | |
923 | break; | |
924 | if (!t->speed_hz && !t->bits_per_word) | |
925 | par_override = 0; | |
926 | } | |
4743a0f8 | 927 | |
5fda88f5 S |
928 | if (!cs_active) { |
929 | omap2_mcspi_force_cs(spi, 1); | |
930 | cs_active = 1; | |
931 | } | |
4743a0f8 | 932 | |
5fda88f5 S |
933 | chconf = mcspi_cached_chconf0(spi); |
934 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
935 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
ccdc7bf9 | 936 | |
5fda88f5 S |
937 | if (t->tx_buf == NULL) |
938 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
939 | else if (t->rx_buf == NULL) | |
940 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
ccdc7bf9 | 941 | |
5fda88f5 S |
942 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
943 | /* Turbo mode is for more than one word */ | |
944 | if (t->len > ((cs->word_len + 7) >> 3)) | |
945 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
946 | } | |
ccdc7bf9 | 947 | |
5fda88f5 | 948 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 949 | |
5fda88f5 S |
950 | if (t->len) { |
951 | unsigned count; | |
952 | ||
953 | /* RX_ONLY mode needs dummy data in TX reg */ | |
954 | if (t->tx_buf == NULL) | |
955 | __raw_writel(0, cs->base | |
956 | + OMAP2_MCSPI_TX0); | |
ccdc7bf9 | 957 | |
5fda88f5 S |
958 | if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) |
959 | count = omap2_mcspi_txrx_dma(spi, t); | |
960 | else | |
961 | count = omap2_mcspi_txrx_pio(spi, t); | |
962 | m->actual_length += count; | |
ccdc7bf9 | 963 | |
5fda88f5 S |
964 | if (count != t->len) { |
965 | status = -EIO; | |
966 | break; | |
ccdc7bf9 SO |
967 | } |
968 | } | |
969 | ||
5fda88f5 S |
970 | if (t->delay_usecs) |
971 | udelay(t->delay_usecs); | |
ccdc7bf9 | 972 | |
5fda88f5 S |
973 | /* ignore the "leave it on after last xfer" hint */ |
974 | if (t->cs_change) { | |
ccdc7bf9 | 975 | omap2_mcspi_force_cs(spi, 0); |
5fda88f5 S |
976 | cs_active = 0; |
977 | } | |
978 | } | |
979 | /* Restore defaults if they were overriden */ | |
980 | if (par_override) { | |
981 | par_override = 0; | |
982 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
983 | } | |
ccdc7bf9 | 984 | |
5fda88f5 S |
985 | if (cs_active) |
986 | omap2_mcspi_force_cs(spi, 0); | |
ccdc7bf9 | 987 | |
5fda88f5 | 988 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 989 | |
5fda88f5 | 990 | m->status = status; |
1f1a4384 | 991 | |
ccdc7bf9 SO |
992 | } |
993 | ||
5fda88f5 S |
994 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, |
995 | struct spi_message *m) | |
ccdc7bf9 SO |
996 | { |
997 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 SO |
998 | struct spi_transfer *t; |
999 | ||
5fda88f5 | 1000 | mcspi = spi_master_get_devdata(master); |
ccdc7bf9 SO |
1001 | m->actual_length = 0; |
1002 | m->status = 0; | |
1003 | ||
1004 | /* reject invalid messages and transfers */ | |
5fda88f5 | 1005 | if (list_empty(&m->transfers)) |
ccdc7bf9 SO |
1006 | return -EINVAL; |
1007 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
1008 | const void *tx_buf = t->tx_buf; | |
1009 | void *rx_buf = t->rx_buf; | |
1010 | unsigned len = t->len; | |
1011 | ||
1012 | if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ | |
1013 | || (len && !(rx_buf || tx_buf)) | |
1014 | || (t->bits_per_word && | |
1015 | ( t->bits_per_word < 4 | |
1016 | || t->bits_per_word > 32))) { | |
5fda88f5 | 1017 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
ccdc7bf9 SO |
1018 | t->speed_hz, |
1019 | len, | |
1020 | tx_buf ? "tx" : "", | |
1021 | rx_buf ? "rx" : "", | |
1022 | t->bits_per_word); | |
1023 | return -EINVAL; | |
1024 | } | |
57d9c10d | 1025 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { |
5fda88f5 | 1026 | dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", |
57d9c10d HH |
1027 | t->speed_hz, |
1028 | OMAP2_MCSPI_MAX_FREQ >> 15); | |
ccdc7bf9 SO |
1029 | return -EINVAL; |
1030 | } | |
1031 | ||
1032 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) | |
1033 | continue; | |
1034 | ||
ccdc7bf9 | 1035 | if (tx_buf != NULL) { |
5fda88f5 | 1036 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, |
ccdc7bf9 | 1037 | len, DMA_TO_DEVICE); |
5fda88f5 S |
1038 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { |
1039 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1040 | 'T', len); |
1041 | return -EINVAL; | |
1042 | } | |
1043 | } | |
1044 | if (rx_buf != NULL) { | |
5fda88f5 | 1045 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, |
ccdc7bf9 | 1046 | DMA_FROM_DEVICE); |
5fda88f5 S |
1047 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { |
1048 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1049 | 'R', len); |
1050 | if (tx_buf != NULL) | |
5fda88f5 | 1051 | dma_unmap_single(mcspi->dev, t->tx_dma, |
ccdc7bf9 SO |
1052 | len, DMA_TO_DEVICE); |
1053 | return -EINVAL; | |
1054 | } | |
1055 | } | |
1056 | } | |
1057 | ||
5fda88f5 S |
1058 | omap2_mcspi_work(mcspi, m); |
1059 | spi_finalize_current_message(master); | |
ccdc7bf9 SO |
1060 | return 0; |
1061 | } | |
1062 | ||
24ab3275 | 1063 | static int __devinit omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1064 | { |
1065 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1066 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1067 | int ret = 0; |
ccdc7bf9 | 1068 | |
1f1a4384 G |
1069 | ret = omap2_mcspi_enable_clocks(mcspi); |
1070 | if (ret < 0) | |
1071 | return ret; | |
ddb22195 | 1072 | |
39f8052d S |
1073 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
1074 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); | |
1075 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; | |
ccdc7bf9 SO |
1076 | |
1077 | omap2_mcspi_set_master_mode(master); | |
a41ae1ad | 1078 | omap2_mcspi_disable_clocks(mcspi); |
ccdc7bf9 SO |
1079 | return 0; |
1080 | } | |
1081 | ||
1f1a4384 G |
1082 | static int omap_mcspi_runtime_resume(struct device *dev) |
1083 | { | |
1084 | struct omap2_mcspi *mcspi; | |
1085 | struct spi_master *master; | |
1086 | ||
1087 | master = dev_get_drvdata(dev); | |
1088 | mcspi = spi_master_get_devdata(master); | |
1089 | omap2_mcspi_restore_ctx(mcspi); | |
1090 | ||
1091 | return 0; | |
1092 | } | |
1093 | ||
d5a80031 BC |
1094 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1095 | .regs_offset = 0, | |
1096 | }; | |
1097 | ||
1098 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1099 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1100 | }; | |
1101 | ||
1102 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1103 | { | |
1104 | .compatible = "ti,omap2-mcspi", | |
1105 | .data = &omap2_pdata, | |
1106 | }, | |
1107 | { | |
1108 | .compatible = "ti,omap4-mcspi", | |
1109 | .data = &omap4_pdata, | |
1110 | }, | |
1111 | { }, | |
1112 | }; | |
1113 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1114 | |
7d6b6d83 | 1115 | static int __devinit omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1116 | { |
1117 | struct spi_master *master; | |
d5a80031 | 1118 | struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1119 | struct omap2_mcspi *mcspi; |
1120 | struct resource *r; | |
1121 | int status = 0, i; | |
d5a80031 BC |
1122 | u32 regs_offset = 0; |
1123 | static int bus_num = 1; | |
1124 | struct device_node *node = pdev->dev.of_node; | |
1125 | const struct of_device_id *match; | |
ccdc7bf9 SO |
1126 | |
1127 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1128 | if (master == NULL) { | |
1129 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1130 | return -ENOMEM; | |
1131 | } | |
1132 | ||
e7db06b5 DB |
1133 | /* the spi->mode bits understood by this driver: */ |
1134 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
1135 | ||
ccdc7bf9 | 1136 | master->setup = omap2_mcspi_setup; |
5fda88f5 S |
1137 | master->prepare_transfer_hardware = omap2_prepare_transfer; |
1138 | master->unprepare_transfer_hardware = omap2_unprepare_transfer; | |
1139 | master->transfer_one_message = omap2_mcspi_transfer_one_message; | |
ccdc7bf9 | 1140 | master->cleanup = omap2_mcspi_cleanup; |
d5a80031 BC |
1141 | master->dev.of_node = node; |
1142 | ||
1143 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); | |
1144 | if (match) { | |
1145 | u32 num_cs = 1; /* default number of chipselect */ | |
1146 | pdata = match->data; | |
1147 | ||
1148 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1149 | master->num_chipselect = num_cs; | |
1150 | master->bus_num = bus_num++; | |
1151 | } else { | |
1152 | pdata = pdev->dev.platform_data; | |
1153 | master->num_chipselect = pdata->num_cs; | |
1154 | if (pdev->id != -1) | |
1155 | master->bus_num = pdev->id; | |
1156 | } | |
1157 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 SO |
1158 | |
1159 | dev_set_drvdata(&pdev->dev, master); | |
1160 | ||
1161 | mcspi = spi_master_get_devdata(master); | |
1162 | mcspi->master = master; | |
1163 | ||
1164 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1165 | if (r == NULL) { | |
1166 | status = -ENODEV; | |
39f1b565 | 1167 | goto free_master; |
ccdc7bf9 | 1168 | } |
1458d160 | 1169 | |
d5a80031 BC |
1170 | r->start += regs_offset; |
1171 | r->end += regs_offset; | |
1458d160 | 1172 | mcspi->phys = r->start; |
ccdc7bf9 | 1173 | |
1a77b127 | 1174 | mcspi->base = devm_request_and_ioremap(&pdev->dev, r); |
55c381e4 RK |
1175 | if (!mcspi->base) { |
1176 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); | |
1177 | status = -ENOMEM; | |
1a77b127 | 1178 | goto free_master; |
55c381e4 | 1179 | } |
ccdc7bf9 | 1180 | |
1f1a4384 | 1181 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1182 | |
1bd897f8 | 1183 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1184 | |
ccdc7bf9 SO |
1185 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
1186 | sizeof(struct omap2_mcspi_dma), | |
1187 | GFP_KERNEL); | |
1188 | ||
1189 | if (mcspi->dma_channels == NULL) | |
1a77b127 | 1190 | goto free_master; |
ccdc7bf9 | 1191 | |
1a5d8190 C |
1192 | for (i = 0; i < master->num_chipselect; i++) { |
1193 | char dma_ch_name[14]; | |
1194 | struct resource *dma_res; | |
1195 | ||
1196 | sprintf(dma_ch_name, "rx%d", i); | |
1197 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | |
1198 | dma_ch_name); | |
1199 | if (!dma_res) { | |
1200 | dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); | |
1201 | status = -ENODEV; | |
1202 | break; | |
1203 | } | |
1204 | ||
1a5d8190 C |
1205 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; |
1206 | sprintf(dma_ch_name, "tx%d", i); | |
1207 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | |
1208 | dma_ch_name); | |
1209 | if (!dma_res) { | |
1210 | dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); | |
1211 | status = -ENODEV; | |
1212 | break; | |
1213 | } | |
1214 | ||
1a5d8190 | 1215 | mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; |
ccdc7bf9 SO |
1216 | } |
1217 | ||
39f1b565 S |
1218 | if (status < 0) |
1219 | goto dma_chnl_free; | |
1220 | ||
27b5284c S |
1221 | pm_runtime_use_autosuspend(&pdev->dev); |
1222 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1223 | pm_runtime_enable(&pdev->dev); |
1224 | ||
1225 | if (status || omap2_mcspi_master_setup(mcspi) < 0) | |
39f1b565 | 1226 | goto disable_pm; |
ccdc7bf9 SO |
1227 | |
1228 | status = spi_register_master(master); | |
1229 | if (status < 0) | |
37a2d84a | 1230 | goto disable_pm; |
ccdc7bf9 SO |
1231 | |
1232 | return status; | |
1233 | ||
39f1b565 | 1234 | disable_pm: |
751c925c | 1235 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1236 | dma_chnl_free: |
1f1a4384 | 1237 | kfree(mcspi->dma_channels); |
39f1b565 | 1238 | free_master: |
37a2d84a | 1239 | spi_master_put(master); |
39f1b565 | 1240 | platform_set_drvdata(pdev, NULL); |
ccdc7bf9 SO |
1241 | return status; |
1242 | } | |
1243 | ||
7d6b6d83 | 1244 | static int __devexit omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 SO |
1245 | { |
1246 | struct spi_master *master; | |
1247 | struct omap2_mcspi *mcspi; | |
1248 | struct omap2_mcspi_dma *dma_channels; | |
ccdc7bf9 SO |
1249 | |
1250 | master = dev_get_drvdata(&pdev->dev); | |
1251 | mcspi = spi_master_get_devdata(master); | |
1252 | dma_channels = mcspi->dma_channels; | |
1253 | ||
1f1a4384 | 1254 | omap2_mcspi_disable_clocks(mcspi); |
751c925c | 1255 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 SO |
1256 | |
1257 | spi_unregister_master(master); | |
1258 | kfree(dma_channels); | |
39f1b565 | 1259 | platform_set_drvdata(pdev, NULL); |
ccdc7bf9 SO |
1260 | |
1261 | return 0; | |
1262 | } | |
1263 | ||
7e38c3c4 KS |
1264 | /* work with hotplug and coldplug */ |
1265 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1266 | ||
42ce7fd6 GC |
1267 | #ifdef CONFIG_SUSPEND |
1268 | /* | |
1269 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1270 | * unactive state when driver was suspend, then force it to unactive state at | |
1271 | * wake up. | |
1272 | */ | |
1273 | static int omap2_mcspi_resume(struct device *dev) | |
1274 | { | |
1275 | struct spi_master *master = dev_get_drvdata(dev); | |
1276 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1bd897f8 BC |
1277 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1278 | struct omap2_mcspi_cs *cs; | |
42ce7fd6 GC |
1279 | |
1280 | omap2_mcspi_enable_clocks(mcspi); | |
1bd897f8 | 1281 | list_for_each_entry(cs, &ctx->cs, node) { |
42ce7fd6 | 1282 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
42ce7fd6 GC |
1283 | /* |
1284 | * We need to toggle CS state for OMAP take this | |
1285 | * change in account. | |
1286 | */ | |
1287 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1); | |
1288 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); | |
1289 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0); | |
1290 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); | |
1291 | } | |
1292 | } | |
1293 | omap2_mcspi_disable_clocks(mcspi); | |
1294 | return 0; | |
1295 | } | |
1296 | #else | |
1297 | #define omap2_mcspi_resume NULL | |
1298 | #endif | |
1299 | ||
1300 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1301 | .resume = omap2_mcspi_resume, | |
1f1a4384 | 1302 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1303 | }; |
1304 | ||
ccdc7bf9 SO |
1305 | static struct platform_driver omap2_mcspi_driver = { |
1306 | .driver = { | |
1307 | .name = "omap2_mcspi", | |
1308 | .owner = THIS_MODULE, | |
d5a80031 BC |
1309 | .pm = &omap2_mcspi_pm_ops, |
1310 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1311 | }, |
7d6b6d83 FB |
1312 | .probe = omap2_mcspi_probe, |
1313 | .remove = __devexit_p(omap2_mcspi_remove), | |
ccdc7bf9 SO |
1314 | }; |
1315 | ||
9fdca9df | 1316 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1317 | MODULE_LICENSE("GPL"); |