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Merge tag 'v3.10.108' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
1da177e4
LT		 107static void qla2x00_free_device(scsi_qla_host_t *);
108
7e47e5ca 109int ql2xfdmienable=1;
f2019cb1 110module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 111MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 112 "Enables FDMI registrations. "
113 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 114
3c290d0b 115int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 116module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
117MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 118 "Maximum queue depth to set for each LUN. "
119 "Default is 32.");
df7baa50 120
9e522cd8
AE		 121int ql2xenabledif = 2;
122module_param(ql2xenabledif, int, S_IRUGO);
bad75002
AE		 123MODULE_PARM_DESC(ql2xenabledif,
124 " Enable T10-CRC-DIF "
8cb2049c
AE		 125 " Default is 0 - No DIF Support. 1 - Enable it"
126 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 127
8cb2049c 128int ql2xenablehba_err_chk = 2;
bad75002
AE		 129module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
130MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 131 " Enable T10-CRC-DIF Error isolation by HBA:\n"
132 " Default is 1.\n"
133 " 0 -- Error isolation disabled\n"
134 " 1 -- Error isolation enabled only for DIX Type 0\n"
135 " 2 -- Error isolation enabled for all Types\n");
bad75002 136
e5896bd5 137int ql2xiidmaenable=1;
f2019cb1 138module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 139MODULE_PARM_DESC(ql2xiidmaenable,
140 "Enables iIDMA settings "
141 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
142
73208dfd 143int ql2xmaxqueues = 1;
f2019cb1 144module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 145MODULE_PARM_DESC(ql2xmaxqueues,
146 "Enables MQ settings "
ae68230c
JP		 147 "Default is 1 for single queue. Set it to number "
148 "of queues in MQ mode.");
68ca949c
AC		 149
150int ql2xmultique_tag;
f2019cb1 151module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 152MODULE_PARM_DESC(ql2xmultique_tag,
153 "Enables CPU affinity settings for the driver "
154 "Default is 0 for no affinity of request and response IO. "
155 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 156
157int ql2xfwloadbin;
86e45bf6 158module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 159MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 160 "Option to specify location from which to load ISP firmware:.\n"
161 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 162 " interface.\n"
163 " 1 -- load firmware from flash.\n"
164 " 0 -- use default semantics.\n");
165
ae97c91e 166int ql2xetsenable;
f2019cb1 167module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 168MODULE_PARM_DESC(ql2xetsenable,
169 "Enables firmware ETS burst."
170 "Default is 0 - skip ETS enablement.");
171
6907869d 172int ql2xdbwr = 1;
86e45bf6 173module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 174MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 175 "Option to specify scheme for request queue posting.\n"
176 " 0 -- Regular doorbell.\n"
177 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 178
f4c496c1 179int ql2xtargetreset = 1;
f2019cb1 180module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 181MODULE_PARM_DESC(ql2xtargetreset,
182 "Enable target reset."
183 "Default is 1 - use hw defaults.");
184
4da26e16 185int ql2xgffidenable;
f2019cb1 186module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 187MODULE_PARM_DESC(ql2xgffidenable,
188 "Enables GFF_ID checks of port type. "
189 "Default is 0 - Do not use GFF_ID information.");
a9083016 190
3822263e 191int ql2xasynctmfenable;
f2019cb1 192module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 193MODULE_PARM_DESC(ql2xasynctmfenable,
194 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
195 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 196
197int ql2xdontresethba;
86e45bf6 198module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 199MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 200 "Option to specify reset behaviour.\n"
201 " 0 (Default) -- Reset on failure.\n"
202 " 1 -- Do not reset on failure.\n");
ed0de87c 203
82515920
AV		 204uint ql2xmaxlun = MAX_LUNS;
205module_param(ql2xmaxlun, uint, S_IRUGO);
206MODULE_PARM_DESC(ql2xmaxlun,
207 "Defines the maximum LU number to register with the SCSI "
208 "midlayer. Default is 65535.");
209
08de2844
GM		 210int ql2xmdcapmask = 0x1F;
211module_param(ql2xmdcapmask, int, S_IRUGO);
212MODULE_PARM_DESC(ql2xmdcapmask,
213 "Set the Minidump driver capture mask level. "
6e96fa7b 214 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 215
3aadff35 216int ql2xmdenable = 1;
08de2844
GM		 217module_param(ql2xmdenable, int, S_IRUGO);
218MODULE_PARM_DESC(ql2xmdenable,
219 "Enable/disable MiniDump. "
3aadff35
GM		 220 "0 - MiniDump disabled. "
221 "1 (Default) - MiniDump enabled.");
08de2844 222
1da177e4 223/*
fa2a1ce5 224 * SCSI host template entry points
1da177e4
LT		 225 */
226static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 227static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 228static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
229static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 230static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 231static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 232static int qla2xxx_eh_abort(struct scsi_cmnd *);
233static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 234static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 235static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
236static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 237
e881a172 238static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 239static int qla2x00_change_queue_type(struct scsi_device *, int);
240
a5326f86 241struct scsi_host_template qla2xxx_driver_template = {
1da177e4 242 .module = THIS_MODULE,
cb63067a 243 .name = QLA2XXX_DRIVER_NAME,
a5326f86 244 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 245
246 .eh_abort_handler = qla2xxx_eh_abort,
247 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 248 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 249 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
250 .eh_host_reset_handler = qla2xxx_eh_host_reset,
251
252 .slave_configure = qla2xxx_slave_configure,
253
254 .slave_alloc = qla2xxx_slave_alloc,
255 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 256 .scan_finished = qla2xxx_scan_finished,
257 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 258 .change_queue_depth = qla2x00_change_queue_depth,
259 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 260 .this_id = -1,
261 .cmd_per_lun = 3,
262 .use_clustering = ENABLE_CLUSTERING,
263 .sg_tablesize = SG_ALL,
264
265 .max_sectors = 0xFFFF,
afb046e2 266 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 267
268 .supported_mode = MODE_INITIATOR,
fca29703
AV		 269};
270
1da177e4 271static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 272struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 273
1da177e4
LT		 274/* TODO Convert to inlines
275 *
276 * Timer routines
277 */
1da177e4 278
2c3dfe3f 279__inline__ void
e315cd28 280qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 281{
e315cd28
AC		 282 init_timer(&vha->timer);
283 vha->timer.expires = jiffies + interval * HZ;
284 vha->timer.data = (unsigned long)vha;
285 vha->timer.function = (void (*)(unsigned long))func;
286 add_timer(&vha->timer);
287 vha->timer_active = 1;
1da177e4
LT		 288}
289
290static inline void
e315cd28 291qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 292{
a9083016 293 /* Currently used for 82XX only. */
7c3df132
SK		 294 if (vha->device_flags & DFLG_DEV_FAILED) {
295 ql_dbg(ql_dbg_timer, vha, 0x600d,
296 "Device in a failed state, returning.\n");
a9083016 297 return;
7c3df132 298 }
a9083016 299
e315cd28 300 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 301}
302
a824ebb3 303static __inline__ void
e315cd28 304qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 305{
e315cd28
AC		 306 del_timer_sync(&vha->timer);
307 vha->timer_active = 0;
1da177e4
LT		 308}
309
1da177e4
LT		 310static int qla2x00_do_dpc(void *data);
311
312static void qla2x00_rst_aen(scsi_qla_host_t *);
313
73208dfd
AC		 314static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
315 struct req_que **, struct rsp_que **);
e30d1756 316static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 317static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 318
1da177e4 319/* -------------------------------------------------------------------------- */
9a347ff4
CD		 320static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
321 struct rsp_que *rsp)
73208dfd 322{
7c3df132 323 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 324 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 325 GFP_KERNEL);
326 if (!ha->req_q_map) {
7c3df132
SK		 327 ql_log(ql_log_fatal, vha, 0x003b,
328 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 329 goto fail_req_map;
330 }
331
2afa19a9 332 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 333 GFP_KERNEL);
334 if (!ha->rsp_q_map) {
7c3df132
SK		 335 ql_log(ql_log_fatal, vha, 0x003c,
336 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 337 goto fail_rsp_map;
338 }
9a347ff4
CD		 339 /*
340 * Make sure we record at least the request and response queue zero in
341 * case we need to free them if part of the probe fails.
342 */
343 ha->rsp_q_map[0] = rsp;
344 ha->req_q_map[0] = req;
73208dfd
AC		 345 set_bit(0, ha->rsp_qid_map);
346 set_bit(0, ha->req_qid_map);
347 return 1;
348
349fail_rsp_map:
350 kfree(ha->req_q_map);
351 ha->req_q_map = NULL;
352fail_req_map:
353 return -ENOMEM;
354}
355
2afa19a9 356static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 357{
8ae6d9c7
GM		 358 if (IS_QLAFX00(ha)) {
359 if (req && req->ring_fx00)
360 dma_free_coherent(&ha->pdev->dev,
361 (req->length_fx00 + 1) * sizeof(request_t),
362 req->ring_fx00, req->dma_fx00);
363 } else if (req && req->ring)
73208dfd
AC		 364 dma_free_coherent(&ha->pdev->dev,
365 (req->length + 1) * sizeof(request_t),
366 req->ring, req->dma);
367
8d93f550
CD		 368 if (req)
369 kfree(req->outstanding_cmds);
370
73208dfd
AC		 371 kfree(req);
372 req = NULL;
373}
374
2afa19a9
AC		 375static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
376{
8ae6d9c7
GM		 377 if (IS_QLAFX00(ha)) {
378 if (rsp && rsp->ring)
379 dma_free_coherent(&ha->pdev->dev,
380 (rsp->length_fx00 + 1) * sizeof(request_t),
381 rsp->ring_fx00, rsp->dma_fx00);
382 } else if (rsp && rsp->ring) {
2afa19a9
AC		 383 dma_free_coherent(&ha->pdev->dev,
384 (rsp->length + 1) * sizeof(response_t),
385 rsp->ring, rsp->dma);
8ae6d9c7 386 }
2afa19a9
AC		 387 kfree(rsp);
388 rsp = NULL;
389}
390
73208dfd
AC		 391static void qla2x00_free_queues(struct qla_hw_data *ha)
392{
393 struct req_que *req;
394 struct rsp_que *rsp;
395 int cnt;
396
2afa19a9 397 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 398 req = ha->req_q_map[cnt];
2afa19a9 399 qla2x00_free_req_que(ha, req);
73208dfd 400 }
73208dfd
AC		 401 kfree(ha->req_q_map);
402 ha->req_q_map = NULL;
2afa19a9
AC		 403
404 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
405 rsp = ha->rsp_q_map[cnt];
406 qla2x00_free_rsp_que(ha, rsp);
407 }
408 kfree(ha->rsp_q_map);
409 ha->rsp_q_map = NULL;
73208dfd
AC		 410}
411
68ca949c
AC		 412static int qla25xx_setup_mode(struct scsi_qla_host *vha)
413{
414 uint16_t options = 0;
415 int ques, req, ret;
416 struct qla_hw_data *ha = vha->hw;
417
7163ea81 418 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 419 ql_log(ql_log_warn, vha, 0x00d8,
420 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 421 goto fail;
422 }
68ca949c 423 if (ql2xmultique_tag) {
68ca949c
AC		 424 /* create a request queue for IO */
425 options |= BIT_7;
426 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
427 QLA_DEFAULT_QUE_QOS);
428 if (!req) {
7c3df132
SK		 429 ql_log(ql_log_warn, vha, 0x00e0,
430 "Failed to create request queue.\n");
68ca949c
AC		 431 goto fail;
432 }
278274d5 433 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 434 vha->req = ha->req_q_map[req];
435 options |= BIT_1;
436 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
437 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
438 if (!ret) {
7c3df132
SK		 439 ql_log(ql_log_warn, vha, 0x00e8,
440 "Failed to create response queue.\n");
68ca949c
AC		 441 goto fail2;
442 }
443 }
7163ea81 444 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 445 ql_dbg(ql_dbg_multiq, vha, 0xc007,
446 "CPU affinity mode enalbed, "
447 "no. of response queues:%d no. of request queues:%d.\n",
448 ha->max_rsp_queues, ha->max_req_queues);
449 ql_dbg(ql_dbg_init, vha, 0x00e9,
450 "CPU affinity mode enalbed, "
451 "no. of response queues:%d no. of request queues:%d.\n",
452 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 453 }
454 return 0;
455fail2:
456 qla25xx_delete_queues(vha);
7163ea81
AC		 457 destroy_workqueue(ha->wq);
458 ha->wq = NULL;
0cd33fcf 459 vha->req = ha->req_q_map[0];
68ca949c
AC		 460fail:
461 ha->mqenable = 0;
7163ea81
AC		 462 kfree(ha->req_q_map);
463 kfree(ha->rsp_q_map);
464 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 465 return 1;
466}
467
1da177e4 468static char *
e315cd28 469qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 470{
e315cd28 471 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 472 static char *pci_bus_modes[] = {
473 "33", "66", "100", "133",
474 };
475 uint16_t pci_bus;
476
477 strcpy(str, "PCI");
478 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
479 if (pci_bus) {
480 strcat(str, "-X (");
481 strcat(str, pci_bus_modes[pci_bus]);
482 } else {
483 pci_bus = (ha->pci_attr & BIT_8) >> 8;
484 strcat(str, " (");
485 strcat(str, pci_bus_modes[pci_bus]);
486 }
487 strcat(str, " MHz)");
488
489 return (str);
490}
491
fca29703 492static char *
e315cd28 493qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 494{
495 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 496 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 497 uint32_t pci_bus;
498 int pcie_reg;
499
e67f1321 500 pcie_reg = pci_pcie_cap(ha->pdev);
fca29703
AV		 501 if (pcie_reg) {
502 char lwstr[6];
503 uint16_t pcie_lstat, lspeed, lwidth;
504
e67f1321 505 pcie_reg += PCI_EXP_LNKCAP;
fca29703
AV		 506 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
507 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
508 lwidth = (pcie_lstat &
509 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
510
511 strcpy(str, "PCIe (");
49300af7
SK		 512 switch (lspeed) {
513 case 1:
c87a0d8c 514 strcat(str, "2.5GT/s ");
49300af7
SK		 515 break;
516 case 2:
c87a0d8c 517 strcat(str, "5.0GT/s ");
49300af7
SK		 518 break;
519 case 3:
520 strcat(str, "8.0GT/s ");
521 break;
522 default:
fca29703 523 strcat(str, "<unknown> ");
49300af7
SK		 524 break;
525 }
fca29703
AV		 526 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
527 strcat(str, lwstr);
528
529 return str;
530 }
531
532 strcpy(str, "PCI");
533 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
534 if (pci_bus == 0 || pci_bus == 8) {
535 strcat(str, " (");
536 strcat(str, pci_bus_modes[pci_bus >> 3]);
537 } else {
538 strcat(str, "-X ");
539 if (pci_bus & BIT_2)
540 strcat(str, "Mode 2");
541 else
542 strcat(str, "Mode 1");
543 strcat(str, " (");
544 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
545 }
546 strcat(str, " MHz)");
547
548 return str;
549}
550
e5f82ab8 551static char *
e315cd28 552qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 553{
554 char un_str[10];
e315cd28 555 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 556
1da177e4
LT		 557 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
558 ha->fw_minor_version,
559 ha->fw_subminor_version);
560
561 if (ha->fw_attributes & BIT_9) {
562 strcat(str, "FLX");
563 return (str);
564 }
565
566 switch (ha->fw_attributes & 0xFF) {
567 case 0x7:
568 strcat(str, "EF");
569 break;
570 case 0x17:
571 strcat(str, "TP");
572 break;
573 case 0x37:
574 strcat(str, "IP");
575 break;
576 case 0x77:
577 strcat(str, "VI");
578 break;
579 default:
580 sprintf(un_str, "(%x)", ha->fw_attributes);
581 strcat(str, un_str);
582 break;
583 }
584 if (ha->fw_attributes & 0x100)
585 strcat(str, "X");
586
587 return (str);
588}
589
e5f82ab8 590static char *
e315cd28 591qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 592{
e315cd28 593 struct qla_hw_data *ha = vha->hw;
f0883ac6 594
3a03eb79
AV		 595 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
596 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 597 return str;
fca29703
AV		 598}
599
9ba56b95
GM		 600void
601qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 602{
9ba56b95
GM		 603 srb_t *sp = (srb_t *)ptr;
604 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
605 struct qla_hw_data *ha = sp->fcport->vha->hw;
606 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 607
9ba56b95
GM		 608 if (sp->flags & SRB_DMA_VALID) {
609 scsi_dma_unmap(cmd);
610 sp->flags &= ~SRB_DMA_VALID;
7c3df132 611 }
fca29703 612
9ba56b95
GM		 613 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
614 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
615 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
616 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
617 }
618
619 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
620 /* List assured to be having elements */
621 qla2x00_clean_dsd_pool(ha, sp);
622 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
623 }
624
625 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
626 dma_pool_free(ha->dl_dma_pool, ctx,
627 ((struct crc_context *)ctx)->crc_ctx_dma);
628 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
629 }
630
631 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
632 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 633
9ba56b95
GM		 634 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
635 ctx1->fcp_cmnd_dma);
636 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
637 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
638 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
639 mempool_free(ctx1, ha->ctx_mempool);
640 ctx1 = NULL;
641 }
642
643 CMD_SP(cmd) = NULL;
b00ee7d7 644 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 645}
646
14b06808 647static void
9ba56b95
GM		 648qla2x00_sp_compl(void *data, void *ptr, int res)
649{
650 struct qla_hw_data *ha = (struct qla_hw_data *)data;
651 srb_t *sp = (srb_t *)ptr;
652 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
653
654 cmd->result = res;
655
656 if (atomic_read(&sp->ref_count) == 0) {
657 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
658 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
659 sp, GET_CMD_SP(sp));
660 if (ql2xextended_error_logging & ql_dbg_io)
661 BUG();
662 return;
663 }
664 if (!atomic_dec_and_test(&sp->ref_count))
665 return;
666
667 qla2x00_sp_free_dma(ha, sp);
668 cmd->scsi_done(cmd);
fca29703
AV		 669}
670
8ae6d9c7
GM		 671/* If we are SP1 here, we need to still take and release the host_lock as SP1
672 * does not have the changes necessary to avoid taking host->host_lock.
673 */
1da177e4 674static int
f5e3e40b 675qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 676{
134ae078 677 scsi_qla_host_t *vha = shost_priv(host);
fca29703 678 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 679 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 680 struct qla_hw_data *ha = vha->hw;
681 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 682 srb_t *sp;
683 int rval;
684
85880801 685 if (ha->flags.eeh_busy) {
7c3df132 686 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 687 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 688 "PCI Channel IO permanent failure, exiting "
689 "cmd=%p.\n", cmd);
b9b12f73 690 cmd->result = DID_NO_CONNECT << 16;
7c3df132 691 } else {
5f28d2d7 692 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 693 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 694 cmd->result = DID_REQUEUE << 16;
7c3df132 695 }
14e660e6
SJ		 696 goto qc24_fail_command;
697 }
698
19a7b4ae
JSEC		 699 rval = fc_remote_port_chkready(rport);
700 if (rval) {
701 cmd->result = rval;
5f28d2d7 702 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 703 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
704 cmd, rval);
fca29703
AV		 705 goto qc24_fail_command;
706 }
707
bad75002
AE		 708 if (!vha->flags.difdix_supported &&
709 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 710 ql_dbg(ql_dbg_io, vha, 0x3004,
711 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
712 cmd);
bad75002
AE		 713 cmd->result = DID_NO_CONNECT << 16;
714 goto qc24_fail_command;
715 }
aa651be8
CD		 716
717 if (!fcport) {
718 cmd->result = DID_NO_CONNECT << 16;
719 goto qc24_fail_command;
720 }
721
fca29703
AV		 722 if (atomic_read(&fcport->state) != FCS_ONLINE) {
723 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 724 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 725 ql_dbg(ql_dbg_io, vha, 0x3005,
726 "Returning DNC, fcport_state=%d loop_state=%d.\n",
727 atomic_read(&fcport->state),
728 atomic_read(&base_vha->loop_state));
fca29703
AV		 729 cmd->result = DID_NO_CONNECT << 16;
730 goto qc24_fail_command;
731 }
7b594131 732 goto qc24_target_busy;
fca29703
AV		 733 }
734
b00ee7d7 735 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
3c290d0b
CD		 736 if (!sp) {
737 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
f5e3e40b 738 goto qc24_host_busy;
3c290d0b 739 }
fca29703 740
9ba56b95
GM		 741 sp->u.scmd.cmd = cmd;
742 sp->type = SRB_SCSI_CMD;
743 atomic_set(&sp->ref_count, 1);
744 CMD_SP(cmd) = (void *)sp;
745 sp->free = qla2x00_sp_free_dma;
746 sp->done = qla2x00_sp_compl;
747
e315cd28 748 rval = ha->isp_ops->start_scsi(sp);
7c3df132 749 if (rval != QLA_SUCCESS) {
53016ed3 750 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 751 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
3c290d0b 752 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
fca29703 753 goto qc24_host_busy_free_sp;
7c3df132 754 }
fca29703 755
fca29703
AV		 756 return 0;
757
758qc24_host_busy_free_sp:
9ba56b95 759 qla2x00_sp_free_dma(ha, sp);
fca29703 760
f5e3e40b 761qc24_host_busy:
fca29703
AV		 762 return SCSI_MLQUEUE_HOST_BUSY;
763
7b594131
MC		 764qc24_target_busy:
765 return SCSI_MLQUEUE_TARGET_BUSY;
766
fca29703 767qc24_fail_command:
f5e3e40b 768 cmd->scsi_done(cmd);
fca29703
AV		 769
770 return 0;
771}
772
1da177e4
LT		 773/*
774 * qla2x00_eh_wait_on_command
775 * Waits for the command to be returned by the Firmware for some
776 * max time.
777 *
778 * Input:
1da177e4 779 * cmd = Scsi Command to wait on.
1da177e4
LT		 780 *
781 * Return:
782 * Not Found : 0
783 * Found : 1
784 */
785static int
e315cd28 786qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 787{
fe74c71f
AV		 788#define ABORT_POLLING_PERIOD 1000
789#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 790 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 791 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
792 struct qla_hw_data *ha = vha->hw;
f4f051eb 793 int ret = QLA_SUCCESS;
1da177e4 794
85880801 795 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 796 ql_dbg(ql_dbg_taskm, vha, 0x8005,
797 "Return:eh_wait.\n");
85880801
AV		 798 return ret;
799 }
800
d970432c 801 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 802 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 803 }
804 if (CMD_SP(cmd))
805 ret = QLA_FUNCTION_FAILED;
1da177e4 806
f4f051eb 807 return ret;
1da177e4
LT		 808}
809
810/*
811 * qla2x00_wait_for_hba_online
fa2a1ce5 812 * Wait till the HBA is online after going through
1da177e4
LT		 813 * <= MAX_RETRIES_OF_ISP_ABORT or
814 * finally HBA is disabled ie marked offline
815 *
816 * Input:
817 * ha - pointer to host adapter structure
fa2a1ce5
AV		 818 *
819 * Note:
1da177e4
LT		 820 * Does context switching-Release SPIN_LOCK
821 * (if any) before calling this routine.
822 *
823 * Return:
824 * Success (Adapter is online) : 0
825 * Failed (Adapter is offline/disabled) : 1
826 */
854165f4 827int
e315cd28 828qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 829{
fca29703
AV		 830 int return_status;
831 unsigned long wait_online;
e315cd28
AC		 832 struct qla_hw_data *ha = vha->hw;
833 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 834
fa2a1ce5 835 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 836 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
837 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
838 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
839 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 840
841 msleep(1000);
842 }
e315cd28 843 if (base_vha->flags.online)
fa2a1ce5 844 return_status = QLA_SUCCESS;
1da177e4
LT		 845 else
846 return_status = QLA_FUNCTION_FAILED;
847
1da177e4
LT		 848 return (return_status);
849}
850
86fbee86
LC		 851/*
852 * qla2x00_wait_for_reset_ready
853 * Wait till the HBA is online after going through
854 * <= MAX_RETRIES_OF_ISP_ABORT or
855 * finally HBA is disabled ie marked offline or flash
856 * operations are in progress.
857 *
858 * Input:
859 * ha - pointer to host adapter structure
860 *
861 * Note:
862 * Does context switching-Release SPIN_LOCK
863 * (if any) before calling this routine.
864 *
865 * Return:
866 * Success (Adapter is online/no flash ops) : 0
867 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
868 */
3dbe756a 869static int
86fbee86
LC		 870qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
871{
872 int return_status;
873 unsigned long wait_online;
874 struct qla_hw_data *ha = vha->hw;
875 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
876
877 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
878 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
879 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
880 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
881 ha->optrom_state != QLA_SWAITING ||
882 ha->dpc_active) && time_before(jiffies, wait_online))
883 msleep(1000);
884
885 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
886 return_status = QLA_SUCCESS;
887 else
888 return_status = QLA_FUNCTION_FAILED;
889
7c3df132
SK		 890 ql_dbg(ql_dbg_taskm, vha, 0x8019,
891 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 892
893 return return_status;
894}
895
2533cf67
LC		 896int
897qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
898{
899 int return_status;
900 unsigned long wait_reset;
901 struct qla_hw_data *ha = vha->hw;
902 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
903
904 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
905 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
906 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
907 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
908 ha->dpc_active) && time_before(jiffies, wait_reset)) {
909
910 msleep(1000);
911
912 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
913 ha->flags.chip_reset_done)
914 break;
915 }
916 if (ha->flags.chip_reset_done)
917 return_status = QLA_SUCCESS;
918 else
919 return_status = QLA_FUNCTION_FAILED;
920
921 return return_status;
922}
923
083a469d
GM		 924static void
925sp_get(struct srb *sp)
926{
927 atomic_inc(&sp->ref_count);
928}
929
1da177e4
LT		 930/**************************************************************************
931* qla2xxx_eh_abort
932*
933* Description:
934* The abort function will abort the specified command.
935*
936* Input:
937* cmd = Linux SCSI command packet to be aborted.
938*
939* Returns:
940* Either SUCCESS or FAILED.
941*
942* Note:
2ea00202 943* Only return FAILED if command not returned by firmware.
1da177e4 944**************************************************************************/
e5f82ab8 945static int
1da177e4
LT		 946qla2xxx_eh_abort(struct scsi_cmnd *cmd)
947{
e315cd28 948 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 949 srb_t *sp;
4e98d3b8 950 int ret;
f4f051eb 951 unsigned int id, lun;
18e144d3 952 unsigned long flags;
2ea00202 953 int wait = 0;
e315cd28 954 struct qla_hw_data *ha = vha->hw;
1da177e4 955
f4f051eb 956 if (!CMD_SP(cmd))
2ea00202 957 return SUCCESS;
1da177e4 958
4e98d3b8
AV		 959 ret = fc_block_scsi_eh(cmd);
960 if (ret != 0)
961 return ret;
962 ret = SUCCESS;
963
f4f051eb
AV		 964 id = cmd->device->id;
965 lun = cmd->device->lun;
1da177e4 966
e315cd28 967 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 968 sp = (srb_t *) CMD_SP(cmd);
969 if (!sp) {
970 spin_unlock_irqrestore(&ha->hardware_lock, flags);
971 return SUCCESS;
972 }
1da177e4 973
7c3df132 974 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 975 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
976 vha->host_no, id, lun, sp, cmd);
17d98630 977
170babc3
MC		 978 /* Get a reference to the sp and drop the lock.*/
979 sp_get(sp);
083a469d 980
e315cd28 981 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 982 if (ha->isp_ops->abort_command(sp)) {
a55aac79 983 ret = FAILED;
7c3df132 984 ql_dbg(ql_dbg_taskm, vha, 0x8003,
cfb0919c 985 "Abort command mbx failed cmd=%p.\n", cmd);
170babc3 986 } else {
7c3df132 987 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 988 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 989 wait = 1;
990 }
75942064
SK		 991
992 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 993 sp->done(ha, sp, 0);
75942064 994 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 995
bc91ade9
CD		 996 /* Did the command return during mailbox execution? */
997 if (ret == FAILED && !CMD_SP(cmd))
998 ret = SUCCESS;
999
f4f051eb 1000 /* Wait for the command to be returned. */
2ea00202 1001 if (wait) {
e315cd28 1002 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1003 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1004 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1005 ret = FAILED;
f4f051eb 1006 }
1da177e4 1007 }
1da177e4 1008
7c3df132 1009 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 1010 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
1011 vha->host_no, id, lun, wait, ret);
1da177e4 1012
f4f051eb
AV		 1013 return ret;
1014}
1da177e4 1015
4d78c973 1016int
e315cd28 1017qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 1018 unsigned int l, enum nexus_wait_type type)
f4f051eb 1019{
17d98630 1020 int cnt, match, status;
18e144d3 1021 unsigned long flags;
e315cd28 1022 struct qla_hw_data *ha = vha->hw;
73208dfd 1023 struct req_que *req;
4d78c973 1024 srb_t *sp;
9ba56b95 1025 struct scsi_cmnd *cmd;
1da177e4 1026
523ec773 1027 status = QLA_SUCCESS;
17d98630 1028
e315cd28 1029 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1030 req = vha->req;
17d98630 1031 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1032 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1033 sp = req->outstanding_cmds[cnt];
1034 if (!sp)
523ec773 1035 continue;
9ba56b95 1036 if (sp->type != SRB_SCSI_CMD)
cf53b069 1037 continue;
17d98630
AC		 1038 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1039 continue;
1040 match = 0;
9ba56b95 1041 cmd = GET_CMD_SP(sp);
17d98630
AC		 1042 switch (type) {
1043 case WAIT_HOST:
1044 match = 1;
1045 break;
1046 case WAIT_TARGET:
9ba56b95 1047 match = cmd->device->id == t;
17d98630
AC		 1048 break;
1049 case WAIT_LUN:
9ba56b95
GM		 1050 match = (cmd->device->id == t &&
1051 cmd->device->lun == l);
17d98630 1052 break;
73208dfd 1053 }
17d98630
AC		 1054 if (!match)
1055 continue;
1056
1057 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1058 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1059 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1060 }
e315cd28 1061 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1062
1063 return status;
1da177e4
LT		 1064}
1065
523ec773
AV		 1066static char *reset_errors[] = {
1067 "HBA not online",
1068 "HBA not ready",
1069 "Task management failed",
1070 "Waiting for command completions",
1071};
1da177e4 1072
e5f82ab8 1073static int
523ec773 1074__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1075 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1076{
e315cd28 1077 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1078 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1079 int err;
1da177e4 1080
7c3df132 1081 if (!fcport) {
523ec773 1082 return FAILED;
7c3df132 1083 }
1da177e4 1084
4e98d3b8
AV		 1085 err = fc_block_scsi_eh(cmd);
1086 if (err != 0)
1087 return err;
1088
7c3df132 1089 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1090 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1091 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1092
523ec773 1093 err = 0;
7c3df132
SK		 1094 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1095 ql_log(ql_log_warn, vha, 0x800a,
1096 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1097 goto eh_reset_failed;
7c3df132 1098 }
523ec773 1099 err = 2;
2afa19a9 1100 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1101 != QLA_SUCCESS) {
1102 ql_log(ql_log_warn, vha, 0x800c,
1103 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1104 goto eh_reset_failed;
7c3df132 1105 }
523ec773 1106 err = 3;
e315cd28 1107 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1108 cmd->device->lun, type) != QLA_SUCCESS) {
1109 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1110 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1111 goto eh_reset_failed;
7c3df132 1112 }
523ec773 1113
7c3df132 1114 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1115 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1116 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1117
1118 return SUCCESS;
1119
4d78c973 1120eh_reset_failed:
7c3df132 1121 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1122 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1123 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1124 cmd);
523ec773
AV		 1125 return FAILED;
1126}
1da177e4 1127
523ec773
AV		 1128static int
1129qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1130{
e315cd28
AC		 1131 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1132 struct qla_hw_data *ha = vha->hw;
1da177e4 1133
523ec773
AV		 1134 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1135 ha->isp_ops->lun_reset);
1da177e4
LT		 1136}
1137
1da177e4 1138static int
523ec773 1139qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1140{
e315cd28
AC		 1141 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1142 struct qla_hw_data *ha = vha->hw;
1da177e4 1143
523ec773
AV		 1144 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1145 ha->isp_ops->target_reset);
1da177e4
LT		 1146}
1147
1da177e4
LT		 1148/**************************************************************************
1149* qla2xxx_eh_bus_reset
1150*
1151* Description:
1152* The bus reset function will reset the bus and abort any executing
1153* commands.
1154*
1155* Input:
1156* cmd = Linux SCSI command packet of the command that cause the
1157* bus reset.
1158*
1159* Returns:
1160* SUCCESS/FAILURE (defined as macro in scsi.h).
1161*
1162**************************************************************************/
e5f82ab8 1163static int
1da177e4
LT		 1164qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1165{
e315cd28 1166 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1167 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1168 int ret = FAILED;
f4f051eb 1169 unsigned int id, lun;
f4f051eb 1170
f4f051eb
AV		 1171 id = cmd->device->id;
1172 lun = cmd->device->lun;
1da177e4 1173
7c3df132 1174 if (!fcport) {
f4f051eb 1175 return ret;
7c3df132 1176 }
1da177e4 1177
4e98d3b8
AV		 1178 ret = fc_block_scsi_eh(cmd);
1179 if (ret != 0)
1180 return ret;
1181 ret = FAILED;
1182
7c3df132 1183 ql_log(ql_log_info, vha, 0x8012,
46270afe 1184 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1185
e315cd28 1186 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1187 ql_log(ql_log_fatal, vha, 0x8013,
1188 "Wait for hba online failed board disabled.\n");
f4f051eb 1189 goto eh_bus_reset_done;
1da177e4
LT		 1190 }
1191
ad537689
SK		 1192 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1193 ret = SUCCESS;
1194
f4f051eb
AV		 1195 if (ret == FAILED)
1196 goto eh_bus_reset_done;
1da177e4 1197
9a41a62b 1198 /* Flush outstanding commands. */
4d78c973 1199 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1200 QLA_SUCCESS) {
1201 ql_log(ql_log_warn, vha, 0x8014,
1202 "Wait for pending commands failed.\n");
9a41a62b 1203 ret = FAILED;
7c3df132 1204 }
1da177e4 1205
f4f051eb 1206eh_bus_reset_done:
7c3df132 1207 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c 1208 "BUS RESET %s nexus=%ld:%d:%d.\n",
d6a03581 1209 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1210
f4f051eb 1211 return ret;
1da177e4
LT		 1212}
1213
1214/**************************************************************************
1215* qla2xxx_eh_host_reset
1216*
1217* Description:
1218* The reset function will reset the Adapter.
1219*
1220* Input:
1221* cmd = Linux SCSI command packet of the command that cause the
1222* adapter reset.
1223*
1224* Returns:
1225* Either SUCCESS or FAILED.
1226*
1227* Note:
1228**************************************************************************/
e5f82ab8 1229static int
1da177e4
LT		 1230qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1231{
e315cd28 1232 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1233 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1234 int ret = FAILED;
f4f051eb 1235 unsigned int id, lun;
e315cd28 1236 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1237
f4f051eb
AV		 1238 id = cmd->device->id;
1239 lun = cmd->device->lun;
f4f051eb 1240
7c3df132 1241 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1242 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1243
86fbee86 1244 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1245 goto eh_host_reset_lock;
1da177e4 1246
e315cd28
AC		 1247 if (vha != base_vha) {
1248 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1249 goto eh_host_reset_lock;
e315cd28 1250 } else {
a9083016
GM		 1251 if (IS_QLA82XX(vha->hw)) {
1252 if (!qla82xx_fcoe_ctx_reset(vha)) {
1253 /* Ctx reset success */
1254 ret = SUCCESS;
1255 goto eh_host_reset_lock;
1256 }
1257 /* fall thru if ctx reset failed */
1258 }
68ca949c
AC		 1259 if (ha->wq)
1260 flush_workqueue(ha->wq);
1261
e315cd28 1262 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1263 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1264 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1265 /* failed. schedule dpc to try */
1266 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1267
7c3df132
SK		 1268 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1269 ql_log(ql_log_warn, vha, 0x802a,
1270 "wait for hba online failed.\n");
e315cd28 1271 goto eh_host_reset_lock;
7c3df132 1272 }
e315cd28
AC		 1273 }
1274 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1275 }
1da177e4 1276
e315cd28 1277 /* Waiting for command to be returned to OS.*/
4d78c973 1278 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1279 QLA_SUCCESS)
f4f051eb 1280 ret = SUCCESS;
1da177e4 1281
f4f051eb 1282eh_host_reset_lock:
cfb0919c
CD		 1283 ql_log(ql_log_info, vha, 0x8017,
1284 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1285 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1286
f4f051eb
AV		 1287 return ret;
1288}
1da177e4
LT		 1289
1290/*
1291* qla2x00_loop_reset
1292* Issue loop reset.
1293*
1294* Input:
1295* ha = adapter block pointer.
1296*
1297* Returns:
1298* 0 = success
1299*/
a4722cf2 1300int
e315cd28 1301qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1302{
0c8c39af 1303 int ret;
bdf79621 1304 struct fc_port *fcport;
e315cd28 1305 struct qla_hw_data *ha = vha->hw;
1da177e4 1306
f4c496c1 1307 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1308 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1309 if (fcport->port_type != FCT_TARGET)
1310 continue;
1311
1312 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1313 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1314 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1315 "Bus Reset failed: Target Reset=%d "
1316 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1317 }
1318 }
1319 }
1320
8ae6d9c7
GM		 1321 if (IS_QLAFX00(ha))
1322 return QLA_SUCCESS;
1323
6246b8a1 1324 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1325 atomic_set(&vha->loop_state, LOOP_DOWN);
1326 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1327 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1328 ret = qla2x00_full_login_lip(vha);
0c8c39af 1329 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1330 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1331 "full_login_lip=%d.\n", ret);
749af3d5 1332 }
0c8c39af
AV		 1333 }
1334
0d6e61bc 1335 if (ha->flags.enable_lip_reset) {
e315cd28 1336 ret = qla2x00_lip_reset(vha);
ad537689 1337 if (ret != QLA_SUCCESS)
7c3df132
SK		 1338 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1339 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1340 }
1341
1da177e4 1342 /* Issue marker command only when we are going to start the I/O */
e315cd28 1343 vha->marker_needed = 1;
1da177e4 1344
0c8c39af 1345 return QLA_SUCCESS;
1da177e4
LT		 1346}
1347
df4bf0bb 1348void
e315cd28 1349qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1350{
73208dfd 1351 int que, cnt;
df4bf0bb
AV		 1352 unsigned long flags;
1353 srb_t *sp;
e315cd28 1354 struct qla_hw_data *ha = vha->hw;
73208dfd 1355 struct req_que *req;
df4bf0bb
AV		 1356
1357 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1358 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1359 req = ha->req_q_map[que];
73208dfd
AC		 1360 if (!req)
1361 continue;
8d93f550
CD		 1362 if (!req->outstanding_cmds)
1363 continue;
1364 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1365 sp = req->outstanding_cmds[cnt];
e612d465 1366 if (sp) {
73208dfd 1367 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1368 sp->done(vha, sp, res);
73208dfd 1369 }
df4bf0bb
AV		 1370 }
1371 }
1372 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1373}
1374
f4f051eb
AV		 1375static int
1376qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1377{
bdf79621 1378 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1379
19a7b4ae 1380 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1381 return -ENXIO;
bdf79621 1382
19a7b4ae 1383 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1384
f4f051eb
AV		 1385 return 0;
1386}
1da177e4 1387
f4f051eb
AV		 1388static int
1389qla2xxx_slave_configure(struct scsi_device *sdev)
1390{
e315cd28 1391 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1392 struct req_que *req = vha->req;
8482e118 1393
9e522cd8
AE		 1394 if (IS_T10_PI_CAPABLE(vha->hw))
1395 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1396
f4f051eb 1397 if (sdev->tagged_supported)
73208dfd 1398 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1399 else
73208dfd 1400 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb
AV		 1401 return 0;
1402}
1da177e4 1403
f4f051eb
AV		 1404static void
1405qla2xxx_slave_destroy(struct scsi_device *sdev)
1406{
1407 sdev->hostdata = NULL;
1da177e4
LT		 1408}
1409
c45dd305
GM		 1410static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1411{
1412 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1413
1414 if (!scsi_track_queue_full(sdev, qdepth))
1415 return;
1416
7c3df132 1417 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1418 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1419 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1420}
1421
1422static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1423{
1424 fc_port_t *fcport = sdev->hostdata;
1425 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1426 struct req_que *req = NULL;
1427
1428 req = vha->req;
1429 if (!req)
1430 return;
1431
1432 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1433 return;
1434
1435 if (sdev->ordered_tags)
1436 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1437 else
1438 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1439
7c3df132 1440 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1441 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1442 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1443}
1444
ce7e4af7 1445static int
e881a172 1446qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1447{
c45dd305
GM		 1448 switch (reason) {
1449 case SCSI_QDEPTH_DEFAULT:
1450 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1451 break;
1452 case SCSI_QDEPTH_QFULL:
1453 qla2x00_handle_queue_full(sdev, qdepth);
1454 break;
1455 case SCSI_QDEPTH_RAMP_UP:
1456 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1457 break;
1458 default:
08002af2 1459 return -EOPNOTSUPP;
c45dd305 1460 }
e881a172 1461
ce7e4af7
AV		 1462 return sdev->queue_depth;
1463}
1464
1465static int
1466qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1467{
1468 if (sdev->tagged_supported) {
1469 scsi_set_tag_type(sdev, tag_type);
1470 if (tag_type)
1471 scsi_activate_tcq(sdev, sdev->queue_depth);
1472 else
1473 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1474 } else
1475 tag_type = 0;
1476
1477 return tag_type;
1478}
1479
3c290d0b
CD		 1480static void
1481qla2x00_host_ramp_down_queuedepth(scsi_qla_host_t *vha)
1482{
1483 scsi_qla_host_t *vp;
1484 struct Scsi_Host *shost;
1485 struct scsi_device *sdev;
1486 struct qla_hw_data *ha = vha->hw;
1487 unsigned long flags;
1488
1489 ha->host_last_rampdown_time = jiffies;
1490
1491 if (ha->cfg_lun_q_depth <= vha->host->cmd_per_lun)
1492 return;
1493
1494 if ((ha->cfg_lun_q_depth / 2) < vha->host->cmd_per_lun)
1495 ha->cfg_lun_q_depth = vha->host->cmd_per_lun;
1496 else
1497 ha->cfg_lun_q_depth = ha->cfg_lun_q_depth / 2;
1498
1499 /*
1500 * Geometrically ramp down the queue depth for all devices on this
1501 * adapter
1502 */
1503 spin_lock_irqsave(&ha->vport_slock, flags);
1504 list_for_each_entry(vp, &ha->vp_list, list) {
1505 shost = vp->host;
1506 shost_for_each_device(sdev, shost) {
1507 if (sdev->queue_depth > shost->cmd_per_lun) {
1508 if (sdev->queue_depth < ha->cfg_lun_q_depth)
1509 continue;
1510 ql_log(ql_log_warn, vp, 0x3031,
1511 "%ld:%d:%d: Ramping down queue depth to %d",
1512 vp->host_no, sdev->id, sdev->lun,
1513 ha->cfg_lun_q_depth);
1514 qla2x00_change_queue_depth(sdev,
1515 ha->cfg_lun_q_depth, SCSI_QDEPTH_DEFAULT);
1516 }
1517 }
1518 }
1519 spin_unlock_irqrestore(&ha->vport_slock, flags);
1520
1521 return;
1522}
1523
1524static void
1525qla2x00_host_ramp_up_queuedepth(scsi_qla_host_t *vha)
1526{
1527 scsi_qla_host_t *vp;
1528 struct Scsi_Host *shost;
1529 struct scsi_device *sdev;
1530 struct qla_hw_data *ha = vha->hw;
1531 unsigned long flags;
1532
1533 ha->host_last_rampup_time = jiffies;
1534 ha->cfg_lun_q_depth++;
1535
1536 /*
1537 * Linearly ramp up the queue depth for all devices on this
1538 * adapter
1539 */
1540 spin_lock_irqsave(&ha->vport_slock, flags);
1541 list_for_each_entry(vp, &ha->vp_list, list) {
1542 shost = vp->host;
1543 shost_for_each_device(sdev, shost) {
1544 if (sdev->queue_depth > ha->cfg_lun_q_depth)
1545 continue;
1546 qla2x00_change_queue_depth(sdev, ha->cfg_lun_q_depth,
1547 SCSI_QDEPTH_RAMP_UP);
1548 }
1549 }
1550 spin_unlock_irqrestore(&ha->vport_slock, flags);
1551
1552 return;
1553}
1554
1da177e4
LT		 1555/**
1556 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1557 * @ha: HA context
1558 *
1559 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1560 * supported addressing method.
1561 */
1562static void
53303c42 1563qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1564{
7524f9b9 1565 /* Assume a 32bit DMA mask. */
1da177e4 1566 ha->flags.enable_64bit_addressing = 0;
1da177e4 1567
6a35528a 1568 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1569 /* Any upper-dword bits set? */
1570 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1571 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1572 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1573 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1574 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1575 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1576 return;
1da177e4 1577 }
1da177e4 1578 }
7524f9b9 1579
284901a9
YH		 1580 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1581 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1582}
1583
fd34f556 1584static void
e315cd28 1585qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1586{
1587 unsigned long flags = 0;
1588 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1589
1590 spin_lock_irqsave(&ha->hardware_lock, flags);
1591 ha->interrupts_on = 1;
1592 /* enable risc and host interrupts */
1593 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1594 RD_REG_WORD(&reg->ictrl);
1595 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1596
1597}
1598
1599static void
e315cd28 1600qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1601{
1602 unsigned long flags = 0;
1603 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1604
1605 spin_lock_irqsave(&ha->hardware_lock, flags);
1606 ha->interrupts_on = 0;
1607 /* disable risc and host interrupts */
1608 WRT_REG_WORD(&reg->ictrl, 0);
1609 RD_REG_WORD(&reg->ictrl);
1610 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1611}
1612
1613static void
e315cd28 1614qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1615{
1616 unsigned long flags = 0;
1617 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1618
1619 spin_lock_irqsave(&ha->hardware_lock, flags);
1620 ha->interrupts_on = 1;
1621 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1622 RD_REG_DWORD(&reg->ictrl);
1623 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1624}
1625
1626static void
e315cd28 1627qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1628{
1629 unsigned long flags = 0;
1630 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1631
124f85e6
AV		 1632 if (IS_NOPOLLING_TYPE(ha))
1633 return;
fd34f556
AV		 1634 spin_lock_irqsave(&ha->hardware_lock, flags);
1635 ha->interrupts_on = 0;
1636 WRT_REG_DWORD(&reg->ictrl, 0);
1637 RD_REG_DWORD(&reg->ictrl);
1638 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1639}
1640
706f457d
GM		 1641static int
1642qla2x00_iospace_config(struct qla_hw_data *ha)
1643{
1644 resource_size_t pio;
1645 uint16_t msix;
1646 int cpus;
1647
706f457d
GM		 1648 if (pci_request_selected_regions(ha->pdev, ha->bars,
1649 QLA2XXX_DRIVER_NAME)) {
1650 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1651 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1652 pci_name(ha->pdev));
1653 goto iospace_error_exit;
1654 }
1655 if (!(ha->bars & 1))
1656 goto skip_pio;
1657
1658 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1659 pio = pci_resource_start(ha->pdev, 0);
1660 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1661 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1662 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1663 "Invalid pci I/O region size (%s).\n",
1664 pci_name(ha->pdev));
1665 pio = 0;
1666 }
1667 } else {
1668 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1669 "Region #0 no a PIO resource (%s).\n",
1670 pci_name(ha->pdev));
1671 pio = 0;
1672 }
1673 ha->pio_address = pio;
1674 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1675 "PIO address=%llu.\n",
1676 (unsigned long long)ha->pio_address);
1677
1678skip_pio:
1679 /* Use MMIO operations for all accesses. */
1680 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1681 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1682 "Region #1 not an MMIO resource (%s), aborting.\n",
1683 pci_name(ha->pdev));
1684 goto iospace_error_exit;
1685 }
1686 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1687 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1688 "Invalid PCI mem region size (%s), aborting.\n",
1689 pci_name(ha->pdev));
1690 goto iospace_error_exit;
1691 }
1692
1693 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1694 if (!ha->iobase) {
1695 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1696 "Cannot remap MMIO (%s), aborting.\n",
1697 pci_name(ha->pdev));
1698 goto iospace_error_exit;
1699 }
1700
1701 /* Determine queue resources */
1702 ha->max_req_queues = ha->max_rsp_queues = 1;
1703 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1704 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1705 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1706 goto mqiobase_exit;
1707
1708 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1709 pci_resource_len(ha->pdev, 3));
1710 if (ha->mqiobase) {
1711 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1712 "MQIO Base=%p.\n", ha->mqiobase);
1713 /* Read MSIX vector size of the board */
1714 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1715 ha->msix_count = msix;
1716 /* Max queues are bounded by available msix vectors */
1717 /* queue 0 uses two msix vectors */
1718 if (ql2xmultique_tag) {
1719 cpus = num_online_cpus();
1720 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1721 (cpus + 1) : (ha->msix_count - 1);
1722 ha->max_req_queues = 2;
1723 } else if (ql2xmaxqueues > 1) {
1724 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1725 QLA_MQ_SIZE : ql2xmaxqueues;
1726 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1727 "QoS mode set, max no of request queues:%d.\n",
1728 ha->max_req_queues);
1729 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1730 "QoS mode set, max no of request queues:%d.\n",
1731 ha->max_req_queues);
1732 }
1733 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1734 "MSI-X vector count: %d.\n", msix);
1735 } else
1736 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1737 "BAR 3 not enabled.\n");
1738
1739mqiobase_exit:
1740 ha->msix_count = ha->max_rsp_queues + 1;
1741 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1742 "MSIX Count:%d.\n", ha->msix_count);
1743 return (0);
1744
1745iospace_error_exit:
1746 return (-ENOMEM);
1747}
1748
1749
6246b8a1
GM		 1750static int
1751qla83xx_iospace_config(struct qla_hw_data *ha)
1752{
1753 uint16_t msix;
1754 int cpus;
1755
1756 if (pci_request_selected_regions(ha->pdev, ha->bars,
1757 QLA2XXX_DRIVER_NAME)) {
1758 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1759 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1760 pci_name(ha->pdev));
1761
1762 goto iospace_error_exit;
1763 }
1764
1765 /* Use MMIO operations for all accesses. */
1766 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1767 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1768 "Invalid pci I/O region size (%s).\n",
1769 pci_name(ha->pdev));
1770 goto iospace_error_exit;
1771 }
1772 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1773 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1774 "Invalid PCI mem region size (%s), aborting\n",
1775 pci_name(ha->pdev));
1776 goto iospace_error_exit;
1777 }
1778
1779 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1780 if (!ha->iobase) {
1781 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1782 "Cannot remap MMIO (%s), aborting.\n",
1783 pci_name(ha->pdev));
1784 goto iospace_error_exit;
1785 }
1786
1787 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1788 /* 83XX 26XX always use MQ type access for queues
1789 * - mbar 2, a.k.a region 4 */
1790 ha->max_req_queues = ha->max_rsp_queues = 1;
1791 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1792 pci_resource_len(ha->pdev, 4));
1793
1794 if (!ha->mqiobase) {
1795 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1796 "BAR2/region4 not enabled\n");
1797 goto mqiobase_exit;
1798 }
1799
1800 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1801 pci_resource_len(ha->pdev, 2));
1802 if (ha->msixbase) {
1803 /* Read MSIX vector size of the board */
1804 pci_read_config_word(ha->pdev,
1805 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1806 ha->msix_count = msix;
1807 /* Max queues are bounded by available msix vectors */
1808 /* queue 0 uses two msix vectors */
1809 if (ql2xmultique_tag) {
1810 cpus = num_online_cpus();
1811 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1812 (cpus + 1) : (ha->msix_count - 1);
1813 ha->max_req_queues = 2;
1814 } else if (ql2xmaxqueues > 1) {
1815 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1816 QLA_MQ_SIZE : ql2xmaxqueues;
1817 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1818 "QoS mode set, max no of request queues:%d.\n",
1819 ha->max_req_queues);
1820 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1821 "QoS mode set, max no of request queues:%d.\n",
1822 ha->max_req_queues);
1823 }
1824 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1825 "MSI-X vector count: %d.\n", msix);
1826 } else
1827 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1828 "BAR 1 not enabled.\n");
1829
1830mqiobase_exit:
1831 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1832
1833 qlt_83xx_iospace_config(ha);
1834
6246b8a1
GM		 1835 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1836 "MSIX Count:%d.\n", ha->msix_count);
1837 return 0;
1838
1839iospace_error_exit:
1840 return -ENOMEM;
1841}
1842
fd34f556
AV		 1843static struct isp_operations qla2100_isp_ops = {
1844 .pci_config = qla2100_pci_config,
1845 .reset_chip = qla2x00_reset_chip,
1846 .chip_diag = qla2x00_chip_diag,
1847 .config_rings = qla2x00_config_rings,
1848 .reset_adapter = qla2x00_reset_adapter,
1849 .nvram_config = qla2x00_nvram_config,
1850 .update_fw_options = qla2x00_update_fw_options,
1851 .load_risc = qla2x00_load_risc,
1852 .pci_info_str = qla2x00_pci_info_str,
1853 .fw_version_str = qla2x00_fw_version_str,
1854 .intr_handler = qla2100_intr_handler,
1855 .enable_intrs = qla2x00_enable_intrs,
1856 .disable_intrs = qla2x00_disable_intrs,
1857 .abort_command = qla2x00_abort_command,
523ec773
AV		 1858 .target_reset = qla2x00_abort_target,
1859 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1860 .fabric_login = qla2x00_login_fabric,
1861 .fabric_logout = qla2x00_fabric_logout,
1862 .calc_req_entries = qla2x00_calc_iocbs_32,
1863 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1864 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1865 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1866 .read_nvram = qla2x00_read_nvram_data,
1867 .write_nvram = qla2x00_write_nvram_data,
1868 .fw_dump = qla2100_fw_dump,
1869 .beacon_on = NULL,
1870 .beacon_off = NULL,
1871 .beacon_blink = NULL,
1872 .read_optrom = qla2x00_read_optrom_data,
1873 .write_optrom = qla2x00_write_optrom_data,
1874 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1875 .start_scsi = qla2x00_start_scsi,
a9083016 1876 .abort_isp = qla2x00_abort_isp,
706f457d 1877 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1878 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1879};
1880
1881static struct isp_operations qla2300_isp_ops = {
1882 .pci_config = qla2300_pci_config,
1883 .reset_chip = qla2x00_reset_chip,
1884 .chip_diag = qla2x00_chip_diag,
1885 .config_rings = qla2x00_config_rings,
1886 .reset_adapter = qla2x00_reset_adapter,
1887 .nvram_config = qla2x00_nvram_config,
1888 .update_fw_options = qla2x00_update_fw_options,
1889 .load_risc = qla2x00_load_risc,
1890 .pci_info_str = qla2x00_pci_info_str,
1891 .fw_version_str = qla2x00_fw_version_str,
1892 .intr_handler = qla2300_intr_handler,
1893 .enable_intrs = qla2x00_enable_intrs,
1894 .disable_intrs = qla2x00_disable_intrs,
1895 .abort_command = qla2x00_abort_command,
523ec773
AV		 1896 .target_reset = qla2x00_abort_target,
1897 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1898 .fabric_login = qla2x00_login_fabric,
1899 .fabric_logout = qla2x00_fabric_logout,
1900 .calc_req_entries = qla2x00_calc_iocbs_32,
1901 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1902 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1903 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1904 .read_nvram = qla2x00_read_nvram_data,
1905 .write_nvram = qla2x00_write_nvram_data,
1906 .fw_dump = qla2300_fw_dump,
1907 .beacon_on = qla2x00_beacon_on,
1908 .beacon_off = qla2x00_beacon_off,
1909 .beacon_blink = qla2x00_beacon_blink,
1910 .read_optrom = qla2x00_read_optrom_data,
1911 .write_optrom = qla2x00_write_optrom_data,
1912 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1913 .start_scsi = qla2x00_start_scsi,
a9083016 1914 .abort_isp = qla2x00_abort_isp,
706f457d 1915 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1916 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1917};
1918
1919static struct isp_operations qla24xx_isp_ops = {
1920 .pci_config = qla24xx_pci_config,
1921 .reset_chip = qla24xx_reset_chip,
1922 .chip_diag = qla24xx_chip_diag,
1923 .config_rings = qla24xx_config_rings,
1924 .reset_adapter = qla24xx_reset_adapter,
1925 .nvram_config = qla24xx_nvram_config,
1926 .update_fw_options = qla24xx_update_fw_options,
1927 .load_risc = qla24xx_load_risc,
1928 .pci_info_str = qla24xx_pci_info_str,
1929 .fw_version_str = qla24xx_fw_version_str,
1930 .intr_handler = qla24xx_intr_handler,
1931 .enable_intrs = qla24xx_enable_intrs,
1932 .disable_intrs = qla24xx_disable_intrs,
1933 .abort_command = qla24xx_abort_command,
523ec773
AV		 1934 .target_reset = qla24xx_abort_target,
1935 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1936 .fabric_login = qla24xx_login_fabric,
1937 .fabric_logout = qla24xx_fabric_logout,
1938 .calc_req_entries = NULL,
1939 .build_iocbs = NULL,
1940 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1941 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1942 .read_nvram = qla24xx_read_nvram_data,
1943 .write_nvram = qla24xx_write_nvram_data,
1944 .fw_dump = qla24xx_fw_dump,
1945 .beacon_on = qla24xx_beacon_on,
1946 .beacon_off = qla24xx_beacon_off,
1947 .beacon_blink = qla24xx_beacon_blink,
1948 .read_optrom = qla24xx_read_optrom_data,
1949 .write_optrom = qla24xx_write_optrom_data,
1950 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1951 .start_scsi = qla24xx_start_scsi,
a9083016 1952 .abort_isp = qla2x00_abort_isp,
706f457d 1953 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1954 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1955};
1956
c3a2f0df
AV		 1957static struct isp_operations qla25xx_isp_ops = {
1958 .pci_config = qla25xx_pci_config,
1959 .reset_chip = qla24xx_reset_chip,
1960 .chip_diag = qla24xx_chip_diag,
1961 .config_rings = qla24xx_config_rings,
1962 .reset_adapter = qla24xx_reset_adapter,
1963 .nvram_config = qla24xx_nvram_config,
1964 .update_fw_options = qla24xx_update_fw_options,
1965 .load_risc = qla24xx_load_risc,
1966 .pci_info_str = qla24xx_pci_info_str,
1967 .fw_version_str = qla24xx_fw_version_str,
1968 .intr_handler = qla24xx_intr_handler,
1969 .enable_intrs = qla24xx_enable_intrs,
1970 .disable_intrs = qla24xx_disable_intrs,
1971 .abort_command = qla24xx_abort_command,
523ec773
AV		 1972 .target_reset = qla24xx_abort_target,
1973 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1974 .fabric_login = qla24xx_login_fabric,
1975 .fabric_logout = qla24xx_fabric_logout,
1976 .calc_req_entries = NULL,
1977 .build_iocbs = NULL,
1978 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1979 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1980 .read_nvram = qla25xx_read_nvram_data,
1981 .write_nvram = qla25xx_write_nvram_data,
1982 .fw_dump = qla25xx_fw_dump,
1983 .beacon_on = qla24xx_beacon_on,
1984 .beacon_off = qla24xx_beacon_off,
1985 .beacon_blink = qla24xx_beacon_blink,
338c9161 1986 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1987 .write_optrom = qla24xx_write_optrom_data,
1988 .get_flash_version = qla24xx_get_flash_version,
bad75002 1989 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1990 .abort_isp = qla2x00_abort_isp,
706f457d 1991 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1992 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1993};
1994
3a03eb79
AV		 1995static struct isp_operations qla81xx_isp_ops = {
1996 .pci_config = qla25xx_pci_config,
1997 .reset_chip = qla24xx_reset_chip,
1998 .chip_diag = qla24xx_chip_diag,
1999 .config_rings = qla24xx_config_rings,
2000 .reset_adapter = qla24xx_reset_adapter,
2001 .nvram_config = qla81xx_nvram_config,
2002 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2003 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2004 .pci_info_str = qla24xx_pci_info_str,
2005 .fw_version_str = qla24xx_fw_version_str,
2006 .intr_handler = qla24xx_intr_handler,
2007 .enable_intrs = qla24xx_enable_intrs,
2008 .disable_intrs = qla24xx_disable_intrs,
2009 .abort_command = qla24xx_abort_command,
2010 .target_reset = qla24xx_abort_target,
2011 .lun_reset = qla24xx_lun_reset,
2012 .fabric_login = qla24xx_login_fabric,
2013 .fabric_logout = qla24xx_fabric_logout,
2014 .calc_req_entries = NULL,
2015 .build_iocbs = NULL,
2016 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2017 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2018 .read_nvram = NULL,
2019 .write_nvram = NULL,
3a03eb79
AV		 2020 .fw_dump = qla81xx_fw_dump,
2021 .beacon_on = qla24xx_beacon_on,
2022 .beacon_off = qla24xx_beacon_off,
6246b8a1 2023 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2024 .read_optrom = qla25xx_read_optrom_data,
2025 .write_optrom = qla24xx_write_optrom_data,
2026 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2027 .start_scsi = qla24xx_dif_start_scsi,
a9083016 2028 .abort_isp = qla2x00_abort_isp,
706f457d 2029 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2030 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2031};
2032
2033static struct isp_operations qla82xx_isp_ops = {
2034 .pci_config = qla82xx_pci_config,
2035 .reset_chip = qla82xx_reset_chip,
2036 .chip_diag = qla24xx_chip_diag,
2037 .config_rings = qla82xx_config_rings,
2038 .reset_adapter = qla24xx_reset_adapter,
2039 .nvram_config = qla81xx_nvram_config,
2040 .update_fw_options = qla24xx_update_fw_options,
2041 .load_risc = qla82xx_load_risc,
9d55ca66 2042 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2043 .fw_version_str = qla24xx_fw_version_str,
2044 .intr_handler = qla82xx_intr_handler,
2045 .enable_intrs = qla82xx_enable_intrs,
2046 .disable_intrs = qla82xx_disable_intrs,
2047 .abort_command = qla24xx_abort_command,
2048 .target_reset = qla24xx_abort_target,
2049 .lun_reset = qla24xx_lun_reset,
2050 .fabric_login = qla24xx_login_fabric,
2051 .fabric_logout = qla24xx_fabric_logout,
2052 .calc_req_entries = NULL,
2053 .build_iocbs = NULL,
2054 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2055 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2056 .read_nvram = qla24xx_read_nvram_data,
2057 .write_nvram = qla24xx_write_nvram_data,
2058 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 2059 .beacon_on = qla82xx_beacon_on,
2060 .beacon_off = qla82xx_beacon_off,
2061 .beacon_blink = NULL,
a9083016
GM		 2062 .read_optrom = qla82xx_read_optrom_data,
2063 .write_optrom = qla82xx_write_optrom_data,
2064 .get_flash_version = qla24xx_get_flash_version,
2065 .start_scsi = qla82xx_start_scsi,
2066 .abort_isp = qla82xx_abort_isp,
706f457d 2067 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2068 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2069};
2070
6246b8a1
GM		 2071static struct isp_operations qla83xx_isp_ops = {
2072 .pci_config = qla25xx_pci_config,
2073 .reset_chip = qla24xx_reset_chip,
2074 .chip_diag = qla24xx_chip_diag,
2075 .config_rings = qla24xx_config_rings,
2076 .reset_adapter = qla24xx_reset_adapter,
2077 .nvram_config = qla81xx_nvram_config,
2078 .update_fw_options = qla81xx_update_fw_options,
2079 .load_risc = qla81xx_load_risc,
2080 .pci_info_str = qla24xx_pci_info_str,
2081 .fw_version_str = qla24xx_fw_version_str,
2082 .intr_handler = qla24xx_intr_handler,
2083 .enable_intrs = qla24xx_enable_intrs,
2084 .disable_intrs = qla24xx_disable_intrs,
2085 .abort_command = qla24xx_abort_command,
2086 .target_reset = qla24xx_abort_target,
2087 .lun_reset = qla24xx_lun_reset,
2088 .fabric_login = qla24xx_login_fabric,
2089 .fabric_logout = qla24xx_fabric_logout,
2090 .calc_req_entries = NULL,
2091 .build_iocbs = NULL,
2092 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2093 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2094 .read_nvram = NULL,
2095 .write_nvram = NULL,
2096 .fw_dump = qla83xx_fw_dump,
2097 .beacon_on = qla24xx_beacon_on,
2098 .beacon_off = qla24xx_beacon_off,
2099 .beacon_blink = qla83xx_beacon_blink,
2100 .read_optrom = qla25xx_read_optrom_data,
2101 .write_optrom = qla24xx_write_optrom_data,
2102 .get_flash_version = qla24xx_get_flash_version,
2103 .start_scsi = qla24xx_dif_start_scsi,
2104 .abort_isp = qla2x00_abort_isp,
2105 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2106 .initialize_adapter = qla2x00_initialize_adapter,
2107};
2108
2109static struct isp_operations qlafx00_isp_ops = {
2110 .pci_config = qlafx00_pci_config,
2111 .reset_chip = qlafx00_soft_reset,
2112 .chip_diag = qlafx00_chip_diag,
2113 .config_rings = qlafx00_config_rings,
2114 .reset_adapter = qlafx00_soft_reset,
2115 .nvram_config = NULL,
2116 .update_fw_options = NULL,
2117 .load_risc = NULL,
2118 .pci_info_str = qlafx00_pci_info_str,
2119 .fw_version_str = qlafx00_fw_version_str,
2120 .intr_handler = qlafx00_intr_handler,
2121 .enable_intrs = qlafx00_enable_intrs,
2122 .disable_intrs = qlafx00_disable_intrs,
2123 .abort_command = qlafx00_abort_command,
2124 .target_reset = qlafx00_abort_target,
2125 .lun_reset = qlafx00_lun_reset,
2126 .fabric_login = NULL,
2127 .fabric_logout = NULL,
2128 .calc_req_entries = NULL,
2129 .build_iocbs = NULL,
2130 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2131 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2132 .read_nvram = qla24xx_read_nvram_data,
2133 .write_nvram = qla24xx_write_nvram_data,
2134 .fw_dump = NULL,
2135 .beacon_on = qla24xx_beacon_on,
2136 .beacon_off = qla24xx_beacon_off,
2137 .beacon_blink = NULL,
2138 .read_optrom = qla24xx_read_optrom_data,
2139 .write_optrom = qla24xx_write_optrom_data,
2140 .get_flash_version = qla24xx_get_flash_version,
2141 .start_scsi = qlafx00_start_scsi,
2142 .abort_isp = qlafx00_abort_isp,
2143 .iospace_config = qlafx00_iospace_config,
2144 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2145};
2146
ea5b6382 2147static inline void
e315cd28 2148qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2149{
2150 ha->device_type = DT_EXTENDED_IDS;
2151 switch (ha->pdev->device) {
2152 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2153 ha->device_type |= DT_ISP2100;
2154 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2155 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2156 break;
2157 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2158 ha->device_type |= DT_ISP2200;
2159 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2160 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2161 break;
2162 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2163 ha->device_type |= DT_ISP2300;
4a59f71d 2164 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2165 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2166 break;
2167 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2168 ha->device_type |= DT_ISP2312;
4a59f71d 2169 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2170 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2171 break;
2172 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2173 ha->device_type |= DT_ISP2322;
4a59f71d 2174 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2175 if (ha->pdev->subsystem_vendor == 0x1028 &&
2176 ha->pdev->subsystem_device == 0x0170)
2177 ha->device_type |= DT_OEM_001;
441d1072 2178 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2179 break;
2180 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2181 ha->device_type |= DT_ISP6312;
441d1072 2182 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2183 break;
2184 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2185 ha->device_type |= DT_ISP6322;
441d1072 2186 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2187 break;
2188 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2189 ha->device_type |= DT_ISP2422;
4a59f71d 2190 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2191 ha->device_type |= DT_FWI2;
c76f2c01 2192 ha->device_type |= DT_IIDMA;
441d1072 2193 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2194 break;
2195 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2196 ha->device_type |= DT_ISP2432;
4a59f71d 2197 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2198 ha->device_type |= DT_FWI2;
c76f2c01 2199 ha->device_type |= DT_IIDMA;
441d1072 2200 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2201 break;
4d4df193
HK		 2202 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2203 ha->device_type |= DT_ISP8432;
2204 ha->device_type |= DT_ZIO_SUPPORTED;
2205 ha->device_type |= DT_FWI2;
2206 ha->device_type |= DT_IIDMA;
2207 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2208 break;
044cc6c8
AV		 2209 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2210 ha->device_type |= DT_ISP5422;
e428924c 2211 ha->device_type |= DT_FWI2;
441d1072 2212 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2213 break;
044cc6c8
AV		 2214 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2215 ha->device_type |= DT_ISP5432;
e428924c 2216 ha->device_type |= DT_FWI2;
441d1072 2217 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2218 break;
c3a2f0df
AV		 2219 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2220 ha->device_type |= DT_ISP2532;
2221 ha->device_type |= DT_ZIO_SUPPORTED;
2222 ha->device_type |= DT_FWI2;
2223 ha->device_type |= DT_IIDMA;
441d1072 2224 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2225 break;
3a03eb79
AV		 2226 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2227 ha->device_type |= DT_ISP8001;
2228 ha->device_type |= DT_ZIO_SUPPORTED;
2229 ha->device_type |= DT_FWI2;
2230 ha->device_type |= DT_IIDMA;
2231 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2232 break;
a9083016
GM		 2233 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2234 ha->device_type |= DT_ISP8021;
2235 ha->device_type |= DT_ZIO_SUPPORTED;
2236 ha->device_type |= DT_FWI2;
2237 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2238 /* Initialize 82XX ISP flags */
2239 qla82xx_init_flags(ha);
2240 break;
6246b8a1
GM		 2241 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2242 ha->device_type |= DT_ISP2031;
2243 ha->device_type |= DT_ZIO_SUPPORTED;
2244 ha->device_type |= DT_FWI2;
2245 ha->device_type |= DT_IIDMA;
2246 ha->device_type |= DT_T10_PI;
2247 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2248 break;
2249 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2250 ha->device_type |= DT_ISP8031;
2251 ha->device_type |= DT_ZIO_SUPPORTED;
2252 ha->device_type |= DT_FWI2;
2253 ha->device_type |= DT_IIDMA;
2254 ha->device_type |= DT_T10_PI;
2255 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2256 break;
8ae6d9c7
GM		 2257 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2258 ha->device_type |= DT_ISPFX00;
2259 break;
ea5b6382 2260 }
e5b68a61 2261
a9083016
GM		 2262 if (IS_QLA82XX(ha))
2263 ha->port_no = !(ha->portnum & 1);
2264 else
2265 /* Get adapter physical port no from interrupt pin register. */
2266 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2267
e5b68a61
AC		 2268 if (ha->port_no & 1)
2269 ha->flags.port0 = 1;
2270 else
2271 ha->flags.port0 = 0;
7c3df132 2272 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2273 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
7c3df132 2274 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382
AV		 2275}
2276
1e99e33a
AV		 2277static void
2278qla2xxx_scan_start(struct Scsi_Host *shost)
2279{
e315cd28 2280 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2281
cbc8eb67
AV		 2282 if (vha->hw->flags.running_gold_fw)
2283 return;
2284
e315cd28
AC		 2285 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2286 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2287 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2288 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2289}
2290
2291static int
2292qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2293{
e315cd28 2294 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2295
e315cd28 2296 if (!vha->host)
1e99e33a 2297 return 1;
e315cd28 2298 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2299 return 1;
2300
e315cd28 2301 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2302}
2303
1da177e4
LT		 2304/*
2305 * PCI driver interface
2306 */
6f039790 2307static int
7ee61397 2308qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2309{
a1541d5a 2310 int ret = -ENODEV;
1da177e4 2311 struct Scsi_Host *host;
e315cd28
AC		 2312 scsi_qla_host_t *base_vha = NULL;
2313 struct qla_hw_data *ha;
29856e28 2314 char pci_info[30];
7d613ac6 2315 char fw_str[30], wq_name[30];
5433383e 2316 struct scsi_host_template *sht;
642ef983 2317 int bars, mem_only = 0;
e315cd28 2318 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2319 struct req_que *req = NULL;
2320 struct rsp_que *rsp = NULL;
1da177e4 2321
285d0321 2322 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2323 sht = &qla2xxx_driver_template;
5433383e 2324 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2325 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2326 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2327 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2328 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2329 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2330 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2331 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2332 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7
GM		 2333 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2334 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001) {
285d0321 2335 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2336 mem_only = 1;
7c3df132
SK		 2337 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2338 "Mem only adapter.\n");
285d0321 2339 }
7c3df132
SK		 2340 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2341 "Bars=%d.\n", bars);
285d0321 2342
09483916
BH		 2343 if (mem_only) {
2344 if (pci_enable_device_mem(pdev))
a72c279d 2345 return ret;
09483916
BH		 2346 } else {
2347 if (pci_enable_device(pdev))
a72c279d 2348 return ret;
09483916 2349 }
285d0321 2350
0927678f
JB		 2351 /* This may fail but that's ok */
2352 pci_enable_pcie_error_reporting(pdev);
285d0321 2353
e315cd28
AC		 2354 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2355 if (!ha) {
7c3df132
SK		 2356 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2357 "Unable to allocate memory for ha.\n");
a72c279d 2358 goto disable_device;
1da177e4 2359 }
7c3df132
SK		 2360 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2361 "Memory allocated for ha=%p.\n", ha);
e315cd28 2362 ha->pdev = pdev;
2d70c103 2363 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2364
2365 /* Clear our data area */
285d0321 2366 ha->bars = bars;
09483916 2367 ha->mem_only = mem_only;
df4bf0bb 2368 spin_lock_init(&ha->hardware_lock);
339aa70e 2369 spin_lock_init(&ha->vport_slock);
a9b6f722 2370 mutex_init(&ha->selflogin_lock);
1da177e4 2371
ea5b6382
AV		 2372 /* Set ISP-type information. */
2373 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2374
2375 /* Set EEH reset type to fundamental if required by hba */
95676112
JC		 2376 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2377 IS_QLA83XX(ha))
ca79cf66 2378 pdev->needs_freset = 1;
ca79cf66 2379
cba1e47f
CD		 2380 ha->prev_topology = 0;
2381 ha->init_cb_size = sizeof(init_cb_t);
2382 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2383 ha->optrom_size = OPTROM_SIZE_2300;
3c290d0b 2384 ha->cfg_lun_q_depth = ql2xmaxqdepth;
cba1e47f 2385
abbd8870 2386 /* Assign ISP specific operations. */
1da177e4 2387 if (IS_QLA2100(ha)) {
642ef983 2388 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2389 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2390 req_length = REQUEST_ENTRY_CNT_2100;
2391 rsp_length = RESPONSE_ENTRY_CNT_2100;
2392 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2393 ha->gid_list_info_size = 4;
3a03eb79
AV		 2394 ha->flash_conf_off = ~0;
2395 ha->flash_data_off = ~0;
2396 ha->nvram_conf_off = ~0;
2397 ha->nvram_data_off = ~0;
fd34f556 2398 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2399 } else if (IS_QLA2200(ha)) {
642ef983 2400 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2401 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2402 req_length = REQUEST_ENTRY_CNT_2200;
2403 rsp_length = RESPONSE_ENTRY_CNT_2100;
2404 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2405 ha->gid_list_info_size = 4;
3a03eb79
AV		 2406 ha->flash_conf_off = ~0;
2407 ha->flash_data_off = ~0;
2408 ha->nvram_conf_off = ~0;
2409 ha->nvram_data_off = ~0;
fd34f556 2410 ha->isp_ops = &qla2100_isp_ops;
fca29703 2411 } else if (IS_QLA23XX(ha)) {
642ef983 2412 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2413 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2414 req_length = REQUEST_ENTRY_CNT_2200;
2415 rsp_length = RESPONSE_ENTRY_CNT_2300;
2416 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2417 ha->gid_list_info_size = 6;
854165f4
AV		 2418 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2419 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2420 ha->flash_conf_off = ~0;
2421 ha->flash_data_off = ~0;
2422 ha->nvram_conf_off = ~0;
2423 ha->nvram_data_off = ~0;
fd34f556 2424 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2425 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2426 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2427 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2428 req_length = REQUEST_ENTRY_CNT_24XX;
2429 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2430 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2431 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2432 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2433 ha->gid_list_info_size = 8;
854165f4 2434 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2435 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2436 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2437 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2438 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2439 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2440 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2441 } else if (IS_QLA25XX(ha)) {
642ef983 2442 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2443 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2444 req_length = REQUEST_ENTRY_CNT_24XX;
2445 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2446 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2447 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2448 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2449 ha->gid_list_info_size = 8;
2450 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2451 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2452 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2453 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2454 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2455 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2456 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2457 } else if (IS_QLA81XX(ha)) {
642ef983 2458 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2459 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2460 req_length = REQUEST_ENTRY_CNT_24XX;
2461 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2462 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2463 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2464 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2465 ha->gid_list_info_size = 8;
2466 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2467 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2468 ha->isp_ops = &qla81xx_isp_ops;
2469 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2470 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2471 ha->nvram_conf_off = ~0;
2472 ha->nvram_data_off = ~0;
a9083016 2473 } else if (IS_QLA82XX(ha)) {
642ef983 2474 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2475 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2476 req_length = REQUEST_ENTRY_CNT_82XX;
2477 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2478 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2479 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2480 ha->gid_list_info_size = 8;
2481 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2482 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2483 ha->isp_ops = &qla82xx_isp_ops;
2484 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2485 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2486 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2487 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2488 } else if (IS_QLA83XX(ha)) {
7d613ac6 2489 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2490 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2491 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2492 req_length = REQUEST_ENTRY_CNT_24XX;
2493 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2494 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2495 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2496 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2497 ha->gid_list_info_size = 8;
2498 ha->optrom_size = OPTROM_SIZE_83XX;
2499 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2500 ha->isp_ops = &qla83xx_isp_ops;
2501 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2502 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2503 ha->nvram_conf_off = ~0;
2504 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2505 } else if (IS_QLAFX00(ha)) {
2506 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2507 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2508 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2509 req_length = REQUEST_ENTRY_CNT_FX00;
2510 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2511 ha->init_cb_size = sizeof(struct init_cb_fx);
2512 ha->isp_ops = &qlafx00_isp_ops;
2513 ha->port_down_retry_count = 30; /* default value */
2514 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2515 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2516 ha->mr.fw_hbt_en = 1;
1da177e4 2517 }
6246b8a1 2518
7c3df132
SK		 2519 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2520 "mbx_count=%d, req_length=%d, "
2521 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2522 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2523 "max_fibre_devices=%d.\n",
7c3df132
SK		 2524 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2525 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2526 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2527 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2528 "isp_ops=%p, flash_conf_off=%d, "
2529 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2530 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2531 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2532
2533 /* Configure PCI I/O space */
2534 ret = ha->isp_ops->iospace_config(ha);
2535 if (ret)
0a63ad12 2536 goto iospace_config_failed;
706f457d
GM		 2537
2538 ql_log_pci(ql_log_info, pdev, 0x001d,
2539 "Found an ISP%04X irq %d iobase 0x%p.\n",
2540 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2541 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2542 init_completion(&ha->mbx_cmd_comp);
2543 complete(&ha->mbx_cmd_comp);
2544 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2545 init_completion(&ha->dcbx_comp);
f356bef1 2546 init_completion(&ha->lb_portup_comp);
1da177e4 2547
2c3dfe3f 2548 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2549
53303c42 2550 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2551 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2552 "64 Bit addressing is %s.\n",
2553 ha->flags.enable_64bit_addressing ? "enable" :
2554 "disable");
73208dfd 2555 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
daa12c3a 2556 if (ret) {
7c3df132
SK		 2557 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2558 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2559
e315cd28
AC		 2560 goto probe_hw_failed;
2561 }
2562
73208dfd 2563 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2564 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2565 req->max_q_depth = ql2xmaxqdepth;
2566
e315cd28
AC		 2567
2568 base_vha = qla2x00_create_host(sht, ha);
2569 if (!base_vha) {
a1541d5a 2570 ret = -ENOMEM;
6e9f21f3 2571 qla2x00_mem_free(ha);
2afa19a9
AC		 2572 qla2x00_free_req_que(ha, req);
2573 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2574 goto probe_hw_failed;
1da177e4
LT		 2575 }
2576
e315cd28
AC		 2577 pci_set_drvdata(pdev, base_vha);
2578
e315cd28 2579 host = base_vha->host;
2afa19a9 2580 base_vha->req = req;
8ae6d9c7
GM		 2581 if (IS_QLAFX00(ha))
2582 host->can_queue = 1024;
2583 else
2584 host->can_queue = req->length + 128;
73208dfd 2585 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2586 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2587 else
e315cd28
AC		 2588 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2589 base_vha->vp_idx;
58548cb5 2590
8ae6d9c7
GM		 2591 /* Setup fcport template structure. */
2592 ha->mr.fcport.vha = base_vha;
2593 ha->mr.fcport.port_type = FCT_UNKNOWN;
2594 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2595 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2596 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2597 ha->mr.fcport.scan_state = 1;
2598
58548cb5
GM		 2599 /* Set the SG table size based on ISP type */
2600 if (!IS_FWI2_CAPABLE(ha)) {
2601 if (IS_QLA2100(ha))
2602 host->sg_tablesize = 32;
2603 } else {
2604 if (!IS_QLA82XX(ha))
2605 host->sg_tablesize = QLA_SG_ALL;
2606 }
7c3df132
SK		 2607 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2608 "can_queue=%d, req=%p, "
2609 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2610 host->can_queue, base_vha->req,
2611 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
642ef983 2612 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2613 host->cmd_per_lun = 3;
2614 host->unique_id = host->host_no;
e02587d7 2615 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2616 host->max_cmd_len = 32;
2617 else
2618 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2619 host->max_channel = MAX_BUSES - 1;
82515920 2620 host->max_lun = ql2xmaxlun;
e315cd28 2621 host->transportt = qla2xxx_transport_template;
9a069e19 2622 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2623
7c3df132
SK		 2624 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2625 "max_id=%d this_id=%d "
2626 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2627 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2628 host->this_id, host->cmd_per_lun, host->unique_id,
2629 host->max_cmd_len, host->max_channel, host->max_lun,
2630 host->transportt, sht->vendor_id);
2631
9a347ff4
CD		 2632que_init:
2633 /* Alloc arrays of request and response ring ptrs */
2634 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2635 ql_log(ql_log_fatal, base_vha, 0x003d,
2636 "Failed to allocate memory for queue pointers..."
2637 "aborting.\n");
2638 goto probe_init_failed;
2639 }
2640
2d70c103 2641 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2642
73208dfd
AC		 2643 /* Set up the irqs */
2644 ret = qla2x00_request_irqs(ha, rsp);
2645 if (ret)
6e9f21f3 2646 goto probe_init_failed;
90a86fc0
JC		 2647
2648 pci_save_state(pdev);
2649
9a347ff4 2650 /* Assign back pointers */
2afa19a9
AC		 2651 rsp->req = req;
2652 req->rsp = rsp;
9a347ff4 2653
8ae6d9c7
GM		 2654 if (IS_QLAFX00(ha)) {
2655 ha->rsp_q_map[0] = rsp;
2656 ha->req_q_map[0] = req;
2657 set_bit(0, ha->req_qid_map);
2658 set_bit(0, ha->rsp_qid_map);
2659 }
2660
08029990
AV		 2661 /* FWI2-capable only. */
2662 req->req_q_in = &ha->iobase->isp24.req_q_in;
2663 req->req_q_out = &ha->iobase->isp24.req_q_out;
2664 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2665 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
6246b8a1 2666 if (ha->mqenable || IS_QLA83XX(ha)) {
08029990
AV		 2667 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2668 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2669 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2670 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2671 }
2672
8ae6d9c7
GM		 2673 if (IS_QLAFX00(ha)) {
2674 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2675 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2676 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2677 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2678 }
2679
a9083016
GM		 2680 if (IS_QLA82XX(ha)) {
2681 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2682 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2683 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2684 }
2685
7c3df132
SK		 2686 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2687 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2688 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2689 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2690 "req->req_q_in=%p req->req_q_out=%p "
2691 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2692 req->req_q_in, req->req_q_out,
2693 rsp->rsp_q_in, rsp->rsp_q_out);
2694 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2695 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2696 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2697 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2698 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2699 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2700
8ae6d9c7 2701 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2702 ql_log(ql_log_fatal, base_vha, 0x00d6,
2703 "Failed to initialize adapter - Adapter flags %x.\n",
2704 base_vha->device_flags);
1da177e4 2705
a9083016
GM		 2706 if (IS_QLA82XX(ha)) {
2707 qla82xx_idc_lock(ha);
2708 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2709 QLA8XXX_DEV_FAILED);
a9083016 2710 qla82xx_idc_unlock(ha);
7c3df132
SK		 2711 ql_log(ql_log_fatal, base_vha, 0x00d7,
2712 "HW State: FAILED.\n");
a9083016
GM		 2713 }
2714
a1541d5a 2715 ret = -ENODEV;
1da177e4
LT		 2716 goto probe_failed;
2717 }
2718
7163ea81
AC		 2719 if (ha->mqenable) {
2720 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2721 ql_log(ql_log_warn, base_vha, 0x00ec,
2722 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2723 goto que_init;
2724 }
2725 }
68ca949c 2726
cbc8eb67
AV		 2727 if (ha->flags.running_gold_fw)
2728 goto skip_dpc;
2729
1da177e4
LT		 2730 /*
2731 * Startup the kernel thread for this host adapter
2732 */
39a11240 2733 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2734 "%s_dpc", base_vha->host_str);
39a11240 2735 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2736 ql_log(ql_log_fatal, base_vha, 0x00ed,
2737 "Failed to start DPC thread.\n");
39a11240 2738 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2739 goto probe_failed;
2740 }
7c3df132
SK		 2741 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2742 "DPC thread started successfully.\n");
1da177e4 2743
2d70c103
NB		 2744 /*
2745 * If we're not coming up in initiator mode, we might sit for
2746 * a while without waking up the dpc thread, which leads to a
2747 * stuck process warning. So just kick the dpc once here and
2748 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2749 */
2750 qla2xxx_wake_dpc(base_vha);
2751
81178772
SK		 2752 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2753 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2754 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2755 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2756
2757 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2758 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2759 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2760 INIT_WORK(&ha->idc_state_handler,
2761 qla83xx_idc_state_handler_work);
2762 INIT_WORK(&ha->nic_core_unrecoverable,
2763 qla83xx_nic_core_unrecoverable_work);
2764 }
2765
cbc8eb67 2766skip_dpc:
e315cd28
AC		 2767 list_add_tail(&base_vha->list, &ha->vp_list);
2768 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2769
2770 /* Initialized the timer */
e315cd28 2771 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2772 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2773 "Started qla2x00_timer with "
2774 "interval=%d.\n", WATCH_INTERVAL);
2775 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2776 "Detected hba at address=%p.\n",
2777 ha);
d19044c3 2778
e02587d7 2779 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2780 if (ha->fw_attributes & BIT_4) {
9e522cd8 2781 int prot = 0, guard;
bad75002 2782 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2783 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2784 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2785 if (ql2xenabledif == 1)
2786 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2787 scsi_host_set_prot(host,
8cb2049c 2788 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2789 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2790 | SHOST_DIF_TYPE3_PROTECTION
2791 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2792 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2793 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2794
2795 guard = SHOST_DIX_GUARD_CRC;
2796
2797 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2798 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2799 guard |= SHOST_DIX_GUARD_IP;
2800
2801 scsi_host_set_guard(host, guard);
bad75002
AE		 2802 } else
2803 base_vha->flags.difdix_supported = 0;
2804 }
2805
a9083016
GM		 2806 ha->isp_ops->enable_intrs(ha);
2807
a1541d5a
AV		 2808 ret = scsi_add_host(host, &pdev->dev);
2809 if (ret)
2810 goto probe_failed;
2811
1486400f
MR		 2812 base_vha->flags.init_done = 1;
2813 base_vha->flags.online = 1;
2814
7c3df132
SK		 2815 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2816 "Init done and hba is online.\n");
2817
2d70c103
NB		 2818 if (qla_ini_mode_enabled(base_vha))
2819 scsi_scan_host(host);
2820 else
2821 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2822 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2823
e315cd28 2824 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2825
8ae6d9c7
GM		 2826 if (IS_QLAFX00(ha)) {
2827 ret = qlafx00_fx_disc(base_vha,
2828 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2829
2830 ret = qlafx00_fx_disc(base_vha,
2831 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2832
2833 /* Register system information */
2834 ret = qlafx00_fx_disc(base_vha,
2835 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2836 }
2837
e315cd28 2838 qla2x00_init_host_attr(base_vha);
a1541d5a 2839
e315cd28 2840 qla2x00_dfs_setup(base_vha);
df613b96 2841
7c3df132
SK		 2842 ql_log(ql_log_info, base_vha, 0x00fb,
2843 "QLogic %s - %s.\n",
2844 ha->model_number, ha->model_desc ? ha->model_desc : "");
2845 ql_log(ql_log_info, base_vha, 0x00fc,
2846 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2847 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2848 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2849 base_vha->host_no,
e315cd28 2850 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2851
2d70c103
NB		 2852 qlt_add_target(ha, base_vha);
2853
1da177e4
LT		 2854 return 0;
2855
6e9f21f3 2856probe_init_failed:
2afa19a9 2857 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2858 ha->req_q_map[0] = NULL;
2859 clear_bit(0, ha->req_qid_map);
2afa19a9 2860 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2861 ha->rsp_q_map[0] = NULL;
2862 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2863 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2864
1da177e4 2865probe_failed:
b9978769
AV		 2866 if (base_vha->timer_active)
2867 qla2x00_stop_timer(base_vha);
2868 base_vha->flags.online = 0;
2869 if (ha->dpc_thread) {
2870 struct task_struct *t = ha->dpc_thread;
2871
2872 ha->dpc_thread = NULL;
2873 kthread_stop(t);
2874 }
2875
e315cd28 2876 qla2x00_free_device(base_vha);
1da177e4 2877
e315cd28 2878 scsi_host_put(base_vha->host);
1da177e4 2879
e315cd28 2880probe_hw_failed:
a9083016
GM		 2881 if (IS_QLA82XX(ha)) {
2882 qla82xx_idc_lock(ha);
2883 qla82xx_clear_drv_active(ha);
2884 qla82xx_idc_unlock(ha);
0a63ad12
SK		 2885 }
2886iospace_config_failed:
2887 if (IS_QLA82XX(ha)) {
2888 if (!ha->nx_pcibase)
2889 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
a9083016
GM		 2890 if (!ql2xdbwr)
2891 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2892 } else {
2893 if (ha->iobase)
2894 iounmap(ha->iobase);
8ae6d9c7
GM		 2895 if (ha->cregbase)
2896 iounmap(ha->cregbase);
a9083016 2897 }
e315cd28
AC		 2898 pci_release_selected_regions(ha->pdev, ha->bars);
2899 kfree(ha);
2900 ha = NULL;
1da177e4 2901
a72c279d 2902disable_device:
e315cd28 2903 pci_disable_device(pdev);
a1541d5a 2904 return ret;
1da177e4 2905}
1da177e4 2906
2d70c103
NB		 2907static void
2908qla2x00_stop_dpc_thread(scsi_qla_host_t *vha)
2909{
2910 struct qla_hw_data *ha = vha->hw;
2911 struct task_struct *t = ha->dpc_thread;
2912
2913 if (ha->dpc_thread == NULL)
2914 return;
2915 /*
2916 * qla2xxx_wake_dpc checks for ->dpc_thread
2917 * so we need to zero it out.
2918 */
2919 ha->dpc_thread = NULL;
2920 kthread_stop(t);
2921}
2922
e30d1756
MI		 2923static void
2924qla2x00_shutdown(struct pci_dev *pdev)
2925{
2926 scsi_qla_host_t *vha;
2927 struct qla_hw_data *ha;
2928
552f3f9a
MI		 2929 if (!atomic_read(&pdev->enable_cnt))
2930 return;
2931
e30d1756
MI		 2932 vha = pci_get_drvdata(pdev);
2933 ha = vha->hw;
2934
2935 /* Turn-off FCE trace */
2936 if (ha->flags.fce_enabled) {
2937 qla2x00_disable_fce_trace(vha, NULL, NULL);
2938 ha->flags.fce_enabled = 0;
2939 }
2940
2941 /* Turn-off EFT trace */
2942 if (ha->eft)
2943 qla2x00_disable_eft_trace(vha);
2944
2945 /* Stop currently executing firmware. */
2946 qla2x00_try_to_stop_firmware(vha);
2947
2948 /* Turn adapter off line */
2949 vha->flags.online = 0;
2950
2951 /* turn-off interrupts on the card */
2952 if (ha->interrupts_on) {
2953 vha->flags.init_done = 0;
2954 ha->isp_ops->disable_intrs(ha);
2955 }
2956
2957 qla2x00_free_irqs(vha);
2958
2959 qla2x00_free_fw_dump(ha);
2960}
2961
4c993f76 2962static void
7ee61397 2963qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2964{
feafb7b1 2965 scsi_qla_host_t *base_vha, *vha;
e315cd28 2966 struct qla_hw_data *ha;
feafb7b1 2967 unsigned long flags;
e315cd28 2968
9a347ff4
CD		 2969 /*
2970 * If the PCI device is disabled that means that probe failed and any
2971 * resources should be have cleaned up on probe exit.
2972 */
2973 if (!atomic_read(&pdev->enable_cnt))
2974 return;
2975
e315cd28
AC		 2976 base_vha = pci_get_drvdata(pdev);
2977 ha = base_vha->hw;
2978
2d70c103
NB		 2979 ha->flags.host_shutting_down = 1;
2980
220d36b4 2981 set_bit(UNLOADING, &base_vha->dpc_flags);
43ebf16d
AE		 2982 mutex_lock(&ha->vport_lock);
2983 while (ha->cur_vport_count) {
2984 struct Scsi_Host *scsi_host;
feafb7b1 2985
43ebf16d 2986 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2987
43ebf16d
AE		 2988 BUG_ON(base_vha->list.next == &ha->vp_list);
2989 /* This assumes first entry in ha->vp_list is always base vha */
2990 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2991 scsi_host = scsi_host_get(vha->host);
feafb7b1 2992
43ebf16d
AE		 2993 spin_unlock_irqrestore(&ha->vport_slock, flags);
2994 mutex_unlock(&ha->vport_lock);
2995
2996 fc_vport_terminate(vha->fc_vport);
2997 scsi_host_put(vha->host);
feafb7b1 2998
43ebf16d 2999 mutex_lock(&ha->vport_lock);
e315cd28 3000 }
43ebf16d 3001 mutex_unlock(&ha->vport_lock);
1da177e4 3002
7d613ac6
SV		 3003 if (IS_QLA8031(ha)) {
3004 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3005 "Clearing fcoe driver presence.\n");
3006 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3007 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3008 "Error while clearing DRV-Presence.\n");
3009 }
3010
b9978769
AV		 3011 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3012
e315cd28 3013 qla2x00_dfs_remove(base_vha);
c795c1e4 3014
e315cd28 3015 qla84xx_put_chip(base_vha);
c795c1e4 3016
b9978769
AV		 3017 /* Disable timer */
3018 if (base_vha->timer_active)
3019 qla2x00_stop_timer(base_vha);
3020
3021 base_vha->flags.online = 0;
3022
68ca949c
AC		 3023 /* Flush the work queue and remove it */
3024 if (ha->wq) {
3025 flush_workqueue(ha->wq);
3026 destroy_workqueue(ha->wq);
3027 ha->wq = NULL;
3028 }
3029
7d613ac6
SV		 3030 /* Cancel all work and destroy DPC workqueues */
3031 if (ha->dpc_lp_wq) {
3032 cancel_work_sync(&ha->idc_aen);
3033 destroy_workqueue(ha->dpc_lp_wq);
3034 ha->dpc_lp_wq = NULL;
3035 }
3036
3037 if (ha->dpc_hp_wq) {
3038 cancel_work_sync(&ha->nic_core_reset);
3039 cancel_work_sync(&ha->idc_state_handler);
3040 cancel_work_sync(&ha->nic_core_unrecoverable);
3041 destroy_workqueue(ha->dpc_hp_wq);
3042 ha->dpc_hp_wq = NULL;
3043 }
3044
b9978769
AV		 3045 /* Kill the kernel thread for this host */
3046 if (ha->dpc_thread) {
3047 struct task_struct *t = ha->dpc_thread;
3048
3049 /*
3050 * qla2xxx_wake_dpc checks for ->dpc_thread
3051 * so we need to zero it out.
3052 */
3053 ha->dpc_thread = NULL;
3054 kthread_stop(t);
3055 }
2d70c103 3056 qlt_remove_target(ha, base_vha);
b9978769 3057
e315cd28 3058 qla2x00_free_sysfs_attr(base_vha);
df613b96 3059
e315cd28 3060 fc_remove_host(base_vha->host);
4d4df193 3061
e315cd28 3062 scsi_remove_host(base_vha->host);
1da177e4 3063
e315cd28 3064 qla2x00_free_device(base_vha);
bdf79621 3065
e315cd28 3066 scsi_host_put(base_vha->host);
1da177e4 3067
a9083016 3068 if (IS_QLA82XX(ha)) {
b963752f
GM		 3069 qla82xx_idc_lock(ha);
3070 qla82xx_clear_drv_active(ha);
3071 qla82xx_idc_unlock(ha);
3072
a9083016
GM		 3073 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
3074 if (!ql2xdbwr)
3075 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
3076 } else {
3077 if (ha->iobase)
3078 iounmap(ha->iobase);
1da177e4 3079
8ae6d9c7
GM		 3080 if (ha->cregbase)
3081 iounmap(ha->cregbase);
3082
a9083016
GM		 3083 if (ha->mqiobase)
3084 iounmap(ha->mqiobase);
6246b8a1
GM		 3085
3086 if (IS_QLA83XX(ha) && ha->msixbase)
3087 iounmap(ha->msixbase);
a9083016 3088 }
73208dfd 3089
e315cd28
AC		 3090 pci_release_selected_regions(ha->pdev, ha->bars);
3091 kfree(ha);
3092 ha = NULL;
1da177e4 3093
90a86fc0
JC		 3094 pci_disable_pcie_error_reporting(pdev);
3095
665db93b 3096 pci_disable_device(pdev);
1da177e4
LT		 3097 pci_set_drvdata(pdev, NULL);
3098}
1da177e4
LT		 3099
3100static void
e315cd28 3101qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3102{
e315cd28 3103 struct qla_hw_data *ha = vha->hw;
1da177e4 3104
85880801
AV		 3105 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3106
3107 /* Disable timer */
3108 if (vha->timer_active)
3109 qla2x00_stop_timer(vha);
3110
2d70c103 3111 qla2x00_stop_dpc_thread(vha);
85880801 3112
2afa19a9 3113 qla25xx_delete_queues(vha);
df613b96 3114 if (ha->flags.fce_enabled)
e315cd28 3115 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3116
a7a167bf 3117 if (ha->eft)
e315cd28 3118 qla2x00_disable_eft_trace(vha);
a7a167bf 3119
f6ef3b18 3120 /* Stop currently executing firmware. */
e315cd28 3121 qla2x00_try_to_stop_firmware(vha);
1da177e4 3122
85880801
AV		 3123 vha->flags.online = 0;
3124
f6ef3b18 3125 /* turn-off interrupts on the card */
a9083016
GM		 3126 if (ha->interrupts_on) {
3127 vha->flags.init_done = 0;
fd34f556 3128 ha->isp_ops->disable_intrs(ha);
a9083016 3129 }
f6ef3b18 3130
e315cd28 3131 qla2x00_free_irqs(vha);
1da177e4 3132
8867048b
CD		 3133 qla2x00_free_fcports(vha);
3134
e315cd28 3135 qla2x00_mem_free(ha);
73208dfd 3136
08de2844
GM		 3137 qla82xx_md_free(vha);
3138
73208dfd 3139 qla2x00_free_queues(ha);
1da177e4
LT		 3140}
3141
8867048b
CD		 3142void qla2x00_free_fcports(struct scsi_qla_host *vha)
3143{
3144 fc_port_t *fcport, *tfcport;
3145
3146 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3147 list_del(&fcport->list);
5f16b331 3148 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3149 kfree(fcport);
3150 fcport = NULL;
3151 }
3152}
3153
d97994dc 3154static inline void
e315cd28 3155qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3156 int defer)
3157{
d97994dc 3158 struct fc_rport *rport;
67becc00 3159 scsi_qla_host_t *base_vha;
044d78e1 3160 unsigned long flags;
d97994dc
AV		 3161
3162 if (!fcport->rport)
3163 return;
3164
3165 rport = fcport->rport;
3166 if (defer) {
67becc00 3167 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3168 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3169 fcport->drport = rport;
044d78e1 3170 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3171 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3172 qla2xxx_wake_dpc(base_vha);
2d70c103 3173 } else {
d97994dc 3174 fc_remote_port_delete(rport);
2d70c103
NB		 3175 qlt_fc_port_deleted(vha, fcport);
3176 }
d97994dc
AV		 3177}
3178
1da177e4
LT		 3179/*
3180 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3181 *
3182 * Input: ha = adapter block pointer. fcport = port structure pointer.
3183 *
3184 * Return: None.
3185 *
3186 * Context:
3187 */
e315cd28 3188void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3189 int do_login, int defer)
1da177e4 3190{
8ae6d9c7
GM		 3191 if (IS_QLAFX00(vha->hw)) {
3192 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3193 qla2x00_schedule_rport_del(vha, fcport, defer);
3194 return;
3195 }
3196
2c3dfe3f 3197 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3198 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3199 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3200 qla2x00_schedule_rport_del(vha, fcport, defer);
3201 }
fa2a1ce5 3202 /*
1da177e4
LT		 3203 * We may need to retry the login, so don't change the state of the
3204 * port but do the retries.
3205 */
3206 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3207 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3208
3209 if (!do_login)
3210 return;
3211
3212 if (fcport->login_retry == 0) {
e315cd28
AC		 3213 fcport->login_retry = vha->hw->login_retry_count;
3214 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3215
7c3df132
SK		 3216 ql_dbg(ql_dbg_disc, vha, 0x2067,
3217 "Port login retry "
1da177e4 3218 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 3219 "id = 0x%04x retry cnt=%d.\n",
3220 fcport->port_name[0], fcport->port_name[1],
3221 fcport->port_name[2], fcport->port_name[3],
3222 fcport->port_name[4], fcport->port_name[5],
3223 fcport->port_name[6], fcport->port_name[7],
3224 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3225 }
3226}
3227
3228/*
3229 * qla2x00_mark_all_devices_lost
3230 * Updates fcport state when device goes offline.
3231 *
3232 * Input:
3233 * ha = adapter block pointer.
3234 * fcport = port structure pointer.
3235 *
3236 * Return:
3237 * None.
3238 *
3239 * Context:
3240 */
3241void
e315cd28 3242qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3243{
3244 fc_port_t *fcport;
3245
e315cd28 3246 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3247 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3248 continue;
0d6e61bc 3249
1da177e4
LT		 3250 /*
3251 * No point in marking the device as lost, if the device is
3252 * already DEAD.
3253 */
3254 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3255 continue;
e315cd28 3256 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3257 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3258 if (defer)
3259 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3260 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3261 qla2x00_schedule_rport_del(vha, fcport, defer);
3262 }
1da177e4
LT		 3263 }
3264}
3265
3266/*
3267* qla2x00_mem_alloc
3268* Allocates adapter memory.
3269*
3270* Returns:
3271* 0 = success.
e8711085 3272* !0 = failure.
1da177e4 3273*/
e8711085 3274static int
73208dfd
AC		 3275qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3276 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3277{
3278 char name[16];
1da177e4 3279
e8711085 3280 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3281 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3282 if (!ha->init_cb)
e315cd28 3283 goto fail;
e8711085 3284
2d70c103
NB		 3285 if (qlt_mem_alloc(ha) < 0)
3286 goto fail_free_init_cb;
3287
642ef983
CD		 3288 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3289 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3290 if (!ha->gid_list)
2d70c103 3291 goto fail_free_tgt_mem;
1da177e4 3292
e8711085
AV		 3293 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3294 if (!ha->srb_mempool)
e315cd28 3295 goto fail_free_gid_list;
e8711085 3296
a9083016
GM		 3297 if (IS_QLA82XX(ha)) {
3298 /* Allocate cache for CT6 Ctx. */
3299 if (!ctx_cachep) {
3300 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3301 sizeof(struct ct6_dsd), 0,
3302 SLAB_HWCACHE_ALIGN, NULL);
3303 if (!ctx_cachep)
20440772 3304 goto fail_free_srb_mempool;
a9083016
GM		 3305 }
3306 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3307 ctx_cachep);
3308 if (!ha->ctx_mempool)
3309 goto fail_free_srb_mempool;
7c3df132
SK		 3310 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3311 "ctx_cachep=%p ctx_mempool=%p.\n",
3312 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3313 }
3314
e8711085
AV		 3315 /* Get memory for cached NVRAM */
3316 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3317 if (!ha->nvram)
a9083016 3318 goto fail_free_ctx_mempool;
e8711085 3319
e315cd28
AC		 3320 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3321 ha->pdev->device);
3322 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3323 DMA_POOL_SIZE, 8, 0);
3324 if (!ha->s_dma_pool)
3325 goto fail_free_nvram;
3326
7c3df132
SK		 3327 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3328 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3329 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3330
bad75002 3331 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3332 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3333 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3334 if (!ha->dl_dma_pool) {
7c3df132
SK		 3335 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3336 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3337 goto fail_s_dma_pool;
3338 }
3339
3340 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3341 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3342 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3343 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3344 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3345 goto fail_dl_dma_pool;
3346 }
7c3df132
SK		 3347 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3348 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3349 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3350 }
3351
e8711085
AV		 3352 /* Allocate memory for SNS commands */
3353 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3354 /* Get consistent memory allocated for SNS commands */
e8711085 3355 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3356 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3357 if (!ha->sns_cmd)
e315cd28 3358 goto fail_dma_pool;
7c3df132 3359 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3360 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3361 } else {
e315cd28 3362 /* Get consistent memory allocated for MS IOCB */
e8711085 3363 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3364 &ha->ms_iocb_dma);
e8711085 3365 if (!ha->ms_iocb)
e315cd28
AC		 3366 goto fail_dma_pool;
3367 /* Get consistent memory allocated for CT SNS commands */
e8711085 3368 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3369 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3370 if (!ha->ct_sns)
3371 goto fail_free_ms_iocb;
7c3df132
SK		 3372 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3373 "ms_iocb=%p ct_sns=%p.\n",
3374 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3375 }
3376
e315cd28 3377 /* Allocate memory for request ring */
73208dfd
AC		 3378 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3379 if (!*req) {
7c3df132
SK		 3380 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3381 "Failed to allocate memory for req.\n");
e315cd28
AC		 3382 goto fail_req;
3383 }
73208dfd
AC		 3384 (*req)->length = req_len;
3385 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3386 ((*req)->length + 1) * sizeof(request_t),
3387 &(*req)->dma, GFP_KERNEL);
3388 if (!(*req)->ring) {
7c3df132
SK		 3389 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3390 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3391 goto fail_req_ring;
3392 }
3393 /* Allocate memory for response ring */
73208dfd
AC		 3394 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3395 if (!*rsp) {
7c3df132
SK		 3396 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3397 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3398 goto fail_rsp;
3399 }
73208dfd
AC		 3400 (*rsp)->hw = ha;
3401 (*rsp)->length = rsp_len;
3402 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3403 ((*rsp)->length + 1) * sizeof(response_t),
3404 &(*rsp)->dma, GFP_KERNEL);
3405 if (!(*rsp)->ring) {
7c3df132
SK		 3406 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3407 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3408 goto fail_rsp_ring;
3409 }
73208dfd
AC		 3410 (*req)->rsp = *rsp;
3411 (*rsp)->req = *req;
7c3df132
SK		 3412 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3413 "req=%p req->length=%d req->ring=%p rsp=%p "
3414 "rsp->length=%d rsp->ring=%p.\n",
3415 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3416 (*rsp)->ring);
73208dfd
AC		 3417 /* Allocate memory for NVRAM data for vports */
3418 if (ha->nvram_npiv_size) {
3419 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3420 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3421 if (!ha->npiv_info) {
7c3df132
SK		 3422 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3423 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3424 goto fail_npiv_info;
3425 }
3426 } else
3427 ha->npiv_info = NULL;
e8711085 3428
b64b0e8f 3429 /* Get consistent memory allocated for EX-INIT-CB. */
6246b8a1 3430 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
b64b0e8f
AV		 3431 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3432 &ha->ex_init_cb_dma);
3433 if (!ha->ex_init_cb)
3434 goto fail_ex_init_cb;
7c3df132
SK		 3435 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3436 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3437 }
3438
a9083016
GM		 3439 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3440
5ff1d584
AV		 3441 /* Get consistent memory allocated for Async Port-Database. */
3442 if (!IS_FWI2_CAPABLE(ha)) {
3443 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3444 &ha->async_pd_dma);
3445 if (!ha->async_pd)
3446 goto fail_async_pd;
7c3df132
SK		 3447 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3448 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3449 }
3450
e315cd28 3451 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3452
3453 /* Allocate memory for our loop_id bitmap */
3454 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3455 GFP_KERNEL);
3456 if (!ha->loop_id_map)
20440772 3457 goto fail_loop_id_map;
5f16b331
CD		 3458 else {
3459 qla2x00_set_reserved_loop_ids(ha);
3460 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
daa12c3a 3461 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3462 }
3463
daa12c3a 3464 return 0;
e315cd28 3465
20440772
QT		 3466fail_loop_id_map:
3467 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 3468fail_async_pd:
3469 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3470fail_ex_init_cb:
3471 kfree(ha->npiv_info);
73208dfd
AC		 3472fail_npiv_info:
3473 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3474 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3475 (*rsp)->ring = NULL;
3476 (*rsp)->dma = 0;
e315cd28 3477fail_rsp_ring:
73208dfd 3478 kfree(*rsp);
e315cd28 3479fail_rsp:
73208dfd
AC		 3480 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3481 sizeof(request_t), (*req)->ring, (*req)->dma);
3482 (*req)->ring = NULL;
3483 (*req)->dma = 0;
e315cd28 3484fail_req_ring:
73208dfd 3485 kfree(*req);
e315cd28
AC		 3486fail_req:
3487 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3488 ha->ct_sns, ha->ct_sns_dma);
3489 ha->ct_sns = NULL;
3490 ha->ct_sns_dma = 0;
e8711085
AV		 3491fail_free_ms_iocb:
3492 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3493 ha->ms_iocb = NULL;
3494 ha->ms_iocb_dma = 0;
20440772
QT		 3495
3496 if (ha->sns_cmd)
3497 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3498 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 3499fail_dma_pool:
bad75002 3500 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3501 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3502 ha->fcp_cmnd_dma_pool = NULL;
3503 }
3504fail_dl_dma_pool:
bad75002 3505 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3506 dma_pool_destroy(ha->dl_dma_pool);
3507 ha->dl_dma_pool = NULL;
3508 }
3509fail_s_dma_pool:
e315cd28
AC		 3510 dma_pool_destroy(ha->s_dma_pool);
3511 ha->s_dma_pool = NULL;
e8711085
AV		 3512fail_free_nvram:
3513 kfree(ha->nvram);
3514 ha->nvram = NULL;
a9083016 3515fail_free_ctx_mempool:
20440772
QT		 3516 if (ha->ctx_mempool)
3517 mempool_destroy(ha->ctx_mempool);
a9083016 3518 ha->ctx_mempool = NULL;
e8711085 3519fail_free_srb_mempool:
20440772
QT		 3520 if (ha->srb_mempool)
3521 mempool_destroy(ha->srb_mempool);
e8711085 3522 ha->srb_mempool = NULL;
e8711085 3523fail_free_gid_list:
642ef983
CD		 3524 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3525 ha->gid_list,
e315cd28 3526 ha->gid_list_dma);
e8711085
AV		 3527 ha->gid_list = NULL;
3528 ha->gid_list_dma = 0;
2d70c103
NB		 3529fail_free_tgt_mem:
3530 qlt_mem_free(ha);
e315cd28
AC		 3531fail_free_init_cb:
3532 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3533 ha->init_cb_dma);
3534 ha->init_cb = NULL;
3535 ha->init_cb_dma = 0;
e8711085 3536fail:
7c3df132
SK		 3537 ql_log(ql_log_fatal, NULL, 0x0030,
3538 "Memory allocation failure.\n");
e8711085 3539 return -ENOMEM;
1da177e4
LT		 3540}
3541
3542/*
e30d1756
MI		 3543* qla2x00_free_fw_dump
3544* Frees fw dump stuff.
1da177e4
LT		 3545*
3546* Input:
e30d1756 3547* ha = adapter block pointer.
1da177e4 3548*/
a824ebb3 3549static void
e30d1756 3550qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3551{
df613b96
AV		 3552 if (ha->fce)
3553 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3554 ha->fce_dma);
df613b96 3555
a7a167bf
AV		 3556 if (ha->fw_dump) {
3557 if (ha->eft)
3558 dma_free_coherent(&ha->pdev->dev,
e30d1756 3559 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3560 vfree(ha->fw_dump);
3561 }
e30d1756
MI		 3562 ha->fce = NULL;
3563 ha->fce_dma = 0;
3564 ha->eft = NULL;
3565 ha->eft_dma = 0;
3566 ha->fw_dump = NULL;
3567 ha->fw_dumped = 0;
3568 ha->fw_dump_reading = 0;
3569}
3570
3571/*
3572* qla2x00_mem_free
3573* Frees all adapter allocated memory.
3574*
3575* Input:
3576* ha = adapter block pointer.
3577*/
3578static void
3579qla2x00_mem_free(struct qla_hw_data *ha)
3580{
3581 qla2x00_free_fw_dump(ha);
3582
81178772
SK		 3583 if (ha->mctp_dump)
3584 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3585 ha->mctp_dump_dma);
3586
e30d1756
MI		 3587 if (ha->srb_mempool)
3588 mempool_destroy(ha->srb_mempool);
a7a167bf 3589
11bbc1d8
AV		 3590 if (ha->dcbx_tlv)
3591 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3592 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3593
ce0423f4
AV		 3594 if (ha->xgmac_data)
3595 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3596 ha->xgmac_data, ha->xgmac_data_dma);
3597
1da177e4
LT		 3598 if (ha->sns_cmd)
3599 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3600 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3601
3602 if (ha->ct_sns)
3603 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3604 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3605
88729e53
AV		 3606 if (ha->sfp_data)
3607 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3608
1da177e4
LT		 3609 if (ha->ms_iocb)
3610 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3611
b64b0e8f 3612 if (ha->ex_init_cb)
a9083016
GM		 3613 dma_pool_free(ha->s_dma_pool,
3614 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3615
5ff1d584
AV		 3616 if (ha->async_pd)
3617 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3618
1da177e4
LT		 3619 if (ha->s_dma_pool)
3620 dma_pool_destroy(ha->s_dma_pool);
3621
1da177e4 3622 if (ha->gid_list)
642ef983
CD		 3623 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3624 ha->gid_list, ha->gid_list_dma);
1da177e4 3625
a9083016
GM		 3626 if (IS_QLA82XX(ha)) {
3627 if (!list_empty(&ha->gbl_dsd_list)) {
3628 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3629
3630 /* clean up allocated prev pool */
3631 list_for_each_entry_safe(dsd_ptr,
3632 tdsd_ptr, &ha->gbl_dsd_list, list) {
3633 dma_pool_free(ha->dl_dma_pool,
3634 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3635 list_del(&dsd_ptr->list);
3636 kfree(dsd_ptr);
3637 }
3638 }
3639 }
3640
3641 if (ha->dl_dma_pool)
3642 dma_pool_destroy(ha->dl_dma_pool);
3643
3644 if (ha->fcp_cmnd_dma_pool)
3645 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3646
3647 if (ha->ctx_mempool)
3648 mempool_destroy(ha->ctx_mempool);
3649
2d70c103
NB		 3650 qlt_mem_free(ha);
3651
e315cd28
AC		 3652 if (ha->init_cb)
3653 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3654 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3655 vfree(ha->optrom_buffer);
3656 kfree(ha->nvram);
73208dfd 3657 kfree(ha->npiv_info);
7a67735b 3658 kfree(ha->swl);
5f16b331 3659 kfree(ha->loop_id_map);
1da177e4 3660
e8711085 3661 ha->srb_mempool = NULL;
a9083016 3662 ha->ctx_mempool = NULL;
1da177e4
LT		 3663 ha->sns_cmd = NULL;
3664 ha->sns_cmd_dma = 0;
3665 ha->ct_sns = NULL;
3666 ha->ct_sns_dma = 0;
3667 ha->ms_iocb = NULL;
3668 ha->ms_iocb_dma = 0;
1da177e4
LT		 3669 ha->init_cb = NULL;
3670 ha->init_cb_dma = 0;
b64b0e8f
AV		 3671 ha->ex_init_cb = NULL;
3672 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3673 ha->async_pd = NULL;
3674 ha->async_pd_dma = 0;
1da177e4
LT		 3675
3676 ha->s_dma_pool = NULL;
a9083016
GM		 3677 ha->dl_dma_pool = NULL;
3678 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3679
1da177e4
LT		 3680 ha->gid_list = NULL;
3681 ha->gid_list_dma = 0;
2d70c103
NB		 3682
3683 ha->tgt.atio_ring = NULL;
3684 ha->tgt.atio_dma = 0;
3685 ha->tgt.tgt_vp_map = NULL;
e315cd28 3686}
1da177e4 3687
e315cd28
AC		 3688struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3689 struct qla_hw_data *ha)
3690{
3691 struct Scsi_Host *host;
3692 struct scsi_qla_host *vha = NULL;
854165f4 3693
e315cd28
AC		 3694 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3695 if (host == NULL) {
7c3df132
SK		 3696 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3697 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3698 goto fail;
3699 }
3700
3701 /* Clear our data area */
3702 vha = shost_priv(host);
3703 memset(vha, 0, sizeof(scsi_qla_host_t));
3704
3705 vha->host = host;
3706 vha->host_no = host->host_no;
3707 vha->hw = ha;
3708
3709 INIT_LIST_HEAD(&vha->vp_fcports);
3710 INIT_LIST_HEAD(&vha->work_list);
3711 INIT_LIST_HEAD(&vha->list);
3712
f999f4c1
AV		 3713 spin_lock_init(&vha->work_lock);
3714
e315cd28 3715 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3716 ql_dbg(ql_dbg_init, vha, 0x0041,
3717 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3718 vha->host, vha->hw, vha,
3719 dev_name(&(ha->pdev->dev)));
3720
e315cd28
AC		 3721 return vha;
3722
3723fail:
3724 return vha;
1da177e4
LT		 3725}
3726
01ef66bb 3727static struct qla_work_evt *
f999f4c1 3728qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3729{
3730 struct qla_work_evt *e;
feafb7b1
AE		 3731 uint8_t bail;
3732
3733 QLA_VHA_MARK_BUSY(vha, bail);
3734 if (bail)
3735 return NULL;
0971de7f 3736
f999f4c1 3737 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3738 if (!e) {
3739 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3740 return NULL;
feafb7b1 3741 }
0971de7f
AV		 3742
3743 INIT_LIST_HEAD(&e->list);
3744 e->type = type;
3745 e->flags = QLA_EVT_FLAG_FREE;
3746 return e;
3747}
3748
01ef66bb 3749static int
f999f4c1 3750qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3751{
f999f4c1 3752 unsigned long flags;
0971de7f 3753
f999f4c1 3754 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3755 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3756 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3757 qla2xxx_wake_dpc(vha);
f999f4c1 3758
0971de7f
AV		 3759 return QLA_SUCCESS;
3760}
3761
3762int
e315cd28 3763qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3764 u32 data)
3765{
3766 struct qla_work_evt *e;
3767
f999f4c1 3768 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3769 if (!e)
3770 return QLA_FUNCTION_FAILED;
3771
3772 e->u.aen.code = code;
3773 e->u.aen.data = data;
f999f4c1 3774 return qla2x00_post_work(vha, e);
0971de7f
AV		 3775}
3776
8a659571
AV		 3777int
3778qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3779{
3780 struct qla_work_evt *e;
3781
f999f4c1 3782 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3783 if (!e)
3784 return QLA_FUNCTION_FAILED;
3785
3786 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3787 return qla2x00_post_work(vha, e);
8a659571
AV		 3788}
3789
ac280b67
AV		 3790#define qla2x00_post_async_work(name, type) \
3791int qla2x00_post_async_##name##_work( \
3792 struct scsi_qla_host *vha, \
3793 fc_port_t *fcport, uint16_t *data) \
3794{ \
3795 struct qla_work_evt *e; \
3796 \
3797 e = qla2x00_alloc_work(vha, type); \
3798 if (!e) \
3799 return QLA_FUNCTION_FAILED; \
3800 \
3801 e->u.logio.fcport = fcport; \
3802 if (data) { \
3803 e->u.logio.data[0] = data[0]; \
3804 e->u.logio.data[1] = data[1]; \
3805 } \
3806 return qla2x00_post_work(vha, e); \
3807}
3808
3809qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3810qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3811qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3812qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3813qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3814qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3815
3420d36c
AV		 3816int
3817qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3818{
3819 struct qla_work_evt *e;
3820
3821 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3822 if (!e)
3823 return QLA_FUNCTION_FAILED;
3824
3825 e->u.uevent.code = code;
3826 return qla2x00_post_work(vha, e);
3827}
3828
3829static void
3830qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3831{
3832 char event_string[40];
3833 char *envp[] = { event_string, NULL };
3834
3835 switch (code) {
3836 case QLA_UEVENT_CODE_FW_DUMP:
3837 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3838 vha->host_no);
3839 break;
3840 default:
3841 /* do nothing */
3842 break;
3843 }
3844 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3845}
3846
8ae6d9c7
GM		 3847int
3848qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3849 uint32_t *data, int cnt)
3850{
3851 struct qla_work_evt *e;
3852
3853 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3854 if (!e)
3855 return QLA_FUNCTION_FAILED;
3856
3857 e->u.aenfx.evtcode = evtcode;
3858 e->u.aenfx.count = cnt;
3859 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3860 return qla2x00_post_work(vha, e);
3861}
3862
ac280b67 3863void
e315cd28 3864qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3865{
f999f4c1
AV		 3866 struct qla_work_evt *e, *tmp;
3867 unsigned long flags;
3868 LIST_HEAD(work);
0971de7f 3869
f999f4c1
AV		 3870 spin_lock_irqsave(&vha->work_lock, flags);
3871 list_splice_init(&vha->work_list, &work);
3872 spin_unlock_irqrestore(&vha->work_lock, flags);
3873
3874 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3875 list_del_init(&e->list);
0971de7f
AV		 3876
3877 switch (e->type) {
3878 case QLA_EVT_AEN:
e315cd28 3879 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3880 e->u.aen.code, e->u.aen.data);
3881 break;
8a659571
AV		 3882 case QLA_EVT_IDC_ACK:
3883 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3884 break;
ac280b67
AV		 3885 case QLA_EVT_ASYNC_LOGIN:
3886 qla2x00_async_login(vha, e->u.logio.fcport,
3887 e->u.logio.data);
3888 break;
3889 case QLA_EVT_ASYNC_LOGIN_DONE:
3890 qla2x00_async_login_done(vha, e->u.logio.fcport,
3891 e->u.logio.data);
3892 break;
3893 case QLA_EVT_ASYNC_LOGOUT:
3894 qla2x00_async_logout(vha, e->u.logio.fcport);
3895 break;
3896 case QLA_EVT_ASYNC_LOGOUT_DONE:
3897 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3898 e->u.logio.data);
3899 break;
5ff1d584
AV		 3900 case QLA_EVT_ASYNC_ADISC:
3901 qla2x00_async_adisc(vha, e->u.logio.fcport,
3902 e->u.logio.data);
3903 break;
3904 case QLA_EVT_ASYNC_ADISC_DONE:
3905 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3906 e->u.logio.data);
3907 break;
3420d36c
AV		 3908 case QLA_EVT_UEVENT:
3909 qla2x00_uevent_emit(vha, e->u.uevent.code);
3910 break;
8ae6d9c7
GM		 3911 case QLA_EVT_AENFX:
3912 qlafx00_process_aen(vha, e);
3913 break;
0971de7f
AV		 3914 }
3915 if (e->flags & QLA_EVT_FLAG_FREE)
3916 kfree(e);
feafb7b1
AE		 3917
3918 /* For each work completed decrement vha ref count */
3919 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3920 }
e315cd28 3921}
f999f4c1 3922
e315cd28
AC		 3923/* Relogins all the fcports of a vport
3924 * Context: dpc thread
3925 */
3926void qla2x00_relogin(struct scsi_qla_host *vha)
3927{
3928 fc_port_t *fcport;
c6b2fca8 3929 int status;
e315cd28
AC		 3930 uint16_t next_loopid = 0;
3931 struct qla_hw_data *ha = vha->hw;
ac280b67 3932 uint16_t data[2];
e315cd28
AC		 3933
3934 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3935 /*
3936 * If the port is not ONLINE then try to login
3937 * to it if we haven't run out of retries.
3938 */
5ff1d584
AV		 3939 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3940 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3941 fcport->login_retry--;
e315cd28 3942 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3943 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3944 ha->isp_ops->fabric_logout(vha,
3945 fcport->loop_id,
3946 fcport->d_id.b.domain,
3947 fcport->d_id.b.area,
3948 fcport->d_id.b.al_pa);
3949
03bcfb57
JC		 3950 if (fcport->loop_id == FC_NO_LOOP_ID) {
3951 fcport->loop_id = next_loopid =
3952 ha->min_external_loopid;
3953 status = qla2x00_find_new_loop_id(
3954 vha, fcport);
3955 if (status != QLA_SUCCESS) {
3956 /* Ran out of IDs to use */
3957 break;
3958 }
3959 }
3960
ac280b67 3961 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3962 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3963 data[0] = 0;
3964 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3965 status = qla2x00_post_async_login_work(
3966 vha, fcport, data);
3967 if (status == QLA_SUCCESS)
3968 continue;
3969 /* Attempt a retry. */
3970 status = 1;
aaf4d3e2 3971 } else {
ac280b67
AV		 3972 status = qla2x00_fabric_login(vha,
3973 fcport, &next_loopid);
aaf4d3e2
SK		 3974 if (status == QLA_SUCCESS) {
3975 int status2;
3976 uint8_t opts;
3977
3978 opts = 0;
3979 if (fcport->flags &
3980 FCF_FCP2_DEVICE)
3981 opts |= BIT_1;
03003960
SK		 3982 status2 =
3983 qla2x00_get_port_database(
3984 vha, fcport, opts);
aaf4d3e2
SK		 3985 if (status2 != QLA_SUCCESS)
3986 status = 1;
3987 }
3988 }
e315cd28
AC		 3989 } else
3990 status = qla2x00_local_device_login(vha,
3991 fcport);
3992
e315cd28
AC		 3993 if (status == QLA_SUCCESS) {
3994 fcport->old_loop_id = fcport->loop_id;
3995
7c3df132
SK		 3996 ql_dbg(ql_dbg_disc, vha, 0x2003,
3997 "Port login OK: logged in ID 0x%x.\n",
3998 fcport->loop_id);
e315cd28
AC		 3999
4000 qla2x00_update_fcport(vha, fcport);
4001
4002 } else if (status == 1) {
4003 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4004 /* retry the login again */
7c3df132
SK		 4005 ql_dbg(ql_dbg_disc, vha, 0x2007,
4006 "Retrying %d login again loop_id 0x%x.\n",
4007 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4008 } else {
4009 fcport->login_retry = 0;
4010 }
4011
4012 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4013 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4014 }
4015 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4016 break;
0971de7f 4017 }
0971de7f
AV		 4018}
4019
7d613ac6
SV		 4020/* Schedule work on any of the dpc-workqueues */
4021void
4022qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4023{
4024 struct qla_hw_data *ha = base_vha->hw;
4025
4026 switch (work_code) {
4027 case MBA_IDC_AEN: /* 0x8200 */
4028 if (ha->dpc_lp_wq)
4029 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4030 break;
4031
4032 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4033 if (!ha->flags.nic_core_reset_hdlr_active) {
4034 if (ha->dpc_hp_wq)
4035 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4036 } else
4037 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4038 "NIC Core reset is already active. Skip "
4039 "scheduling it again.\n");
4040 break;
4041 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4042 if (ha->dpc_hp_wq)
4043 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4044 break;
4045 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4046 if (ha->dpc_hp_wq)
4047 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4048 break;
4049 default:
4050 ql_log(ql_log_warn, base_vha, 0xb05f,
4051 "Unknow work-code=0x%x.\n", work_code);
4052 }
4053
4054 return;
4055}
4056
4057/* Work: Perform NIC Core Unrecoverable state handling */
4058void
4059qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4060{
4061 struct qla_hw_data *ha =
2ad1b67c 4062 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4063 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4064 uint32_t dev_state = 0;
4065
4066 qla83xx_idc_lock(base_vha, 0);
4067 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4068 qla83xx_reset_ownership(base_vha);
4069 if (ha->flags.nic_core_reset_owner) {
4070 ha->flags.nic_core_reset_owner = 0;
4071 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4072 QLA8XXX_DEV_FAILED);
4073 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4074 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4075 }
4076 qla83xx_idc_unlock(base_vha, 0);
4077}
4078
4079/* Work: Execute IDC state handler */
4080void
4081qla83xx_idc_state_handler_work(struct work_struct *work)
4082{
4083 struct qla_hw_data *ha =
2ad1b67c 4084 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4085 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4086 uint32_t dev_state = 0;
4087
4088 qla83xx_idc_lock(base_vha, 0);
4089 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4090 if (dev_state == QLA8XXX_DEV_FAILED ||
4091 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4092 qla83xx_idc_state_handler(base_vha);
4093 qla83xx_idc_unlock(base_vha, 0);
4094}
4095
fa492630 4096static int
7d613ac6
SV		 4097qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4098{
4099 int rval = QLA_SUCCESS;
4100 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4101 uint32_t heart_beat_counter1, heart_beat_counter2;
4102
4103 do {
4104 if (time_after(jiffies, heart_beat_wait)) {
4105 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4106 "Nic Core f/w is not alive.\n");
4107 rval = QLA_FUNCTION_FAILED;
4108 break;
4109 }
4110
4111 qla83xx_idc_lock(base_vha, 0);
4112 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4113 &heart_beat_counter1);
4114 qla83xx_idc_unlock(base_vha, 0);
4115 msleep(100);
4116 qla83xx_idc_lock(base_vha, 0);
4117 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4118 &heart_beat_counter2);
4119 qla83xx_idc_unlock(base_vha, 0);
4120 } while (heart_beat_counter1 == heart_beat_counter2);
4121
4122 return rval;
4123}
4124
4125/* Work: Perform NIC Core Reset handling */
4126void
4127qla83xx_nic_core_reset_work(struct work_struct *work)
4128{
4129 struct qla_hw_data *ha =
4130 container_of(work, struct qla_hw_data, nic_core_reset);
4131 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4132 uint32_t dev_state = 0;
4133
81178772
SK		 4134 if (IS_QLA2031(ha)) {
4135 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4136 ql_log(ql_log_warn, base_vha, 0xb081,
4137 "Failed to dump mctp\n");
4138 return;
4139 }
4140
7d613ac6
SV		 4141 if (!ha->flags.nic_core_reset_hdlr_active) {
4142 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4143 qla83xx_idc_lock(base_vha, 0);
4144 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4145 &dev_state);
4146 qla83xx_idc_unlock(base_vha, 0);
4147 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4148 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4149 "Nic Core f/w is alive.\n");
4150 return;
4151 }
4152 }
4153
4154 ha->flags.nic_core_reset_hdlr_active = 1;
4155 if (qla83xx_nic_core_reset(base_vha)) {
4156 /* NIC Core reset failed. */
4157 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4158 "NIC Core reset failed.\n");
4159 }
4160 ha->flags.nic_core_reset_hdlr_active = 0;
4161 }
4162}
4163
4164/* Work: Handle 8200 IDC aens */
4165void
4166qla83xx_service_idc_aen(struct work_struct *work)
4167{
4168 struct qla_hw_data *ha =
4169 container_of(work, struct qla_hw_data, idc_aen);
4170 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4171 uint32_t dev_state, idc_control;
4172
4173 qla83xx_idc_lock(base_vha, 0);
4174 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4175 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4176 qla83xx_idc_unlock(base_vha, 0);
4177 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4178 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4179 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4180 "Application requested NIC Core Reset.\n");
4181 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4182 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4183 QLA_SUCCESS) {
4184 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4185 "Other protocol driver requested NIC Core Reset.\n");
4186 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4187 }
4188 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4189 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4190 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4191 }
4192}
4193
4194static void
4195qla83xx_wait_logic(void)
4196{
4197 int i;
4198
4199 /* Yield CPU */
4200 if (!in_interrupt()) {
4201 /*
4202 * Wait about 200ms before retrying again.
4203 * This controls the number of retries for single
4204 * lock operation.
4205 */
4206 msleep(100);
4207 schedule();
4208 } else {
4209 for (i = 0; i < 20; i++)
4210 cpu_relax(); /* This a nop instr on i386 */
4211 }
4212}
4213
fa492630 4214static int
7d613ac6
SV		 4215qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4216{
4217 int rval;
4218 uint32_t data;
4219 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4220 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4221 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4222 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4223 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4224
4225 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4226 if (rval)
4227 return rval;
4228
4229 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4230 return QLA_SUCCESS;
4231 } else {
4232 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4233 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4234 data);
4235 if (rval)
4236 return rval;
4237
4238 msleep(200);
4239
4240 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4241 &data);
4242 if (rval)
4243 return rval;
4244
4245 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4246 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4247 ~(idc_lck_rcvry_stage_mask));
4248 rval = qla83xx_wr_reg(base_vha,
4249 QLA83XX_IDC_LOCK_RECOVERY, data);
4250 if (rval)
4251 return rval;
4252
4253 /* Forcefully perform IDC UnLock */
4254 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4255 &data);
4256 if (rval)
4257 return rval;
4258 /* Clear lock-id by setting 0xff */
4259 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4260 0xff);
4261 if (rval)
4262 return rval;
4263 /* Clear lock-recovery by setting 0x0 */
4264 rval = qla83xx_wr_reg(base_vha,
4265 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4266 if (rval)
4267 return rval;
4268 } else
4269 return QLA_SUCCESS;
4270 }
4271
4272 return rval;
4273}
4274
fa492630 4275static int
7d613ac6
SV		 4276qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4277{
4278 int rval = QLA_SUCCESS;
4279 uint32_t o_drv_lockid, n_drv_lockid;
4280 unsigned long lock_recovery_timeout;
4281
4282 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4283retry_lockid:
4284 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4285 if (rval)
4286 goto exit;
4287
4288 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4289 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4290 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4291 return QLA_SUCCESS;
4292 else
4293 return QLA_FUNCTION_FAILED;
4294 }
4295
4296 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4297 if (rval)
4298 goto exit;
4299
4300 if (o_drv_lockid == n_drv_lockid) {
4301 qla83xx_wait_logic();
4302 goto retry_lockid;
4303 } else
4304 return QLA_SUCCESS;
4305
4306exit:
4307 return rval;
4308}
4309
4310void
4311qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4312{
4313 uint16_t options = (requester_id << 15) | BIT_6;
4314 uint32_t data;
6c315553 4315 uint32_t lock_owner;
7d613ac6
SV		 4316 struct qla_hw_data *ha = base_vha->hw;
4317
4318 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4319retry_lock:
4320 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4321 == QLA_SUCCESS) {
4322 if (data) {
4323 /* Setting lock-id to our function-number */
4324 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4325 ha->portnum);
4326 } else {
6c315553
SK		 4327 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4328 &lock_owner);
7d613ac6 4329 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4330 "Failed to acquire IDC lock, acquired by %d, "
4331 "retrying...\n", lock_owner);
7d613ac6
SV		 4332
4333 /* Retry/Perform IDC-Lock recovery */
4334 if (qla83xx_idc_lock_recovery(base_vha)
4335 == QLA_SUCCESS) {
4336 qla83xx_wait_logic();
4337 goto retry_lock;
4338 } else
4339 ql_log(ql_log_warn, base_vha, 0xb075,
4340 "IDC Lock recovery FAILED.\n");
4341 }
4342
4343 }
4344
4345 return;
4346
4347 /* XXX: IDC-lock implementation using access-control mbx */
4348retry_lock2:
4349 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4350 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4351 "Failed to acquire IDC lock. retrying...\n");
4352 /* Retry/Perform IDC-Lock recovery */
4353 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4354 qla83xx_wait_logic();
4355 goto retry_lock2;
4356 } else
4357 ql_log(ql_log_warn, base_vha, 0xb076,
4358 "IDC Lock recovery FAILED.\n");
4359 }
4360
4361 return;
4362}
4363
4364void
4365qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4366{
4367 uint16_t options = (requester_id << 15) | BIT_7, retry;
4368 uint32_t data;
4369 struct qla_hw_data *ha = base_vha->hw;
4370
4371 /* IDC-unlock implementation using driver-unlock/lock-id
4372 * remote registers
4373 */
4374 retry = 0;
4375retry_unlock:
4376 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4377 == QLA_SUCCESS) {
4378 if (data == ha->portnum) {
4379 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4380 /* Clearing lock-id by setting 0xff */
4381 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4382 } else if (retry < 10) {
4383 /* SV: XXX: IDC unlock retrying needed here? */
4384
4385 /* Retry for IDC-unlock */
4386 qla83xx_wait_logic();
4387 retry++;
4388 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4389 "Failed to release IDC lock, retyring=%d\n", retry);
4390 goto retry_unlock;
4391 }
4392 } else if (retry < 10) {
4393 /* Retry for IDC-unlock */
4394 qla83xx_wait_logic();
4395 retry++;
4396 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4397 "Failed to read drv-lockid, retyring=%d\n", retry);
4398 goto retry_unlock;
4399 }
4400
4401 return;
4402
4403 /* XXX: IDC-unlock implementation using access-control mbx */
4404 retry = 0;
4405retry_unlock2:
4406 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4407 if (retry < 10) {
4408 /* Retry for IDC-unlock */
4409 qla83xx_wait_logic();
4410 retry++;
4411 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4412 "Failed to release IDC lock, retyring=%d\n", retry);
4413 goto retry_unlock2;
4414 }
4415 }
4416
4417 return;
4418}
4419
4420int
4421__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4422{
4423 int rval = QLA_SUCCESS;
4424 struct qla_hw_data *ha = vha->hw;
4425 uint32_t drv_presence;
4426
4427 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4428 if (rval == QLA_SUCCESS) {
4429 drv_presence |= (1 << ha->portnum);
4430 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4431 drv_presence);
4432 }
4433
4434 return rval;
4435}
4436
4437int
4438qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4439{
4440 int rval = QLA_SUCCESS;
4441
4442 qla83xx_idc_lock(vha, 0);
4443 rval = __qla83xx_set_drv_presence(vha);
4444 qla83xx_idc_unlock(vha, 0);
4445
4446 return rval;
4447}
4448
4449int
4450__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4451{
4452 int rval = QLA_SUCCESS;
4453 struct qla_hw_data *ha = vha->hw;
4454 uint32_t drv_presence;
4455
4456 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4457 if (rval == QLA_SUCCESS) {
4458 drv_presence &= ~(1 << ha->portnum);
4459 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4460 drv_presence);
4461 }
4462
4463 return rval;
4464}
4465
4466int
4467qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4468{
4469 int rval = QLA_SUCCESS;
4470
4471 qla83xx_idc_lock(vha, 0);
4472 rval = __qla83xx_clear_drv_presence(vha);
4473 qla83xx_idc_unlock(vha, 0);
4474
4475 return rval;
4476}
4477
fa492630 4478static void
7d613ac6
SV		 4479qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4480{
4481 struct qla_hw_data *ha = vha->hw;
4482 uint32_t drv_ack, drv_presence;
4483 unsigned long ack_timeout;
4484
4485 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4486 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4487 while (1) {
4488 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4489 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4490 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4491 break;
4492
4493 if (time_after_eq(jiffies, ack_timeout)) {
4494 ql_log(ql_log_warn, vha, 0xb067,
4495 "RESET ACK TIMEOUT! drv_presence=0x%x "
4496 "drv_ack=0x%x\n", drv_presence, drv_ack);
4497 /*
4498 * The function(s) which did not ack in time are forced
4499 * to withdraw any further participation in the IDC
4500 * reset.
4501 */
4502 if (drv_ack != drv_presence)
4503 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4504 drv_ack);
4505 break;
4506 }
4507
4508 qla83xx_idc_unlock(vha, 0);
4509 msleep(1000);
4510 qla83xx_idc_lock(vha, 0);
4511 }
4512
4513 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4514 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4515}
4516
fa492630 4517static int
7d613ac6
SV		 4518qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4519{
4520 int rval = QLA_SUCCESS;
4521 uint32_t idc_control;
4522
4523 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4524 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4525
4526 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4527 __qla83xx_get_idc_control(vha, &idc_control);
4528 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4529 __qla83xx_set_idc_control(vha, 0);
4530
4531 qla83xx_idc_unlock(vha, 0);
4532 rval = qla83xx_restart_nic_firmware(vha);
4533 qla83xx_idc_lock(vha, 0);
4534
4535 if (rval != QLA_SUCCESS) {
4536 ql_log(ql_log_fatal, vha, 0xb06a,
4537 "Failed to restart NIC f/w.\n");
4538 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4539 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4540 } else {
4541 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4542 "Success in restarting nic f/w.\n");
4543 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4544 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4545 }
4546
4547 return rval;
4548}
4549
4550/* Assumes idc_lock always held on entry */
4551int
4552qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4553{
4554 struct qla_hw_data *ha = base_vha->hw;
4555 int rval = QLA_SUCCESS;
4556 unsigned long dev_init_timeout;
4557 uint32_t dev_state;
4558
4559 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4560 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4561
4562 while (1) {
4563
4564 if (time_after_eq(jiffies, dev_init_timeout)) {
4565 ql_log(ql_log_warn, base_vha, 0xb06e,
4566 "Initialization TIMEOUT!\n");
4567 /* Init timeout. Disable further NIC Core
4568 * communication.
4569 */
4570 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4571 QLA8XXX_DEV_FAILED);
4572 ql_log(ql_log_info, base_vha, 0xb06f,
4573 "HW State: FAILED.\n");
4574 }
4575
4576 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4577 switch (dev_state) {
4578 case QLA8XXX_DEV_READY:
4579 if (ha->flags.nic_core_reset_owner)
4580 qla83xx_idc_audit(base_vha,
4581 IDC_AUDIT_COMPLETION);
4582 ha->flags.nic_core_reset_owner = 0;
4583 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4584 "Reset_owner reset by 0x%x.\n",
4585 ha->portnum);
4586 goto exit;
4587 case QLA8XXX_DEV_COLD:
4588 if (ha->flags.nic_core_reset_owner)
4589 rval = qla83xx_device_bootstrap(base_vha);
4590 else {
4591 /* Wait for AEN to change device-state */
4592 qla83xx_idc_unlock(base_vha, 0);
4593 msleep(1000);
4594 qla83xx_idc_lock(base_vha, 0);
4595 }
4596 break;
4597 case QLA8XXX_DEV_INITIALIZING:
4598 /* Wait for AEN to change device-state */
4599 qla83xx_idc_unlock(base_vha, 0);
4600 msleep(1000);
4601 qla83xx_idc_lock(base_vha, 0);
4602 break;
4603 case QLA8XXX_DEV_NEED_RESET:
4604 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4605 qla83xx_need_reset_handler(base_vha);
4606 else {
4607 /* Wait for AEN to change device-state */
4608 qla83xx_idc_unlock(base_vha, 0);
4609 msleep(1000);
4610 qla83xx_idc_lock(base_vha, 0);
4611 }
4612 /* reset timeout value after need reset handler */
4613 dev_init_timeout = jiffies +
4614 (ha->fcoe_dev_init_timeout * HZ);
4615 break;
4616 case QLA8XXX_DEV_NEED_QUIESCENT:
4617 /* XXX: DEBUG for now */
4618 qla83xx_idc_unlock(base_vha, 0);
4619 msleep(1000);
4620 qla83xx_idc_lock(base_vha, 0);
4621 break;
4622 case QLA8XXX_DEV_QUIESCENT:
4623 /* XXX: DEBUG for now */
4624 if (ha->flags.quiesce_owner)
4625 goto exit;
4626
4627 qla83xx_idc_unlock(base_vha, 0);
4628 msleep(1000);
4629 qla83xx_idc_lock(base_vha, 0);
4630 dev_init_timeout = jiffies +
4631 (ha->fcoe_dev_init_timeout * HZ);
4632 break;
4633 case QLA8XXX_DEV_FAILED:
4634 if (ha->flags.nic_core_reset_owner)
4635 qla83xx_idc_audit(base_vha,
4636 IDC_AUDIT_COMPLETION);
4637 ha->flags.nic_core_reset_owner = 0;
4638 __qla83xx_clear_drv_presence(base_vha);
4639 qla83xx_idc_unlock(base_vha, 0);
4640 qla8xxx_dev_failed_handler(base_vha);
4641 rval = QLA_FUNCTION_FAILED;
4642 qla83xx_idc_lock(base_vha, 0);
4643 goto exit;
4644 case QLA8XXX_BAD_VALUE:
4645 qla83xx_idc_unlock(base_vha, 0);
4646 msleep(1000);
4647 qla83xx_idc_lock(base_vha, 0);
4648 break;
4649 default:
4650 ql_log(ql_log_warn, base_vha, 0xb071,
4651 "Unknow Device State: %x.\n", dev_state);
4652 qla83xx_idc_unlock(base_vha, 0);
4653 qla8xxx_dev_failed_handler(base_vha);
4654 rval = QLA_FUNCTION_FAILED;
4655 qla83xx_idc_lock(base_vha, 0);
4656 goto exit;
4657 }
4658 }
4659
4660exit:
4661 return rval;
4662}
4663
1da177e4
LT		 4664/**************************************************************************
4665* qla2x00_do_dpc
4666* This kernel thread is a task that is schedule by the interrupt handler
4667* to perform the background processing for interrupts.
4668*
4669* Notes:
4670* This task always run in the context of a kernel thread. It
4671* is kick-off by the driver's detect code and starts up
4672* up one per adapter. It immediately goes to sleep and waits for
4673* some fibre event. When either the interrupt handler or
4674* the timer routine detects a event it will one of the task
4675* bits then wake us up.
4676**************************************************************************/
4677static int
4678qla2x00_do_dpc(void *data)
4679{
2c3dfe3f 4680 int rval;
e315cd28
AC		 4681 scsi_qla_host_t *base_vha;
4682 struct qla_hw_data *ha;
1da177e4 4683
e315cd28
AC		 4684 ha = (struct qla_hw_data *)data;
4685 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4686
1da177e4
LT		 4687 set_user_nice(current, -20);
4688
563585ec 4689 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4690 while (!kthread_should_stop()) {
7c3df132
SK		 4691 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4692 "DPC handler sleeping.\n");
1da177e4 4693
39a11240
CH		 4694 schedule();
4695 __set_current_state(TASK_RUNNING);
1da177e4 4696
c142caf0
AV		 4697 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4698 goto end_loop;
1da177e4 4699
85880801 4700 if (ha->flags.eeh_busy) {
7c3df132
SK		 4701 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4702 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4703 goto end_loop;
85880801
AV		 4704 }
4705
1da177e4
LT		 4706 ha->dpc_active = 1;
4707
5f28d2d7
SK		 4708 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4709 "DPC handler waking up, dpc_flags=0x%lx.\n",
4710 base_vha->dpc_flags);
1da177e4 4711
e315cd28 4712 qla2x00_do_work(base_vha);
0971de7f 4713
a9083016
GM		 4714 if (IS_QLA82XX(ha)) {
4715 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4716 &base_vha->dpc_flags)) {
4717 qla82xx_idc_lock(ha);
4718 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 4719 QLA8XXX_DEV_FAILED);
a9083016 4720 qla82xx_idc_unlock(ha);
7c3df132
SK		 4721 ql_log(ql_log_info, base_vha, 0x4004,
4722 "HW State: FAILED.\n");
a9083016
GM		 4723 qla82xx_device_state_handler(base_vha);
4724 continue;
4725 }
4726
4727 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4728 &base_vha->dpc_flags)) {
4729
7c3df132
SK		 4730 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4731 "FCoE context reset scheduled.\n");
a9083016
GM		 4732 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4733 &base_vha->dpc_flags))) {
4734 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4735 /* FCoE-ctx reset failed.
4736 * Escalate to chip-reset
4737 */
4738 set_bit(ISP_ABORT_NEEDED,
4739 &base_vha->dpc_flags);
4740 }
4741 clear_bit(ABORT_ISP_ACTIVE,
4742 &base_vha->dpc_flags);
4743 }
4744
7c3df132
SK		 4745 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4746 "FCoE context reset end.\n");
a9083016 4747 }
8ae6d9c7
GM		 4748 } else if (IS_QLAFX00(ha)) {
4749 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4750 &base_vha->dpc_flags)) {
4751 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4752 "Firmware Reset Recovery\n");
4753 if (qlafx00_reset_initialize(base_vha)) {
4754 /* Failed. Abort isp later. */
4755 if (!test_bit(UNLOADING,
4756 &base_vha->dpc_flags))
4757 set_bit(ISP_UNRECOVERABLE,
4758 &base_vha->dpc_flags);
4759 ql_dbg(ql_dbg_dpc, base_vha,
4760 0x4021,
4761 "Reset Recovery Failed\n");
4762 }
4763 }
4764
4765 if (test_and_clear_bit(FX00_TARGET_SCAN,
4766 &base_vha->dpc_flags)) {
4767 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4768 "ISPFx00 Target Scan scheduled\n");
4769 if (qlafx00_rescan_isp(base_vha)) {
4770 if (!test_bit(UNLOADING,
4771 &base_vha->dpc_flags))
4772 set_bit(ISP_UNRECOVERABLE,
4773 &base_vha->dpc_flags);
4774 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4775 "ISPFx00 Target Scan Failed\n");
4776 }
4777 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4778 "ISPFx00 Target Scan End\n");
4779 }
a9083016
GM		 4780 }
4781
e315cd28
AC		 4782 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4783 &base_vha->dpc_flags)) {
1da177e4 4784
7c3df132
SK		 4785 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4786 "ISP abort scheduled.\n");
1da177e4 4787 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4788 &base_vha->dpc_flags))) {
1da177e4 4789
a9083016 4790 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4791 /* failed. retry later */
4792 set_bit(ISP_ABORT_NEEDED,
e315cd28 4793 &base_vha->dpc_flags);
99363ef8 4794 }
e315cd28
AC		 4795 clear_bit(ABORT_ISP_ACTIVE,
4796 &base_vha->dpc_flags);
99363ef8
SJ		 4797 }
4798
7c3df132
SK		 4799 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4800 "ISP abort end.\n");
1da177e4
LT		 4801 }
4802
a394aac8
DJ		 4803 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4804 &base_vha->dpc_flags)) {
e315cd28 4805 qla2x00_update_fcports(base_vha);
c9c5ced9 4806 }
d97994dc 4807
2d70c103
NB		 4808 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4809 int ret;
4810 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4811 if (ret != QLA_SUCCESS)
4812 ql_log(ql_log_warn, base_vha, 0x121,
4813 "Failed to enable receiving of RSCN "
4814 "requests: 0x%x.\n", ret);
4815 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4816 }
4817
8ae6d9c7
GM		 4818 if (IS_QLAFX00(ha))
4819 goto loop_resync_check;
4820
579d12b5 4821 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4822 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4823 "Quiescence mode scheduled.\n");
8fcd6b8b
CD		 4824 if (IS_QLA82XX(ha)) {
4825 qla82xx_device_state_handler(base_vha);
4826 clear_bit(ISP_QUIESCE_NEEDED,
4827 &base_vha->dpc_flags);
4828 if (!ha->flags.quiesce_owner) {
4829 qla2x00_perform_loop_resync(base_vha);
4830
4831 qla82xx_idc_lock(ha);
4832 qla82xx_clear_qsnt_ready(base_vha);
4833 qla82xx_idc_unlock(ha);
4834 }
4835 } else {
4836 clear_bit(ISP_QUIESCE_NEEDED,
4837 &base_vha->dpc_flags);
4838 qla2x00_quiesce_io(base_vha);
579d12b5 4839 }
7c3df132
SK		 4840 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4841 "Quiescence mode end.\n");
579d12b5
SK		 4842 }
4843
e315cd28 4844 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 4845 &base_vha->dpc_flags) &&
e315cd28 4846 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 4847
7c3df132
SK		 4848 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4849 "Reset marker scheduled.\n");
e315cd28
AC		 4850 qla2x00_rst_aen(base_vha);
4851 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 4852 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4853 "Reset marker end.\n");
1da177e4
LT		 4854 }
4855
4856 /* Retry each device up to login retry count */
e315cd28
AC		 4857 if ((test_and_clear_bit(RELOGIN_NEEDED,
4858 &base_vha->dpc_flags)) &&
4859 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4860 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 4861
7c3df132
SK		 4862 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
4863 "Relogin scheduled.\n");
e315cd28 4864 qla2x00_relogin(base_vha);
7c3df132
SK		 4865 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
4866 "Relogin end.\n");
1da177e4 4867 }
8ae6d9c7 4868loop_resync_check:
e315cd28 4869 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 4870 &base_vha->dpc_flags)) {
1da177e4 4871
7c3df132
SK		 4872 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
4873 "Loop resync scheduled.\n");
1da177e4
LT		 4874
4875 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 4876 &base_vha->dpc_flags))) {
1da177e4 4877
e315cd28 4878 rval = qla2x00_loop_resync(base_vha);
1da177e4 4879
e315cd28
AC		 4880 clear_bit(LOOP_RESYNC_ACTIVE,
4881 &base_vha->dpc_flags);
1da177e4
LT		 4882 }
4883
7c3df132
SK		 4884 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
4885 "Loop resync end.\n");
1da177e4
LT		 4886 }
4887
8ae6d9c7
GM		 4888 if (IS_QLAFX00(ha))
4889 goto intr_on_check;
4890
e315cd28
AC		 4891 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
4892 atomic_read(&base_vha->loop_state) == LOOP_READY) {
4893 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
4894 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 4895 }
4896
3c290d0b
CD		 4897 if (test_and_clear_bit(HOST_RAMP_DOWN_QUEUE_DEPTH,
4898 &base_vha->dpc_flags)) {
4899 /* Prevents simultaneous ramp up and down */
4900 clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
4901 &base_vha->dpc_flags);
4902 qla2x00_host_ramp_down_queuedepth(base_vha);
4903 }
4904
4905 if (test_and_clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
4906 &base_vha->dpc_flags))
4907 qla2x00_host_ramp_up_queuedepth(base_vha);
8ae6d9c7 4908intr_on_check:
1da177e4 4909 if (!ha->interrupts_on)
fd34f556 4910 ha->isp_ops->enable_intrs(ha);
1da177e4 4911
e315cd28
AC		 4912 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
4913 &base_vha->dpc_flags))
4914 ha->isp_ops->beacon_blink(base_vha);
f6df144c 4915
8ae6d9c7
GM		 4916 if (!IS_QLAFX00(ha))
4917 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 4918
1da177e4 4919 ha->dpc_active = 0;
c142caf0 4920end_loop:
563585ec 4921 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 4922 } /* End of while(1) */
563585ec 4923 __set_current_state(TASK_RUNNING);
1da177e4 4924
7c3df132
SK		 4925 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
4926 "DPC handler exiting.\n");
1da177e4
LT		 4927
4928 /*
4929 * Make sure that nobody tries to wake us up again.
4930 */
1da177e4
LT		 4931 ha->dpc_active = 0;
4932
ac280b67
AV		 4933 /* Cleanup any residual CTX SRBs. */
4934 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4935
39a11240
CH		 4936 return 0;
4937}
4938
4939void
e315cd28 4940qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 4941{
e315cd28 4942 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 4943 struct task_struct *t = ha->dpc_thread;
4944
e315cd28 4945 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 4946 wake_up_process(t);
1da177e4
LT		 4947}
4948
1da177e4
LT		 4949/*
4950* qla2x00_rst_aen
4951* Processes asynchronous reset.
4952*
4953* Input:
4954* ha = adapter block pointer.
4955*/
4956static void
e315cd28 4957qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 4958{
e315cd28
AC		 4959 if (vha->flags.online && !vha->flags.reset_active &&
4960 !atomic_read(&vha->loop_down_timer) &&
4961 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 4962 do {
e315cd28 4963 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4964
4965 /*
4966 * Issue marker command only when we are going to start
4967 * the I/O.
4968 */
e315cd28
AC		 4969 vha->marker_needed = 1;
4970 } while (!atomic_read(&vha->loop_down_timer) &&
4971 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 4972 }
4973}
4974
1da177e4
LT		 4975/**************************************************************************
4976* qla2x00_timer
4977*
4978* Description:
4979* One second timer
4980*
4981* Context: Interrupt
4982***************************************************************************/
2c3dfe3f 4983void
e315cd28 4984qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 4985{
1da177e4 4986 unsigned long cpu_flags = 0;
1da177e4
LT		 4987 int start_dpc = 0;
4988 int index;
4989 srb_t *sp;
85880801 4990 uint16_t w;
e315cd28 4991 struct qla_hw_data *ha = vha->hw;
73208dfd 4992 struct req_que *req;
85880801 4993
a5b36321 4994 if (ha->flags.eeh_busy) {
7c3df132
SK		 4995 ql_dbg(ql_dbg_timer, vha, 0x6000,
4996 "EEH = %d, restarting timer.\n",
4997 ha->flags.eeh_busy);
a5b36321
LC		 4998 qla2x00_restart_timer(vha, WATCH_INTERVAL);
4999 return;
5000 }
5001
85880801
AV		 5002 /* Hardware read to raise pending EEH errors during mailbox waits. */
5003 if (!pci_channel_offline(ha->pdev))
5004 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 5005
cefcaba6
SK		 5006 /* Make sure qla82xx_watchdog is run only for physical port */
5007 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 5008 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5009 start_dpc++;
5010 qla82xx_watchdog(vha);
5011 }
5012
8ae6d9c7
GM		 5013 if (!vha->vp_idx && IS_QLAFX00(ha))
5014 qlafx00_timer_routine(vha);
5015
1da177e4 5016 /* Loop down handler. */
e315cd28 5017 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5018 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5019 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5020 && vha->flags.online) {
1da177e4 5021
e315cd28
AC		 5022 if (atomic_read(&vha->loop_down_timer) ==
5023 vha->loop_down_abort_time) {
1da177e4 5024
7c3df132
SK		 5025 ql_log(ql_log_info, vha, 0x6008,
5026 "Loop down - aborting the queues before time expires.\n");
1da177e4 5027
e315cd28
AC		 5028 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5029 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5030
f08b7251
AV		 5031 /*
5032 * Schedule an ISP abort to return any FCP2-device
5033 * commands.
5034 */
2c3dfe3f 5035 /* NPIV - scan physical port only */
e315cd28 5036 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5037 spin_lock_irqsave(&ha->hardware_lock,
5038 cpu_flags);
73208dfd 5039 req = ha->req_q_map[0];
2c3dfe3f 5040 for (index = 1;
8d93f550 5041 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5042 index++) {
5043 fc_port_t *sfcp;
5044
e315cd28 5045 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5046 if (!sp)
5047 continue;
9ba56b95 5048 if (sp->type != SRB_SCSI_CMD)
cf53b069 5049 continue;
2c3dfe3f 5050 sfcp = sp->fcport;
f08b7251 5051 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5052 continue;
bdf79621 5053
8f7daead
GM		 5054 if (IS_QLA82XX(ha))
5055 set_bit(FCOE_CTX_RESET_NEEDED,
5056 &vha->dpc_flags);
5057 else
5058 set_bit(ISP_ABORT_NEEDED,
e315cd28 5059 &vha->dpc_flags);
2c3dfe3f
SJ		 5060 break;
5061 }
5062 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5063 cpu_flags);
1da177e4 5064 }
1da177e4
LT		 5065 start_dpc++;
5066 }
5067
5068 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5069 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5070 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5071 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5072 "Loop down - aborting ISP.\n");
5073
8f7daead
GM		 5074 if (IS_QLA82XX(ha))
5075 set_bit(FCOE_CTX_RESET_NEEDED,
5076 &vha->dpc_flags);
5077 else
5078 set_bit(ISP_ABORT_NEEDED,
5079 &vha->dpc_flags);
1da177e4
LT		 5080 }
5081 }
7c3df132
SK		 5082 ql_dbg(ql_dbg_timer, vha, 0x600a,
5083 "Loop down - seconds remaining %d.\n",
5084 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 5085 }
5086
cefcaba6
SK		 5087 /* Check if beacon LED needs to be blinked for physical host only */
5088 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc
SK		 5089 /* There is no beacon_blink function for ISP82xx */
5090 if (!IS_QLA82XX(ha)) {
5091 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5092 start_dpc++;
5093 }
f6df144c
AV		 5094 }
5095
550bf57d 5096 /* Process any deferred work. */
e315cd28 5097 if (!list_empty(&vha->work_list))
550bf57d
AV		 5098 start_dpc++;
5099
1da177e4 5100 /* Schedule the DPC routine if needed */
e315cd28
AC		 5101 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5102 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5103 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5104 start_dpc ||
e315cd28
AC		 5105 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5106 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5107 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5108 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5109 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
3c290d0b
CD		 5110 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
5111 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags) ||
5112 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags))) {
7c3df132
SK		 5113 ql_dbg(ql_dbg_timer, vha, 0x600b,
5114 "isp_abort_needed=%d loop_resync_needed=%d "
5115 "fcport_update_needed=%d start_dpc=%d "
5116 "reset_marker_needed=%d",
5117 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5118 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5119 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5120 start_dpc,
5121 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5122 ql_dbg(ql_dbg_timer, vha, 0x600c,
5123 "beacon_blink_needed=%d isp_unrecoverable=%d "
5124 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3c290d0b
CD		 5125 "relogin_needed=%d, host_ramp_down_needed=%d "
5126 "host_ramp_up_needed=%d.\n",
7c3df132
SK		 5127 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5128 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5129 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5130 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3c290d0b
CD		 5131 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
5132 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags),
5133 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags));
e315cd28 5134 qla2xxx_wake_dpc(vha);
7c3df132 5135 }
1da177e4 5136
e315cd28 5137 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5138}
5139
5433383e
AV		 5140/* Firmware interface routines. */
5141
6246b8a1 5142#define FW_BLOBS 10
5433383e
AV		 5143#define FW_ISP21XX 0
5144#define FW_ISP22XX 1
5145#define FW_ISP2300 2
5146#define FW_ISP2322 3
48c02fde 5147#define FW_ISP24XX 4
c3a2f0df 5148#define FW_ISP25XX 5
3a03eb79 5149#define FW_ISP81XX 6
a9083016 5150#define FW_ISP82XX 7
6246b8a1
GM		 5151#define FW_ISP2031 8
5152#define FW_ISP8031 9
5433383e 5153
bb8ee499
AV		 5154#define FW_FILE_ISP21XX "ql2100_fw.bin"
5155#define FW_FILE_ISP22XX "ql2200_fw.bin"
5156#define FW_FILE_ISP2300 "ql2300_fw.bin"
5157#define FW_FILE_ISP2322 "ql2322_fw.bin"
5158#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5159#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5160#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5161#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5162#define FW_FILE_ISP2031 "ql2600_fw.bin"
5163#define FW_FILE_ISP8031 "ql8300_fw.bin"
bb8ee499 5164
e1e82b6f 5165static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5166
5167static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5168 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5169 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5170 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5171 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5172 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5173 { .name = FW_FILE_ISP25XX, },
3a03eb79 5174 { .name = FW_FILE_ISP81XX, },
a9083016 5175 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5176 { .name = FW_FILE_ISP2031, },
5177 { .name = FW_FILE_ISP8031, },
5433383e
AV		 5178};
5179
5180struct fw_blob *
e315cd28 5181qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5182{
e315cd28 5183 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5184 struct fw_blob *blob;
5185
5433383e
AV		 5186 if (IS_QLA2100(ha)) {
5187 blob = &qla_fw_blobs[FW_ISP21XX];
5188 } else if (IS_QLA2200(ha)) {
5189 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5190 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5191 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5192 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5193 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5194 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5195 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5196 } else if (IS_QLA25XX(ha)) {
5197 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5198 } else if (IS_QLA81XX(ha)) {
5199 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5200 } else if (IS_QLA82XX(ha)) {
5201 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5202 } else if (IS_QLA2031(ha)) {
5203 blob = &qla_fw_blobs[FW_ISP2031];
5204 } else if (IS_QLA8031(ha)) {
5205 blob = &qla_fw_blobs[FW_ISP8031];
8a655229
DC		 5206 } else {
5207 return NULL;
5433383e
AV		 5208 }
5209
e1e82b6f 5210 mutex_lock(&qla_fw_lock);
5433383e
AV		 5211 if (blob->fw)
5212 goto out;
5213
5214 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5215 ql_log(ql_log_warn, vha, 0x0063,
5216 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5217 blob->fw = NULL;
5218 blob = NULL;
5219 goto out;
5220 }
5221
5222out:
e1e82b6f 5223 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5224 return blob;
5225}
5226
5227static void
5228qla2x00_release_firmware(void)
5229{
5230 int idx;
5231
e1e82b6f 5232 mutex_lock(&qla_fw_lock);
5433383e 5233 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5234 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5235 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5236}
5237
14e660e6
SJ		 5238static pci_ers_result_t
5239qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5240{
85880801
AV		 5241 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5242 struct qla_hw_data *ha = vha->hw;
5243
7c3df132
SK		 5244 ql_dbg(ql_dbg_aer, vha, 0x9000,
5245 "PCI error detected, state %x.\n", state);
b9b12f73 5246
14e660e6
SJ		 5247 switch (state) {
5248 case pci_channel_io_normal:
85880801 5249 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5250 return PCI_ERS_RESULT_CAN_RECOVER;
5251 case pci_channel_io_frozen:
85880801 5252 ha->flags.eeh_busy = 1;
a5b36321
LC		 5253 /* For ISP82XX complete any pending mailbox cmd */
5254 if (IS_QLA82XX(ha)) {
7190575f 5255 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5256 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5257 qla82xx_clear_pending_mbx(vha);
a5b36321 5258 }
90a86fc0 5259 qla2x00_free_irqs(vha);
14e660e6 5260 pci_disable_device(pdev);
bddd2d65
LC		 5261 /* Return back all IOs */
5262 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5263 return PCI_ERS_RESULT_NEED_RESET;
5264 case pci_channel_io_perm_failure:
85880801
AV		 5265 ha->flags.pci_channel_io_perm_failure = 1;
5266 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5267 return PCI_ERS_RESULT_DISCONNECT;
5268 }
5269 return PCI_ERS_RESULT_NEED_RESET;
5270}
5271
5272static pci_ers_result_t
5273qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5274{
5275 int risc_paused = 0;
5276 uint32_t stat;
5277 unsigned long flags;
e315cd28
AC		 5278 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5279 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5280 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5281 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5282
bcc5b6d3
SK		 5283 if (IS_QLA82XX(ha))
5284 return PCI_ERS_RESULT_RECOVERED;
5285
14e660e6
SJ		 5286 spin_lock_irqsave(&ha->hardware_lock, flags);
5287 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5288 stat = RD_REG_DWORD(&reg->hccr);
5289 if (stat & HCCR_RISC_PAUSE)
5290 risc_paused = 1;
5291 } else if (IS_QLA23XX(ha)) {
5292 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5293 if (stat & HSR_RISC_PAUSED)
5294 risc_paused = 1;
5295 } else if (IS_FWI2_CAPABLE(ha)) {
5296 stat = RD_REG_DWORD(&reg24->host_status);
5297 if (stat & HSRX_RISC_PAUSED)
5298 risc_paused = 1;
5299 }
5300 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5301
5302 if (risc_paused) {
7c3df132
SK		 5303 ql_log(ql_log_info, base_vha, 0x9003,
5304 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5305 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5306
5307 return PCI_ERS_RESULT_NEED_RESET;
5308 } else
5309 return PCI_ERS_RESULT_RECOVERED;
5310}
5311
fa492630
SK		 5312static uint32_t
5313qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5314{
5315 uint32_t rval = QLA_FUNCTION_FAILED;
5316 uint32_t drv_active = 0;
5317 struct qla_hw_data *ha = base_vha->hw;
5318 int fn;
5319 struct pci_dev *other_pdev = NULL;
5320
7c3df132
SK		 5321 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5322 "Entered %s.\n", __func__);
a5b36321
LC		 5323
5324 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5325
5326 if (base_vha->flags.online) {
5327 /* Abort all outstanding commands,
5328 * so as to be requeued later */
5329 qla2x00_abort_isp_cleanup(base_vha);
5330 }
5331
5332
5333 fn = PCI_FUNC(ha->pdev->devfn);
5334 while (fn > 0) {
5335 fn--;
7c3df132
SK		 5336 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5337 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5338 other_pdev =
5339 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5340 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5341 fn));
5342
5343 if (!other_pdev)
5344 continue;
5345 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5346 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5347 "Found PCI func available and enable at 0x%x.\n",
5348 fn);
a5b36321
LC		 5349 pci_dev_put(other_pdev);
5350 break;
5351 }
5352 pci_dev_put(other_pdev);
5353 }
5354
5355 if (!fn) {
5356 /* Reset owner */
7c3df132
SK		 5357 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5358 "This devfn is reset owner = 0x%x.\n",
5359 ha->pdev->devfn);
a5b36321
LC		 5360 qla82xx_idc_lock(ha);
5361
5362 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5363 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5364
5365 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5366 QLA82XX_IDC_VERSION);
5367
5368 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5369 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5370 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5371
5372 qla82xx_idc_unlock(ha);
5373 /* Reset if device is not already reset
5374 * drv_active would be 0 if a reset has already been done
5375 */
5376 if (drv_active)
5377 rval = qla82xx_start_firmware(base_vha);
5378 else
5379 rval = QLA_SUCCESS;
5380 qla82xx_idc_lock(ha);
5381
5382 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5383 ql_log(ql_log_info, base_vha, 0x900b,
5384 "HW State: FAILED.\n");
a5b36321
LC		 5385 qla82xx_clear_drv_active(ha);
5386 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5387 QLA8XXX_DEV_FAILED);
a5b36321 5388 } else {
7c3df132
SK		 5389 ql_log(ql_log_info, base_vha, 0x900c,
5390 "HW State: READY.\n");
a5b36321 5391 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5392 QLA8XXX_DEV_READY);
a5b36321 5393 qla82xx_idc_unlock(ha);
7190575f 5394 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5395 rval = qla82xx_restart_isp(base_vha);
5396 qla82xx_idc_lock(ha);
5397 /* Clear driver state register */
5398 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5399 qla82xx_set_drv_active(base_vha);
5400 }
5401 qla82xx_idc_unlock(ha);
5402 } else {
7c3df132
SK		 5403 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5404 "This devfn is not reset owner = 0x%x.\n",
5405 ha->pdev->devfn);
a5b36321 5406 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5407 QLA8XXX_DEV_READY)) {
7190575f 5408 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5409 rval = qla82xx_restart_isp(base_vha);
5410 qla82xx_idc_lock(ha);
5411 qla82xx_set_drv_active(base_vha);
5412 qla82xx_idc_unlock(ha);
5413 }
5414 }
5415 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5416
5417 return rval;
5418}
5419
14e660e6
SJ		 5420static pci_ers_result_t
5421qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5422{
5423 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5424 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5425 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5426 struct rsp_que *rsp;
5427 int rc, retries = 10;
09483916 5428
7c3df132
SK		 5429 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5430 "Slot Reset.\n");
85880801 5431
90a86fc0
JC		 5432 /* Workaround: qla2xxx driver which access hardware earlier
5433 * needs error state to be pci_channel_io_online.
5434 * Otherwise mailbox command timesout.
5435 */
5436 pdev->error_state = pci_channel_io_normal;
5437
5438 pci_restore_state(pdev);
5439
8c1496bd
RL		 5440 /* pci_restore_state() clears the saved_state flag of the device
5441 * save restored state which resets saved_state flag
5442 */
5443 pci_save_state(pdev);
5444
09483916
BH		 5445 if (ha->mem_only)
5446 rc = pci_enable_device_mem(pdev);
5447 else
5448 rc = pci_enable_device(pdev);
14e660e6 5449
09483916 5450 if (rc) {
7c3df132 5451 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5452 "Can't re-enable PCI device after reset.\n");
a5b36321 5453 goto exit_slot_reset;
14e660e6 5454 }
14e660e6 5455
90a86fc0
JC		 5456 rsp = ha->rsp_q_map[0];
5457 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5458 goto exit_slot_reset;
90a86fc0 5459
e315cd28 5460 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5461 goto exit_slot_reset;
5462
5463 if (IS_QLA82XX(ha)) {
5464 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5465 ret = PCI_ERS_RESULT_RECOVERED;
5466 goto exit_slot_reset;
5467 } else
5468 goto exit_slot_reset;
5469 }
14e660e6 5470
90a86fc0
JC		 5471 while (ha->flags.mbox_busy && retries--)
5472 msleep(1000);
85880801 5473
e315cd28 5474 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5475 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5476 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5477 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5478
90a86fc0 5479
a5b36321 5480exit_slot_reset:
7c3df132
SK		 5481 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5482 "slot_reset return %x.\n", ret);
85880801 5483
14e660e6
SJ		 5484 return ret;
5485}
5486
5487static void
5488qla2xxx_pci_resume(struct pci_dev *pdev)
5489{
e315cd28
AC		 5490 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5491 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5492 int ret;
5493
7c3df132
SK		 5494 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5495 "pci_resume.\n");
85880801 5496
e315cd28 5497 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5498 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5499 ql_log(ql_log_fatal, base_vha, 0x9002,
5500 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5501 }
85880801 5502
3e46f031
LC		 5503 pci_cleanup_aer_uncorrect_error_status(pdev);
5504
85880801 5505 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5506}
5507
a55b2d21 5508static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5509 .error_detected = qla2xxx_pci_error_detected,
5510 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5511 .slot_reset = qla2xxx_pci_slot_reset,
5512 .resume = qla2xxx_pci_resume,
5513};
5514
5433383e 5515static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5516 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5517 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5518 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5519 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5520 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5521 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5522 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5523 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5524 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5525 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5526 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5527 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5528 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5529 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5530 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5531 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5532 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5533 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
5433383e
AV		 5534 { 0 },
5535};
5536MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5537
fca29703 5538static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5539 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5540 .driver = {
5541 .owner = THIS_MODULE,
5542 },
fca29703 5543 .id_table = qla2xxx_pci_tbl,
7ee61397 5544 .probe = qla2x00_probe_one,
4c993f76 5545 .remove = qla2x00_remove_one,
e30d1756 5546 .shutdown = qla2x00_shutdown,
14e660e6 5547 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5548};
5549
75ef9de1 5550static const struct file_operations apidev_fops = {
6a03b4cd 5551 .owner = THIS_MODULE,
6038f373 5552 .llseek = noop_llseek,
6a03b4cd
HZ		 5553};
5554
1da177e4
LT		 5555/**
5556 * qla2x00_module_init - Module initialization.
5557 **/
5558static int __init
5559qla2x00_module_init(void)
5560{
fca29703
AV		 5561 int ret = 0;
5562
1da177e4 5563 /* Allocate cache for SRBs. */
354d6b21 5564 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5565 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5566 if (srb_cachep == NULL) {
7c3df132
SK		 5567 ql_log(ql_log_fatal, NULL, 0x0001,
5568 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5569 return -ENOMEM;
5570 }
5571
2d70c103
NB		 5572 /* Initialize target kmem_cache and mem_pools */
5573 ret = qlt_init();
5574 if (ret < 0) {
5575 kmem_cache_destroy(srb_cachep);
5576 return ret;
5577 } else if (ret > 0) {
5578 /*
5579 * If initiator mode is explictly disabled by qlt_init(),
5580 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5581 * performing scsi_scan_target() during LOOP UP event.
5582 */
5583 qla2xxx_transport_functions.disable_target_scan = 1;
5584 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5585 }
5586
1da177e4
LT		 5587 /* Derive version string. */
5588 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5589 if (ql2xextended_error_logging)
0181944f
AV		 5590 strcat(qla2x00_version_str, "-debug");
5591
1c97a12a
AV		 5592 qla2xxx_transport_template =
5593 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5594 if (!qla2xxx_transport_template) {
5595 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5596 ql_log(ql_log_fatal, NULL, 0x0002,
5597 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5598 qlt_exit();
1da177e4 5599 return -ENODEV;
2c3dfe3f 5600 }
6a03b4cd
HZ		 5601
5602 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5603 if (apidev_major < 0) {
7c3df132
SK		 5604 ql_log(ql_log_fatal, NULL, 0x0003,
5605 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5606 }
5607
2c3dfe3f
SJ		 5608 qla2xxx_transport_vport_template =
5609 fc_attach_transport(&qla2xxx_transport_vport_functions);
5610 if (!qla2xxx_transport_vport_template) {
5611 kmem_cache_destroy(srb_cachep);
2d70c103 5612 qlt_exit();
2c3dfe3f 5613 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5614 ql_log(ql_log_fatal, NULL, 0x0004,
5615 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5616 return -ENODEV;
2c3dfe3f 5617 }
7c3df132
SK		 5618 ql_log(ql_log_info, NULL, 0x0005,
5619 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5620 qla2x00_version_str);
7ee61397 5621 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5622 if (ret) {
5623 kmem_cache_destroy(srb_cachep);
2d70c103 5624 qlt_exit();
fca29703 5625 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5626 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5627 ql_log(ql_log_fatal, NULL, 0x0006,
5628 "pci_register_driver failed...ret=%d Failing load!.\n",
5629 ret);
fca29703
AV		 5630 }
5631 return ret;
1da177e4
LT		 5632}
5633
5634/**
5635 * qla2x00_module_exit - Module cleanup.
5636 **/
5637static void __exit
5638qla2x00_module_exit(void)
5639{
6a03b4cd 5640 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5641 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5642 qla2x00_release_firmware();
354d6b21 5643 kmem_cache_destroy(srb_cachep);
2d70c103 5644 qlt_exit();
a9083016
GM		 5645 if (ctx_cachep)
5646 kmem_cache_destroy(ctx_cachep);
1da177e4 5647 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5648 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5649}
5650
5651module_init(qla2x00_module_init);
5652module_exit(qla2x00_module_exit);
5653
5654MODULE_AUTHOR("QLogic Corporation");
5655MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5656MODULE_LICENSE("GPL");
5657MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5658MODULE_FIRMWARE(FW_FILE_ISP21XX);
5659MODULE_FIRMWARE(FW_FILE_ISP22XX);
5660MODULE_FIRMWARE(FW_FILE_ISP2300);
5661MODULE_FIRMWARE(FW_FILE_ISP2322);
5662MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5663MODULE_FIRMWARE(FW_FILE_ISP25XX);
kernel source for telekom puls (alcatel/mediatek)